ec010505 microprocessors and applications module 1

7/28/2019 Ec010505 Microprocessors and Applications Module 1

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ECO1O 505 MICROPROCESSOR AND ITS APPLICATIONS

MODULE-1

1. WHAT ARE DIFFERENT TYPES OF BUSES AND THEIR SPECIALTIES IN 8085? (5 mark

question)

8085 Bus Structure:

Address Bus:

• The address bus is a group of 16 lines generally identified as A0 to A15.

• The address bus is unidirectional: bits flow in one direction-from the MPU to peripheral

devices.

• The MPU uses the address bus to perform the first function: identifying a peripheral or a

memory location.

Data Bus:

• The data bus is a group of eight lines used for data flow.

• These lines are bi-directional - data flow in both directions between the MPU and memory

and peripheral devices.

• The MPU uses the data bus to perform the second function: transferring binary information.

• The eight data lines enable the MPU to manipulate 8-bit data ranging from 00 to FF (28 =

256 numbers).

• The largest number that can appear on the data bus is 11111111.

Control Bus:

•

The control bus carries synchronization signals and providing timing signals.• The MPU generates specific control signals for every operation it performs. These signals are

used to identify a device type with which the MPU wants to communicate.

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DIVYA RAPECEMATHA COLLEGE OF TECHNOLOGY




2. LIST AND EXPLAIN DIFFERENT REGISTERS IN 8085? (5 mark question)

Registers of 8085:General purpose registers:

• The 8085 have six general-purpose registers to store 8-bit data during program execution.

• These registers are identified as B, C, D, E, H, and L.

• They can be combined as register pairs-BC, DE, and HL-to perform some 16-bit operations.

Temporary registers:

• They are used to hold 8 bit data during execution of some instructions and are not available

to the programmer.Special purpose registers:

Accumulator:

• It is used to store arithmetic and logical and i/o operations

Flag Register

•8 bit register –shows the status of the microprocessor before/after an operation

• S (sign flag), Z (zero flag), AC (auxiliary carry flag), P (parity flag) & CY (carry flag)

register16bit register:

• Program counter: always point to the address of the next instruction to be fetched

• Stack pointer: it holds the address of the most recent stack entry.

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3. WHAT ARE THE ROLES OF VARIOUS FLAGS IN 8085? (5 mark question)

Flags:

• The ALU includes five flip-flops that are set or reset according to the result of an operation.

• The microprocessor uses the flags for testing the data conditions.

• They are Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags. The most

commonly used flags are Sign, Zero, and Carry.





The bit position for the flags in flag register is,

1. Sign Flag (S):After execution of any arithmetic and logical operation, if D7 of the result is 1, the sign flag is set.Otherwise it is reset.

D7 is reserved for indicating the sign; the remaining is the magnitude of number.If D7 is 1, the number will be viewed as negative number. If D7 is 0, the number will be viewed as

positive number.

2. Zero Flag (z):If the result of arithmetic and logical operation is zero, then zero flag is set otherwise it is reset.

3. Auxiliary Carry Flag (AC):

If D3 generates any carry when doing any arithmetic and logical operation, this flag is set.Otherwise it is reset.

4. Parity Flag (P):

If the result of arithmetic and logical operation contains even number of 1's then this flag will beset and if it is odd number of 1's it will be reset.

5. Carry Flag (CY):

If any arithmetic and logical operation result any carry then carry flag is set otherwise it is reset. ______________________________________________________________________

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4. WHAT IS ALU EXPLAIN ITS FUNCTIONS? (3 mark question)

ALU performs arithmetic and logical functions on eight bit variables.It has two inputs

1. Accumulator (A):

• The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU).

• This register is used to store 8-bit data and to perform arithmetic and logical operations.

• The result of an operation is stored in the accumulator.

2. TEMPORY REGISTER:

• It is used to hold temporary data and it is not accessible to the programmer

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5. WHAT ARE THE CONTROL SIGNALS AVAILABLE FOR MEMORY AND I/O OPERATIONS

IN 8085? (3 mark question)





• RD (output 3-state, active low) - Read memory or IO device.

• This indicates that the selected memory location or I/O device is to be read and that the

data bus is ready for accepting data from the memory or I/O device.

• WR (output 3-state, active low) - Write memory or IO device.

• This indicates that the data on the data bus is to be written into the selected memory

location or I/O device.

• IO/M (output) - Select memory or an IO device.• This status signal indicates that the read / write operation relates to whether the memory or

I/O device.

• It goes high to indicate an I/O operation.

• It goes low for memory operations.

• By combing RD,WR,IO/M we can generate the control signals

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5. WHAT ARE THE FUNCTIONS OF (3 MARK QUESTION?)

TRAP ii) SOD iii) INTA IV) Ready

TRAP:

• TRAP is a non-maskable interrupt of 8085. It is not disabled by processor reset or after

recognition of interrupt.

INTA

• On receipt of an interrupt, the microprocessor acknowledges the interrupt by the active low

INTA (Interrupt Acknowledge) signal.

READY (input)

• Memory and I/O devices will have slower response compared to microprocessors.

• Before completing the present job such a slow peripheral may not be able to handle further

data or control signal from CPU.

•

The processor sets the READY signal after completing the present job to access the data.• The microprocessor enters into WAIT state while the READY pin is disabled.

SOD:

• SOD (Serial Output Data) – This is an output signal which enables the transmission of serial

data bit by bit to the external device.





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6. EXPLAIN THE FOLLOWING SIGNALS IN 8085? (3 MARK QUESTION)

ALE ii) READY iii) HOLD IV) IO/M

READY (input)• Memory and I/O devices will have slower response compared to microprocessors.

• Before completing the present job such a slow peripheral may not be able to handle further

data or control signal from CPU.

• The processor sets the READY signal after completing the present job to access the data.

• The microprocessor enters into WAIT state while the READY pin is disabled.

HOLD:

• HOLD signal is generated by the DMA controller circuit. On receipt of this signal, the

microprocessor acknowledges the request by sending out HLDA signal and leaves out the

control of the buses. After the HLDA signal the DMA controller starts the direct transfer of

data.

ALE:

• In 8085, ADo to AD7 lines are multiplexed and lower half of address (Ao to A7) is available

only during T1 of the machine cycle.

• The latching of lower half address from the multiplexed address lines by using ALE signal.

IO/M

• IO/M (output) - Select memory or an IO device.• This status signal indicates that the read / write operation relates to whether the memory or

I/O device.

• It goes high to indicate an I/O operation.

• It goes low for memory operations.

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7. EXPLAIN WITH SCHEMATIC HOW ADDRESS AND DATA SIGNALS CAN BE GENERATED

FROM 8085 COMMON ADDRESS DATA LINES?(5 mark question)

• The high order address is placed on the address bus and hold for 3 clk periods,





• The low order address is lost after the first clk period, this address needs to be hold

however we need to use latch

• The address AD7 –AD0 is connected as inputs to the latch 74LS373.

• The ALE signal is connected to the enable (G) pin of the latch and the OC –Output control –

of the latch is grounded

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8. EXPLAIN THE FUNCTION OF ALE IN 8085? (3 mark question)

• AD7–AD0 lines are serving a dual purpose and that they need to be demultiplexed to get all

the information.

• The high order bits of the address remain on the bus for three clock periods.

• However, the low order bits remain for only one clock period and they would be lost if they

are not saved externally.

• Also, notice that the low order bits of the address disappear when they are needed most.





• To make sure we have the entire address for the full three clock cycles, we will use an

external latch to save the value of AD7–AD0 when it is carrying the address bits. We use

the ALE signal to enable this latch.

• Given that ALE operates as a pulse during T1, we will be able to latch the address.

Then when ALE goes low, the address is saved and the AD7–AD0 lines can be used for their

purpose as the bi-directional data lines

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9. WHAT ARE MASK ABLE AND NON MASK ABLE INTERRUPTS IN 8085? EXPLAIN BY

INDICATING THE ORDER OF THEIR PRIORITIES?(3 MARK QUESTION)

TRAP: non maskable interrupt & it has the highest priority

RST 7.5:maskable interrupt

RST 6.5: maskable interrupt

RST 5.5: maskable interrupt

INTR: maskable interrupt with the lowest priority among all

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10. LIST THE INTERRUPTS ACCORDING TO THEIR PRIORITY?( 3 MARK QUESTION)

• They are the signals initiated by an external device to request the microprocessor to do a

particular task or work.

• There are five hardware interrupts called,



11.WHAT ARE TRISTATE DEVICES? EXPLAIN? (3 MARK QUESTION)





Tri state devices:

• 3 output states are high & low states and additionally a high impedance state.

• When enable E is high the gate is enabled and the output Q can be 1 or 0 (if A is 0, Q is 1,

otherwise Q is 0). However, when E is low the gate is disabled and the output Q enters into ahigh impedance state.

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12. What are the status signals of 8085? Explain the function?( 3 MARK QUESTION)

• It is used to know the type of current operation of the microprocessor.

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13. WITH A NEAT DIAGRAM EXPLAIN THE INTERNAL ARCHITECTURE OF 8085?(12markquestion)





Temporary registers:They are used to hold 8 bit data during execution of some instructions and are not available to the

programmer.Special purpose registers:

Accumulator:

• It is used to store arithmetic and logical and i/o operations

Flag Register• 8 bit register –shows the status of the microprocessor before/after an operation

• S (sign flag), Z (zero flag), AC (auxiliary carry flag), P (parity flag) & CY (carry flag)

Register16bit register:

• Program counter: always point to the address of the next instruction to be fetched

• Stack pointer: it holds the address of the most recent stack entry.

Instruction registers:

• The opcode of the instruction being processed is stored in these register.

Alu:• Performs arithmetical and logical functions on eight bit variables;

Instruction decoder:

It decodes the instruction and accordingly gives the timing and control signals which control theregister ,data buffer s ,ALU and external peripherals depending on the nature of instruction.

Address buffer:

• it is used to drive external higher order address bus.it is also used to latch higher order bus

under certain conditions such as reset ,hold,?&halt when address lines are nt in use

Address/data buffer:

• It is used to drive multiplexed address/ data bus.

Incrementer/decrementer address latch:

• This is used to increment or decrement the contents of program counter or stach pointer as

a part of instruction related to them.

Interrupt control:

• There are five hardware interrupts called,







Serial control:

• SID (input) - Serial input data line

• SOD (output) - Serial output data line

• These signals are used for serial communication.

Timing and control circuitary:

• The control circuitry in the 8085 processor is responsible for all operations .the control

circuitry and its operation are synchronized with the help of clock.

The operations are:

• Control of fetching and decoding operations

• Generating appropriate signals for instruction execution and generating signals required for

interfacing external devices to the processor

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15. WITH A TIMING DIAGRAM EXPLAIN THE OPERATIONS TAKING PLACE WHEN THEINSTRUCTION EXECUTED? (12mark question)

16.SKETCH THE BASIC TIMING DIAGRAM FOR M1(FETCH CYCLE) ,M2(READ CYCLE)SHOWING IO/M,ALE,S1,S0,RD, AD0-AD7,A8-A15 SIGNAL WAVEFORMS WITH RESPECT

TO THE CLOCK OF THE SYSTEM? EXPLAIN THEM? (12mark question)

17.DEFINE INSTRUCTION CYCLE, MACHINE CYCLE AND T-STATE & SHOW IN THE TIMING

DIAGRAM DRAWN? (12mark question)

• Each instruction of the 8085 processor consists of one to five machine cycles, i.e., when the

8085 processor executes an instruction, it will execute some of the machine cycles in aspecific order.

• The processor takes a definite time to execute the machine cycles. The time taken by the

processor to execute a machine cycle is expressed in T-states.





• One T-state is equal to the time period of the internal clock signal of the processor.

• The T-state starts at the falling edge of a clock

Opcode fetch machine cycle of 8085 :

• Each instruction of the processor has one byte opcode.

• The opcodes are stored in memory. So, the processor executes the opcode fetch machine

cycle to fetch the opcode from memory.

• Hence, every instruction starts with opcode fetch machine cycle.

• The time taken by the processor to execute the opcode fetch cycle is 4T.

• In this time, the first, 3 T-states are used for fetching the opcode from memory and the

remaining T-states are used for internal operations by the processor.





- Timing Diagram for Opcode Fetch Machine Cycle

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18. WITH NECESSARY TIMING DIAGRAMS EXPLAIN THE MEMORY READ AND WRITE

OPERATIONS SKETCH AND EXPLAIN ALL THE ASSOCIATED CONTROL SIGNALS? (12markquestion)

19. WITH NECESSARY TIMING DIAGRAMS EXPLAIN THE MEMORY READ AND WRITE

OPERATIONS? SPECIFY THE NO OF MACHINE CYCLE AND T-STATES REQUIRED?(12mark question)

Memory Read Machine Cycle of 8085:

• The memory read machine cycle is executed by the processor to read a data byte from

memory.

• The processor takes 3T states to execute this cycle.

• The instructions which have more than one byte word size will use the machine cycle after

the opcode fetch machine cycle.

Fig Fig - Timing Diagram for Memory Read Machine Cycle





Memory Write Machine Cycle of 8085:

• The memory write machine cycle is executed by the processor to write a data byte in a

memory location.• The processor takes, 3T states to execute this machine cycle.

Fig - Timing Diagram for Memory Write Machine Cycle

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20.WITH NECESSARY TIMING DIAGRAMS EXPLAIN THE I/O READ AND I/O WRITEOPERATIONS? SPECIFY THE NO OF MACHINE CYCLE AND T-STATES REQUIRED? (12mark

question)

I/O Read Cycle of 8085:

• The I/O Read cycle is executed by the processor to read a data byte from I/O port or from

the peripheral, which is I/O, mapped in the system.

• The processor takes 3T states to execute this machine cycle.





• The IN instruction uses this machine cycle during the execution.

Fig - Timing Diagram for I/O Read Machine Cycle

I/O Write Cycle of 8085:

• The I/O write machine cycle is executed by the processor to write a data byte in the I/O

port or to a peripheral, which is I/O, mapped in the system.

• The processor takes, 3T states to execute this machine cycle.





Fig - Timing Diagram for I/O Write Machine Cycle

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21. DISTINGUISH BETWEEN INSTRUCTION AND MACHINE CYCLE? ( 3 MARK

QUESTION)

Instruction Cycle:

• The time required to execute an instruction is called instruction cycle.

Machine Cycle:

• The time required to access the memory or input/output devices is called machine cycle.

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22. DISTINGUISH BETWEEN FETCH AND EXECUTE CYCLE? ( 3 MARK QUESTION)

• The instruction cycle is divided in to fetch and execute cycles.

• The fetch cycle is executed to fetch the opcode from memory.





• The execute cycle is executed to decode the instruction and to perform the work instructed by the

instruction.

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23. DESCRIBE HOW THE ADDRESS SPACE PARTIONING? DRAW THE CIRCUIT DIAGRAM,CLEARLY INDICATING THE SELECT LINES, TO INTERFACE THE 64KB EPROM WITH 8085?

(12mark question)

Consider a system in which the full memory space 64kb is utilized for EPROM memory. Interface

the EPROM with 8085 processor.

• The memory capacity is 64 Kbytes. i.e

• 2^n = 64 x 1000 bytes where n = address lines.

• So, n = 16.

• In this system the entire 16 address lines of the processor are connected to address input

pins of memory IC in order to address the internal locations of memory.

• The chip select (CS) pin of EPROM is permanently tied to logic low (i.e., tied to ground).

• Since the processor is connected to EPROM, the active low RD pin is connected to active low

output enable pin of EPROM.

• The range of address for EPROM is 0000H to FFFFH.

Fig - Interfacing 64Kb EPROM with 8085





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24.Draw the circuit diagram for a typical 32k*8 RAM chip and 32kb*8 EPROM

chip.indicate the entire control/address/status signal involved? How this can beconnected to a 8085 through a chip select? (12mark question)

Consider a system in which the available 64kb memory space is equally divided between EPROM

and RAM. Interface the EPROM and RAM with 8085 processor.

• Implement 32kb memory capacity of EPROM using single IC 27256.

• 32kb RAM capacity is implemented using single IC 62256.

• The 32kb memory requires 15 address lines and so the address lines A0 - A14 of the

processor are connected to 15 address pins of both EPROM and RAM.

• The unused address line A15 is used as to chip select. If A15 is 1, it select RAM and If A15

is 0, it select EPROM.

• Inverter is used for selecting the memory.

• The memory used is both Ram and EPROM, so the low RD and WR pins of processor are

connected to low WE and OE pins of memory respectively.• The address range of EPROM will be 0000H to 7FFFH and that of RAM will be 7FFFH to

FFFFH.

Fig - Interfacing 32Kb EPROM and 32Kb RAM with 8085

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25.Draw the circuit diagram for a typical four 8k*8 RAM chip .indicate the entirecontrol/address/status signal involved? How this can be connected to a 8085 through a

chip select? Show decoding logic and the circuit details? (12mark question)





Consider a system in which 32kb memory space is implemented using four numbers of 8kbmemory. Interface the EPROM and RAM with 8085 processor.

• The total memory capacity is 32Kb. So, let two number of 8kb n memory be EPROM and the

remaining two numbers be RAM.

• Each 8kb memory requires 13 address lines and so the address lines A0- A12 of the

processor are connected to 13 address pins of all the memory.

• The address lines and A13 - A14 can be decoded using a 2-to-4 decoder to generate fourchip select signals.

• These four chip select signals can be used to select one of the four memory IC at any one

time.

• The address line A15 is used as enable for decoder.

• The simplified schematic memory organization is shown.

Fig The address allotted to each memory IC is shown in following table.





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26. DISTINGUISH BETWEEN MEMORY MAPPED I/O AND I/O MAPPED I/O? (5 mark question)





27. THE MEMORY ADDRESS LAST LOCATION OF ONE AN 8BYTE CHIP IS FFFFH.SPECIFY THESTARTING ADDRESS? (3 mark question)

• 8 Kbyte chip requires 13 address lines(A0-A12) i.e. 23*210=213

• The remaining address lines can be used to select the chip cs-A13,A14, A15

• The ending address given in question is FFFF

• A15,A14, A13 ,A12,A11, A10, A9,A8, A7, A6,A5, A4, A3,A2, A1, A0

• 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

• F F F F

• Therefore starting address is

• A15,A14, A13 ,A12,A11, A10, A9,A8, A7, A6,A5, A4, A3,A2, A1, A0





• 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0

• E 0 0 0

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ec010505 microprocessors and applications module 1

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