dynamic interconnection networks 2014/saman... · (001, 000), (101, 101), and (110,010) at the same...

LECTURE 5

DR. SAMMAN H. AMEEN

Dynamic Interconnection

Networks

1

Last week

We discussed interconnection networks (INs) and their classification

This week we explain

1. Dynamic interconnection network

2. Single and multistage dynamic interconnection networks

PAGE 2

• An IN is characterized by its size and degree. By size, we mean the number of inputs and outputs of an IN where as the degree of a IN is defined as the size of SEs used to build it.

• A permutation IN is a network in which all N! permutations can be realized where N is the number of inputs and outputs of the network

•

Module size Legitimate states Permutation connection

2 × 2 4 2

4 × 4 256 24

8 × 8 16,777,216 40,320

N × N NN N!

• Permutation function: each input can only be connected a single output.

• Legitimate state: Each input can be connected to multiple outputs, but each output can only be connected to a single input

The different settings of a 2x2 Switching Element (SE)

single stage IN is a dynamic network composed of one linking

stage and two end SE stages. It should be noted that in some

references, a single stage IN is composed of only one switching

stage and one linking stage.

Methods are needed to change the interconnection pattern

so that a given input is sent to the desired output.

One common method is to circulate the input and output

connections until the desired destination is reached. This

is called Shuffle-Exchange, since a shuffle operation (on

the input number) is performed first followed by an

exchange operation.

A useful permutation is the exchange permutation,

A perfect shuffle interconnection for eight inputs and outputs.

A perfect-shuffle permutation of port labels can

be used to map from a set of source labels S to a

set of destination labels D. The ordered set of

input labels is divided into two subsets of equal

size which are then interleaved. This can be

represented by the bipartite graph of figure, from

which it can be observed that this permutation can

be produced by a simple manipulation of the

binary representation of the source label.

The perfect shuffle The inverse perfect shuffle

• Single stage Shuffle-Exchange IN (left)

• Perfect shuffle mapping function (right)

• Perfect shuffle operation: rotate 1 place left, eg 101 --> 011

• Exchange operation: invert least significant bit, e.g. 101 --> 100

• Shuffle and exchange operation: either rotate left or invert least significant bit

• In an 8-input single stage Shuffle–Exchange if the source is 0 (000) and the destination is 6 (110), then the following is the required sequence of Shuffle/ Exchange operations

and circulation of data:

E(000) →1(001)

S(001) → 2(010)

E(010) → 3(011)

S(011) → 6(110)

(Solid lines are exchanges and dashed lines are shuffle.)

The number of recirculations required to implement a particular

routing depends upon the connectivity of the network, and this

leads to a trade-off between connectivity (cost) and routing

time.

As an example, the figure

represents a single-stage network

based on the shuffle-exchange

connection

• The interconnection pattern used in the butterfly network is defined as follows:

• β(pn, pn-1, .. p2, p1 , p0) = {po, pn-1, .. p2 , p1, pn}

Informally, the most and least significant bits in the binary

representation of the network port label are interchanged, and

this is illustrated in the figure which shows the two-part graph

for a butterfly permutation.

B(000) = 000

B(001) = 100

B(010) = 010

B(011) = 110

B(100) = 001

B(101) = 101

B(110) = 011

B(111) = 111

The PM2I network consists of 2k interconnection functions defined as follows:

For example, consider the case N =8, PM2+1(4) =4+21 mod 8 = 6.

The PM2I network for

N =8

(a), PM2+0

(b) PM2+1

(b) PM2+2

1

• To illustrate the necessity of data routing in an array processor, we show the execution details of the following vector instruction in an array of N PEs. The sum S(k) of the first k components in a vector A is desired for each k from 0 to n - I. Let A = {A0,Ar, . . . ,A„-i)-We need to compute the following n summations:

To connect

• Processors and processors

• Processors and memory

• Processors and cashes

• Cashes and cashes

• I/O devices

At each intersection of a horizontal (incoming) and

vertical (outgoing) line is a cross-point. A cross-point is

a small switch that can be electrically opened or closed,

depending on whether the horizontal and vertical lines

are to be connected or not.

we see three cross-points closed simultaneously,

allowing connections between the (CPU, memory) pairs

(001, 000), (101, 101), and (110,010) at the same time.

One of the worst properties of the crossbar switch is that the number of cross-points grows as n2. For medium-sized

systems, a crossbar design is workable. However, with 1000 CPUs and 1000 memory modules, we need a million

cross-points. Such a large crossbar switch is not feasible. We need something quite different

The simplest circuit for connecting n CPUs to k memories

is the crossbar switch

• Use two-input AND and OR gates to construct NxN crossbar switch network between N processors and N memory modules. Use cij signal as the enable signal for the switch in ith

row and jth column. Let the width of each crosspoint be w bits.

• Explain the circuit operation

M1 M2 Mn

P1

P2

Pn

C11

C21

Cn1

C12

C22

Cn2

C1n

C2n

Cnn

...

...

Crosspoint

The cross-point shown here

is only unidirectional to

simplify the sketch.

Bidirectional cross-point.

C11

P1

M1

Crosspoint

Multistage Interconnection Networks (MINs) were introduced to improve the performance over

single-stage networks while maintaining an acceptable cost. Multistage interconnection networks

use the method of routing data in Inter-stage Connection (ISC) patterns. These inter-stage

connection patterns are kept between stages of switches. Each stage of connections is always the

same, with switches changing dynamically depending on the desired routing.

There are various configurations for multistage interconnection networks. They all follow the same

basic concept, with the pattern of inter-stage connections being different. Each pattern can be

better than others in different applications, depending on the layout of the system and how the

particular application is designed.

The schematic of a typical multistage interconnection network.

The figure shows how input 00 is

routed to output 11, and input 10 is

routed to output 00. It can also be

seen that multiple simultaneous paths

can be established

• In a Banyan network, there exists only a single path between an input port and an output port.

Up to N paths can be established between input and output ports, where N is the number of

ports. The output ports of the Banyan network are addressed in binary in an ascending order

• Delta Networks, which form a subset of Banyan networks, and Normally, a Delta network uses a

size of power of 2. Every Delta network is a Banyan network while the reverse is not always true.

Delta networks have a routing property called Self routing Property or Delta Property.

• Non Banyan networks are more expensive and complex to control then Banyan networks. Yet

they may offer fault tolerance and may solve some conflicts.

• The self routing property of Delta networks as shown in figure allows the routing decision to be

determined by the destination address, regardless of the source address.

In a Banyan network, there exists only a single path between an input port and an output port. Up

to N paths can be established between input and output ports, where N is the number of ports. The

output ports of the Banyan network are addressed in binary in an ascending order

• -:- Omega networks

• -:- Butterfly networks

• -:- Baseline networks

• -:- (Generalized) Cube networks

and their reverse networks

• -:- Flip networks

• -:- Reverse Butterfly networks

• -:- Reverse Baseline networks

• -:- Indirect Binary n-cube networks

• The interconnection stages are Shuffle– Exchange networks.

• two-input switching elements whose input is a shuffle connection.

• for network size = N

• The number of stages n (n = log2 N single-stage)

• Each stage consists of a column of N/2 Switching elements

• Network degree D= (N/2 ) log2 N

• Number of permutations in a omega network 2D

A Flip network is considered to be a mirror image of the Omega network.

It uses the inverse perfect shuffle permutation

The ith butterfly permutation βki , for 0 ≤ i ≤ n − 1, is defined by

βki (xn−1 xn−2 ... xi+1 xi xi−1 ... x1 x0) = xn−1 xn−2 ... xi+1 x0 xi−1 ... x1 xi

MINs have been classified into three classes depending on the availability of paths to establish new connections.

1. Blocking Networks

2. Nonblocking Networks

3. Rearrangeable Network

1-Blocking Networks

A connection between free input/output pair is not always possible because of conflicts with existing connections. Typically, there is a unique path between every input/output pair, thus minimizing the number of switches and stages.

One of the most critical issues concerning an IN topology is the existence or absence of multiple paths. By providing multiple paths in Blocking networks, conflicts can be reduced and fault tolerance can be increased.

2-Nonblocking Networks

Any input can be connected to any free output port without affecting the existing connections. They require extra stages and have multiple paths between every input and output. A popular example of Non-blocking networks is a Clos network

3-Rearrangeable Network

Any input port can be connected to any free output. However the existing connections may require rearrangement of paths. These networks also require multiple paths between every input and output, but the number of

paths and the cost is smaller than in the case of Non blocking networks.

Depending on the kind of channels and switches, MINs can be

either:

1. Unidirectional MINs. Channels and switches are

unidirectional.

2. Bidirectional MINs. Channels and switches are bidirectional.

This implies that information can be transmitted simultaneously

in opposite directions between neighboring switches.

dynamic interconnection networks 2014/saman... · (001, 000), (101, 101), and (110,010) at the same...

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