duplexing and scheduling for 5g systems · 3 introduction resource allocation in 5g systems -...

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Duplexing and Scheduling for 5G Systems

Ganesh Venkatraman, Praneeth Laddu, Antti Tolli

Email: {gvenkatr, pladdu, antti.tolli}@ee.oulu.fi

Centre for Wireless Communications (CWC),

Department of Communications Engineering (DCE),

University of Oulu, Oulu, FI-90014

c© Centre for Wireless Communications (CWC)

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1 Introduction

2 Scheduler Design Challenges & Requirements

3 Scheduling for Bidirectional Training

DL-DL Scenario

DL-UL Scenario

4 Conclusions


3

Introduction

Resource allocation in 5G systems - highly complex

- assignment over space, frequency and time dimensions

- dynamic TDD

Scheduling algorithm - determines a subset of users for each scheduling block (SB)

Scheduling objective - should be supported by precoder design


4

4G Issues and 5G Solutions

Shortcomings of 4G Systems

Physical layer latency - 1ms (subframe duration)

Synchronous TDD - cannot adapt to differential loads in each BS

Coordinated multipoint transmission - requires huge backhaul capacity

Enhancements for 5G Systems

Subframe duration - reduced to 0.1ms

DL and UL controls are embedded in each subframe

Dynamic TDD - can adapt to instantaneous loads in the network

Bidirectional training (BiT) through over-the-air (OTA) to reduce the load on

backhaul network


5

Challenges for Scheduler Design

Number of users - significantly large

More spatial degrees of freedom - MU-MIMO transmission

QoS requirements (includes latency and reliability)

Synchronizing transmissions over multiple BSs (CoMP)

Interference from neighboring BSs (or users) - Dynamic TDD

Best-Effort - PF scheduling (queues and delays can be considered)

Real time requirements - 0.1 ms periodicity


6

Scheduler Design Requirements

Channel knowledge - UL sounding reference signals

UE position in the cell (can be used for uplink scheduling)

QoS and delay requirements for UEs

Interference from neighboring BSs (or users) - Dynamic TDD

Objective of scheduler algorithm and precoder design - should be same

Open Issues

Minimum scheduling resolution to be supported - 1RB (includes ? tones)

Maximum scheduling resolution (coherence bandwidth ≈ 3MHz?)


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Bidirectional Training

Figure: Bidirectional Training Model

Data B F F B

Frame 𝑛

Frame 𝑛 − 1 Frame 𝑛 + 1

Beamformer signaling

BiT is performed by OTA transmissions - minimize backhaul signaling

Each TDD subframe includes - beamformer training followed by data transmission

BiT backward-forward signaling - facilitate fast iterative beamformer exchanges

Each BS and user terminal uses orthogonal precoded pilot signals for training


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Scheduling for Bidirectional Training

5G frame structure - includes both DL and UL control in each subframe

BiT based precoders are designed over multiple subframes - before actual data

transmission

Orthogonal precoded pilots - achieved using sub-carriers in control symbols

Scheduling for synchronous and dynamic TDD modes are addressed

Figure: 5G frame structure (0.1 msec)

UL

Co

ntr

ol S

ymb

ol

DL

Co

ntr

ol S

ymb

ol

Gu

ard

Per

iod

Uplink or Downlink Data Symbols

Gu

ard

Per

iod


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System Model for DL-DL Mode

Interference signal

Desired signal

𝑄1 𝑄2 𝑄3 𝑄4 𝑄5 𝑄6

𝑈1

𝑈2

𝑈3

𝑈4

𝑈5

𝑈6

DL Transmission DL Transmission


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Scheduler Design for DL-DL Mode (Frame - 1)

DL SCH (𝑈1)

Control for user set 𝑈𝑥 regarding Bidirectional training procedure initialization and SBs allocation

UL SCH (𝑈7)

BS 1

Control for user set 𝑈𝑦 regarding

Bidirectional training procedure initialization and SBs allocation

BS 2


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DL SCH (𝑈1) UL SCH (𝑈2)


Precoded pilot signals from BS - 1

Uplink precoded pilot signals from UEs in BS - 1

UL SCH (𝑈7) DL SCH (𝑈8)



BS 1



BS 2


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DL SCH (𝑈1) UL SCH (𝑈2) UL SCH (𝑈3) DL SCH (𝑈4) UL SCH (𝑈5)




UL SCH (𝑈7) DL SCH (𝑈8) UL SCH (𝑈9) UL SCH (𝑈8) UL SCH (𝑈7)



BS 1



BS 2


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Scheduler Design for DL-DL Mode

DL SCH (𝑈1) UL SCH (𝑈2) UL SCH (𝑈3) DL SCH (𝑈4) DL SCH (𝑈𝑥)

UL SCH (𝑈5)




MCS and other control for UEs regarding data transmission

UL SCH (𝑈7) DL SCH (𝑈8) UL SCH (𝑈9) UL SCH (𝑈8) DL SCH (𝑈𝑦)

UL SCH (𝑈7)




BS 1

DL transmission synchronized across BSs



BS 2


14

System Model for DL-UL Mode

DL Interference signal

Desired signal

𝑄1 𝑄2 𝑄3

𝑄4

𝑄5

𝑄6

𝑈1 𝑈2

𝑈3

𝑈4

𝑈5

𝑈6

DL Transmission UL Transmission

UL Interference signal


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Scheduler Design for DL-UL Mode (Frame - 1)

DL SCH (𝑈1)


UL SCH (𝑈7)


BS 2

BS 1




16


DL SCH (𝑈1) UL SCH (𝑈2)



UL SCH (𝑈7) DL SCH (𝑈8)


BS 2

BS 1




17


DL SCH (𝑈1) UL SCH (𝑈2) UL SCH (𝑈3)




UL SCH (𝑈7) DL SCH (𝑈8) UL SCH (𝑈9)



BS 2

BS 1




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DL SCH (𝑈1) UL SCH (𝑈2) UL SCH (𝑈3) DL SCH (𝑈4) UL SCH (𝑈5)




UL SCH (𝑈7) DL SCH (𝑈8) UL SCH (𝑈9) UL SCH (𝑈8) UL SCH (𝑈7)



BS 2

BS 1




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Scheduler Design for DL-UL Mode

DL SCH (𝑈1) UL SCH (𝑈2) UL SCH (𝑈3) DL SCH (𝑈4) DL SCH (𝑈𝑥)

UL SCH (𝑈5)





UL SCH (𝑈7) DL SCH (𝑈8) UL SCH (𝑈9) UL SCH (𝑈8) UL SCH (𝑈𝑦)

UL SCH (𝑈7)




BS 2

BS 1

DL/UL transmission synchronized across BSs




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Conclusions

Scheduler algorithm - precoder design - objective should be same

BiT is used for designing precoders to minimize the backhaul load

SPS can be used to reduce control overhead after precoder training

Allocating orthogonal resources in DL and UL control symbols - challenging task


duplexing and scheduling for 5g systems · 3 introduction resource allocation in 5g systems -...

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