dual output, two-phase synchronous buck dc/dc controller ...these two modes, along with...

��

��

��

SGLS225B − JANUARY 2004 − REVISED APRIL 2008

1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

� Qualified for Automotive Applications

� Independent Dual-Outputs Operate 180 °Out of Phase

� Wide Input Voltage Range: 4.5-V − 28-V

� Adjustable Output Voltage Down to 0.9 V

� Pin-Selectable PWM/SKIP Mode for HighEfficiency Under Light Loads

� Synchronous Buck Operation Allows up to95% Efficiency

� Separate Standby Control and OvercurrentProtection For Each Channel

� Programmable Short-Circuit Protection

� Low Supply (1 mA) and Shutdown (1 nA)Current

� Power Good Output

� High-Speed Error Amplifiers

� Sequencing Easily Achieved by SelectingSoftstart Capacitor Values.

� 5-V Linear Regulator Power Internal ICCircuitry

� 30-Pin TSSOP Packaging

� Gate Leakage Test Passing Level is 50 V

description

The TPS5120 is a dual channel, high-efficiencysynchronous buck controller where the outputsrun 180 degrees out of phase, which lowers theinput current ripple, thereby reducing the input capacitance cost. The PWM/SKIP pin allows the operating modeto switch from PWM mode to skip mode under light load conditions. The skip mode enables a lower operatingfrequency and shortens the pulse width to the low-side MOSFET, increasing the efficiency under light loadconditions. These two modes, along with synchronous-rectifier drivers, dead time, and very low quiescentcurrent, allow power to be conserved and the battery life to be extended under all load conditions. The 1.5 A(typical) high-side and low-side MOSFET drivers on-chip are designed to drive less expensive N-channelMOSFETs. The resistorless current protection and fixed high-side driver voltage simplify the power supplydesign and reduce the external parts count. Each channel is independent, offering a separate controller,overcurrent protection, and standby control. Sequencing is flexible and can be tailored by choosing differentsoftstart capacitor values. Other features, such as undervoltage lockout, power good, overvoltage,undervoltage, and programmable short-circuit protection promote system reliability.

ORDERING INFORMATION�

PACKAGE�

TA TSSOP(DBT)

−40°C to 125°C TPS5120QDBTRQ1† For the most current package and ordering

information, see the Package OptionAddendum at the end of this document, orsee the TI web site at http://www.ti.com.

‡ Package drawings, thermal data, andsymbolization are available athttp://www.ti.com/packaging.

Copyright 2008 Texas Instruments Incorporated�� !"#�� $ %&��'�# "$ �� (&)*�%"#�� +"#',��+&%#$ %��! #� $('%��%"#��$ ('� #-' #'�!$ �� '."$ ��$#�&!'�#$$#"�+"�+ /"��"�#0, ��+&%#�� (��%'$$��1 +�'$ ��# �'%'$$"��*0 ��%*&+'#'$#��1 �� "** ("�"!'#'�$,

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1

2

3

4

5

6

78

9

10

11

12

13

14

15

30

29

28

27

26

25

2423

22

21

20

19

18

17

16

INV1FB1

SOFTSTART1PWM/SKIP

CT5V_STBY

GNDREF

STBY1STBY2

FLTPOWERGOODSOFTSTART2

FB2INV2

LH1OUT1_uLL1OUT1_dOUTGND1TRIP1VCCTRIP2VREF5REG5V_INOUTGND2OUT2_dLL2OUT2_uLH2

DBT PACKAGE(TOP VIEW)

��

��

��


2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

typical design

22

GND L1

L2

Q1

Q2

Q3

Q4

D1

D2

C1

C3

C4

C5

C6

C7

C8

C10

C11

C12

C13

C14

R1 R2

R3

R4

R5 R6

R7

R8R9

R10

C15

U1TPS5120DBT

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

30

29

28

27

26

25

24

23

21

20

19

18

17

16

INV1

FB1

SOFTSTART1

PWM/SKIP

CT

5V_STBY

GND

REF

STBY1

STBY2

FLT

POWERGOOD

SOFTSTART2

FB2

INV2

LH1

OUT1_u

LL1

OUT1_d

OUTGND1

TRIP1

Vcc

TRIP2

VREF5

REG5V_IN

OUTGND2

OUT2_d

LL2

OUT2_u

LH2

VO1

VI

VO2

C15

C16

Figure 1. EVM Typical Design

��

��

��



functional block diagram

SOFTSTART1

DLY

DLY

OSC

Timer

SOFTSTART2

DLY

DLY

Phase

V 5 VREG

CurrentProtection

Trigger

Skip Comp.

PWM Comp.

Err Amp.

0.85 V

STBY1UVLO

SIGNAL

STBY2

OVP1

OVP2

UVP1

UVP2

0.85 V+12%

Err Amp.

Skip Comp.

0.85 V UVLOSIGNAL

UVLOComp.

0.85 V

INV2INV1

PGcomp4PGcomp3

INV2

PGcomp2

INV1

0.85 V−7% PGcomp1

4.5 V

5.0 V

PWM Comp.

Current Comp.

VCC

SOFTSTART1

FB1

INV1

CT

FLT

FB2

INV2

PWM/SKIP

SOFTSTART2

STBY1

STBY2REF

5V_STBY

GND

POWERGOOD

REG5V_IN

VREF5

LH2

OUT2_u

LL2

OUT2_d

OUTGND2

TRIP2

TRIP1

V

OUTGND1

OUT1_d

LL1

OUT1_u

LH1

SFT1 SFT2

Inverter

0.85 V+12%

0.85 V −19.4%

0.85 V −19.4%

ref

0.85 V −7%

0.85 V +7%0.85 V +7%

CC

_+

_

+

_

+

_

+

_

+

_+

_

++

_+

_

++

_

+

_

+

_

+

_

+

_+

_

+

_

+

_+

_

+

_

+

−(VCC

− VTRIP1VCC

LSD Trip

HSD Trip

_

+

HSD Trip

LSD Trip

− VTRIP1)

− VTRIP2VCC

−(VCC − VTRIP2)

��

��

��



Terminal Functions

TERMINALI/O DESCRIPTION

NAME NO.I/O DESCRIPTION

CT 5 I/O External capacitor from CT to GND for adjusting the triangle oscillator

FB1 2 O Feedback output of CH1 error amplifier

FB2 14 O Feedback output of CH2 error amplifier

GND 7 Control GND

INV1 1 I Inverting input of the CH1 error amplifier, skip comparator, and OVP1/UVP1 comparator

INV2 15 I Inverting input of the CH2 error amplifier, skip comparator, and OVP2/UVP2 comparator

LH1 30 I/O Bootstrap capacitor connection for CH1 high-side gate drive

LH2 16 I/O Bootstrap capacitor connection for CH2 high-side gate drive

LL1 28 I/O Bootstrap this pin low for CH1 high-side gate driving return and output current protection. Connect this pin tothe junction of the high-side and low-side FETs for a floating drive configuration.

LL2 18 I/O Bootstrap this pin low for CH2 high-side gate driving return and output current protection. Connect this pin tothe junction of the high-side and low-side FETs for a floating drive configuration.

OUT1_d 27 O Gate drive output for CH1 low-side gate drive

OUT2_d 19 O Gate drive output for CH2 low-side gate drive

OUT1_u 29 O Gate drive output for CH1 high-side switching FETs

OUT2_u 17 O Gate drive output for CH2 high-side switching FETs

OUTGND1 26 Ground for CH1 FET drivers

OUTGND2 20 Ground for CH2 FET drivers

POWERGOOD 12 O Power good open-drain output. When low, POWERGOOD reports an output fail condition. PG comparatorsmonitor both SMPS’s over voltage and UVLO of VREF5. The threshold is ±7%. When the SMPS starts up, thePOWERGOOD pin’s output goes high. POWERGOOD also monitors VREF5’s UVLO output.

PWM/SKIP 4 I PWM/SKIP mode select pin. The PWM/SKIP pin is used to change the output’s operating mode. If this terminalis lower than 0.5 V, it works in PWM mode. When a minimum voltage of 2 V is applied, the device operates inskip mode. In light load condition (< 0.2 A), the skip mode gives a short pulse to the low-side FETs instead of afull pulse. With this control, switching frequency is lowered and switching loss is reduced. Also, the outputcapacitor energy discharging through the output inductor and low-side FETs is stopped. Therefore, TPS5120achieves a higher efficiency in light load conditions.

REF 8 O 0.85-V reference voltage output. The 0.85-V reference voltage is used for setting the output voltage and thevoltage protection. This reference voltage is dropped down from a 5-V regulator.

REG5V_IN 21 I External 5-V input

FLT 11 I/O Fault latch timer pin. An external capacitor is connected between FLT and GND to set the FLT enable time up.

SOFTSTART1 3 I/O External capacitor from SOFTSTART1 to GND for CH1 softstart control. Separate soft-start terminals make itpossible to set the start-up time of each output independently.

SOFTSTART2 13 I/O External capacitor from SOFTSTART2 to GND for CH2 softstart control. Separate soft-start terminals make itpossible to set the start-up time of each output independently.

STBY1 9 I Standby control for CH1. SMPS1 can be switched into standby mode separately by grounding the STBY1 pin.

STBY2 10 I Standby control for CH2. SMPS2 can be switched into standby mode separately by grounding the STBY2 pin.

TRIP1 25 I External resistor connection for CH1 output current control

TRIP2 23 I External resistor connection for CH2 output current control

VCC 24 Supply voltage input

VREF5 22 O 5-V internal regulator output

5V_STBY 6 I 5-V linear regulator control

��

��

��



detailed description

switching-mode power supply (SMPS) 1, 2

The TPS5120 includes dual SMPS controllers that operate 180° out of phase and at the same frequency. Bothchannels have standby and softstart.

5-V regulator

An internal linear voltage regulator is used for the high-side driver bootstrap voltage and source of VREF(0.85 V). When the 5-V regulator is disconnected from the MOSFET drivers, it is only used for the source ofVREF. Since the input voltage range is from 4.5 V to 28 V, this feature offers a fixed voltage for the bootstrapvoltage so that the drive design is much easier. It is also used for powering the low-side driver. The toleranceis 4%. The 5-V regulator is disabled when STBY1, STBY2, and 5V_STBY are all set low.

5-V switch

If the internal 5-V switch senses the 5-V input from the REG5V_IN pin, the internal 5-V linear regulator isdisconnected from the MOSFET drivers. The external 5 V is then used for both the low-side driver and thehigh-side bootstrap, thus, increasing the efficiency.

error amplifier

Each channel has its own error amplifier to regulate the output voltage of the synchronous buck converter. Itis used in the PWM mode for the high output current condition (> 0.2 A). The unity gain bandwidth is 2.5 MHz.This decreases the amplifier delay during fast load transients and contributes to a fast transient response.

skip comparator

In skip mode, each channel has its own hysteretic comparator to regulate the output voltage of the synchronousbuck converter. The hysteresis is set internally and is typically set at 9 mV. The delay from the comparator inputto the driver output is typically 1.2 µs.

low-side driver

The low-side driver is designed to drive low rds(on) N-channel MOSFETs. The maximum drive voltage is 5 V fromVREF5. The current rating of the driver is typically 1.5 A at source and sink.

high-side driver

The high-side driver is designed to drive low rds(on) N-channel MOSFETs. The current rating of the driver is 1.2 Aat source and sink. When configured as a floating driver, the bias voltage to the driver is developed from VREF5,limiting the maximum drive voltage between OUTx_u and LLx to 5 V. The maximum voltage that can be appliedbetween LHx and OUTGND is 33 V.

deadtime

Deadtime prevents shoot through current from flowing through the main power FETs during switching transitionsby actively controlling the turnon time of the MOSFETs drivers.

current protection

Overcurrent protection is achieved by comparing the drain-to-source voltage of the high-side and low-sideMOSFET devices to a set-point voltage. This voltage is set using an external resistor between VCC and theTRIP1 or TRIP2 terminals. If the drain-to-source voltage up exceeds the set-point voltage during high-sideconduction, the current limit circuit terminates the high-side driver pulse. If the set-point voltage is exceededduring low-side conduction, the low-side pulse is extended through the next cycle. Together this action has theeffect of decreasing the output voltage until the undervoltage protection circuit is activated and the fault latchis set and both the high and low-side MOSFET drivers are shut off.

��

��

��



detailed description (continued)

overvoltage protection

For overvoltage protection (OVP), the TPS5120 monitors INV pin voltage. When the INV voltage is higher than0.95 V (+12%), the OVP comparator output goes high and the FLT timer starts to charge an external capacitorconnected to FLT. After a set time, the FLT circuit latches the MOSFET drivers off.

undervoltage protection

For undervoltage protection (UVP), the TPS5120 monitors INV pin voltage. When the INV voltage is lower than0.68 V (−19.4%), the OVP comparator output goes high, and the FLT timer starts to charge an external capacitorconnected to FLT. Also, when the current comparator triggers the OCP, the UVP comparator detects the undervoltage output and starts the FLT capacitor charge. After a set time, the FLT circuit latches off all of the MOSFETdrivers.

FLT

When an OVP or UVP comparator output goes high, the FLT circuit starts to charge the FLT capacitor. If theFLT pin voltage goes beyond a constant level, the TPS5120 latches the MOSFET drivers. At this time, the stateof MOSFET is different depending on the OVP alert and the UVP alert. Also, the enable time used to latch theMOSFET driver is decided by the capacity of the FLT capacitor. The charging constant current value is alsodifferent depending on whether it is an OVP alert or a UVP alert. The difference is shown in the followingequation:

FLT source current (OVP) = FLT source current (UVP) × 5

shutdown

The TPS5120 can be shut down by grounding STBY1, STBY2, and 5V_STBY. The shutdown current is as lowas 1 µA.

UVLO

When the input voltage goes up to about 4 V, the TPS5120 is operational. When the input voltage is lower thanthe turnon value, the device is turned off. The typical hysteresis voltage is 40 mV.

phase Inverter

Phase inverter controls the phase of SMPS1 and SMPS 2. SMPS1 operates in phase with the OSC. SMPS2operates 180° out of phase from SMPS1. This allows smaller input capacitors to be used.

oscillator

The TPS5120 has a triangle oscillator generator internal to the IC. The oscillation frequency is set by the sizeof the capacitor connected to the CT pin. The voltage amplitude is 0.43 V ~ 1.17 V.

��

��

��



Table 1. Logic Chart

5V_STBY STBY1 STBY2 SMPS1 SMPS2 5 V REGULATOR POWERGOOD

L L L Disable Disable Disable Disable

L L H Disable Enable Enable Active†

L H L Enable Disable Enable Active†

L H H Enable Enable Enable Active

H L L Disable Disable Enable L

H L H Disable Enable Enable Active†

H H L Enable Disable Enable Active†

H H H Enable Enable Enable Active† PG is set high during a softstart.

POWERGOOD timing sequence

POWERGOOD

STBY1

STBY2

INV1

INV2

H

L

H

L

H

L

0.91 V0.85 V0.78 V

0 V

0.91 V

0.85 V0.78 V

0 V

TSS

During a softstart, this channel’s powergood comparator output is fixed low (POWERGOOD output is high).

��

��

��



absolute maximum ratings over operating free-air temperature (unless otherwise noted) †

Supply voltage, VCC (see Note 1) −0.3 V to 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage: INV1, INV2, CT, PWM/SKIP, REG5V_IN, SOFTSTART1, SOFTSTART2, −0.3 V to 7 V. . . . .

FLT, POWERGOOD −0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STBY1, STBY2, 5V_STBY, TRIP1, TRIP2 −0.3 V to 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage: LL1, LL2 −1.0 V to 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OUT1_u, OUT2_u −1.0 V to 35 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LH1, LH2 −0.3 V to 35 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OUT1_d, OUT2_d, 5V_OUT, FB1, FB2 −0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REF −0.3 V to 3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OUT1_u, LH1 to LL1 −0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OUT2_u, LH2 to LL2 −0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power dissipation (TA ≤ 25°C), PD 874 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gate Leakage Test Results ±50 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating junction temperature range, TJ −40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, Tstg −55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values are with respect to the network ground terminal unless otherwise noted.2. This rating is specified at duty = 10% on output rise and fall each pulse. Each pulse width (rise and fall) for the peak current should

not exceed 2 µs.3. See Dissipation Rating Table for free-air temperature range above 25°C.

DISSIPATION RATING TABLE

PACKAGETA ≤ 25°C

POWER RATINGDERATING FACTORABOVE TA = 25°C

POWER DISSIPATIONTA = 85°C

DBT 874 mW 6.993 mW/°C 454 mW

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, VCC 4.5 28 V

INV1, INV2, CT, PWM/SKIP, SOFTSTART1, SOFTSTART2, FLT 6

REG5V_IN, POWERGOOD −0.1 5.5

Input voltage, VI STBY1, STBY2, 5V_STBY 28 VInput voltage, VIOUT1_u, OUT2_u, LH1, LH2 33

V

TRIP1, TRIP2 −0.1 28

Oscillator frequency, fosc 300 500 kHz

Operating junction temperature range, TJ −40 125 °C

��

��

��



electrical characteristics over recommended free-air temperature range, V CC = 7 V (unlessotherwise noted)

reference voltagePARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Vref Reference voltage 0.85 V

TA = 25°C, I = 50 µA −1% 1%

Vref(tol) Reference voltage tolerance TJ = −20°C to 125°C, I = 50 µA −1.5% 1.5%Vref(tol) Reference voltage toleranceTJ = −40°C to 125°C, I = 50 µA −2% 2%

R(egin) Line regulation VCC = 4.5 V to 28 V, I = 50 µA 0.05 3 mV

R(egl) Load regulation I = 0.1 µA to 1 mA 0.15 5 mV

oscillatorPARAMETER TEST CONDITIONS MIN TYP MAX UNIT

fosc Frequency PWM mode, CT = 44 pF, TA = 25 °C 300 kHz

VOH High level output voltageDC 1 1.1 1.2

VVOH High level output voltage fosc = 300 kHz 1.17V

VOL Low level output voltageDC 0.4 0.5 0.6

VVOL Low level output voltage fosc = 300 kHz 0.43V

error amplifierPARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIO Input offset voltage TA = 25°C 2 10 mV

Open-loop voltage gain 50 dB

Unity-gain bandwidth 2.5 MHz

I(snk) Output sink current VO = 1 V 0.3 0.7 mA

I(src) Output source current VO = 1 V 0.2 0.9 mA

skip comparatorPARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Vhys Hysteresis window SKIP mode 9 mV

duty controlPARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DUTY Maximum duty cycle 300 kHz, VI = 0 V 83%

controlPARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIH High-level input voltageSTBY1, STBY2 2.2

VVIH High-level input voltage PWM/SKIP, 5V_STBY 2.2V

VIL Low-level input voltageSTBY1, STBY2 0.3

VVIL Low-level input voltage PWM/SKIP, 5V_STBY 0.3V

5-V internal switchPARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V(TO_H)Threshold

4.2 4.8V

V(TO_L)Threshold

4.1 4.7V

Vhys Hysteresis 30 200 mV

��

��

��



electrical characteristics over recommended free-air temperature range, V CC = 7 V (unlessotherwise noted) (continued)

5-V regulatorPARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VO Output voltageIO = 0 mA to 50 mA,TA = 25°C

VCC = 5.5 V to 28 V, 4.8 5.2 V

R(egin) Line regulation VCC = 5.5 V to 28 V, I =10 mA 20 mV

R(egl) Load regulation I = 1 mA to 10 mA, VCC = 5.5 V 40 mV

IOS Short circuit output current 5VREG = 0 V, TA = 25°C 65 mA

V(TO_H)UVLO threshold voltage 5V_OUT voltage

3.6 4.2V

V(TO_L)UVLO threshold voltage 5V_OUT voltage

3.5 4.1V

Vhys Hysteresis 5V_OUT voltage 20 150 mV

output driversPARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OUT_u sink current VO = 3 V 1.2 A

OUT_u source current VO = 2 V −1.5 A

OUT_d sink current VO = 3 V 1.5 A

OUT_d source current VO = 2 V −1.5 A

I(TRIP) TRIP pin current TA = 25°C 11.5 13 14.5 µA

soft startPARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I(SOFT) Soft start current 1.6 2.3 2.9 µA

V(TO_H)Threshold voltage (SKIP mode)

3.7V

V(TO_L)Threshold voltage (SKIP mode)

2.5V

output voltage monitorPARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OVP comparator threshold 0.91 0.95 0.99 V

UVP comparator threshold 0.64 0.68 0.72 V

PG comparator 1, 2 threshold 0.75 0.78 0.81 V

PG comparator 3, 4 threshold 0.88 0.91 0.94 V

PG propagation delay from INV to POWERGOODTurnon 13

sPG propagation delay from INV to POWERGOODTurnoff 1.2

µs

Timer latch current sourceUVP protection 1.5 2.3 3.1

ATimer latch current sourceOVP protection 8 11.5 15

µA

supply currentPARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ICC Supply current TA = 25°C, CT = 0 V, INV = 0 V 1.1 1.5 mA

ICC(S) Shutdown current STBY 1, STBY2, 5V_STBY = 0 V 0.001 10 µA

��

��

��



TYPICAL CHARACTERISTICS

Figure 2

TJ − Junction Temperature − °C

QUIESCENT CURRENTvs

JUNCTION TEMPERATURE

1.05

1.10

1.15

1.20

1.25

1.30

−50 0 50 100 150

Icc

− Q

uies

cent

Cur

rent

− m

A

VCC = 28 V

VCC = 7 VVCC = 4.5 V

QUIESCENT CURRENT (SHUTDOWN)vs


0

200

400

600

800

1000

1200

−50 0 50 100 150

Icc(

s) −

Qui

esce

nt C

urre

nt −

nA VCC = 28 V

VCC = 7 V

VCC = 4.5 V

TJ − Junction Temperature − °CFigure 3

Figure 4

DRIVE OUTPUT CURRENT (OUT_u)vs

DRIVE OUTPUT VOLTAGE−1.80

−1.70

−1.60

−1.50

−1.40

−1.30

−1.20

−1.10

−1.00

−0.90

−0.800.5 1 1.5 2 2.5 3 3.5

I O(S

OU

RC

E) −

Driv

e O

utpu

t Cur

rent

(O

UT

_u)

− A

TJ = −40 °C

TJ = −20 °C

TJ = 25 °C

TJ = 85 °C

TJ = 125 °C

VO − Drive Output Voltage (OUT_u) − VFigure 5

vsDRIVE OUTPUT VOLTAGE

0.60

0.70

0.80

0.90

1.00

1.10

1.20

1.30

1.40

1.50

1.5 2 2.5 3 3.5 4 4.5

I O(S

INK

)

TJ = −40 °C

TJ = 25 °CTJ = −20 °C

TJ = 85 °C

TJ = 125 °C

VO − Drive Output Voltage (OUT_u) − V

DRIVE OUTPUT CURRENT (OUT_u)

− D

rive

Out

put C

urre

nt (

OU

T_u

) −

A

��

��

��




Figure 6

DRIVE OUTPUT CURRENT (OUT_d)vs

DRIVE OUTPUT VOLTAGE−2.00

−1.80

−1.60

−1.40

−1.20

−1.00

−0.800.5 1 1.5 2 2.5 3 3.5

VO − Drive Output Voltage (OUT_d) − V

I O(S

OU

RC

E)−

Driv

e O

utpu

t Cur

rent

(O

UT

_d)

− A

TJ = −40 °C TJ = −20 °C

TJ = 25 °C

TJ = 85 °C TJ = 125 °C

Figure 7

vsDRIVE OUTPUT VOLTAGE

0.80

0.90

1.00

1.10

1.20

1.30

1.40

1.50

1.60

1.70

1.80

1.5 2 2.5 3 3.5 4 4.5

TJ = −40 °C TJ = −20 °C

TJ = 25 °C

TJ = 85 °C

TJ = 125 °CI O

(SIN

K)

DRIVE OUTPUT CURRENT (OUT_d)

− D

rive

Out

put C

urre

nt (

OU

T_d

) −

A

VO − Drive Output Voltage (OUT_d) − V

Figure 8

OSCILLATOR OUTPUT VOLTAGEvs


1.00

1.02

1.04

1.06

1.08

1.10

1.12

1.14

1.16

1.18

1.20

−50 0 50 100 150

V (O

SC

H)

− O

scill

ator

Out

put V

olta

ge −

V

VCC = 4.5 V,VCC = 7 V,VCC = 28 V


Figure 9

OSCILLATOR OUTPUT VOLTAGEvs


480

485

490

495

500

−50 0 50 100 150

V (O

SC

L) −

Osc

illat

or O

utpu

t Vol

tage

− m

V


VCC = 4.5 V,VCC = 7 V,VCC = 28 V

��

��

��




Figure 10

ERROR AMPLIFIER INPUT OFFSET VOLTAGEvs


2.20

2.25

2.30

2.35

2.40

2.45

2.50

2.55

−50 0 50 100 150

VIO

− E

rror

Am

plifi

er In

put O

ffset

Vol

tage

− m

V

VCC = 28 V


VCC = 4.5 V,VCC = 7 V

Figure 11

ERROR AMPLIFIER OUTPUT VOLTAGE vs


1.50

1.75

2.00

2.25

2.50

2.75

3.00

−50 0 50 100 150V O

+ −

Pos

itive

Err

or A

mpl

ifier

Out

put V

olta

ge −

V

VCC = 4.5 V,VCC = 7 V,VCC = 28 V


Figure 12

ERROR AMPLIFIER OUTPUT VOLTAGEvs


0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

−50 0 50 100 150

VO

−−

Neg

ativ

e E

rror

Am

plifi

er O

utpu

t Vol

tage

− m

V


VCC = 4.5 V,VCC = 7 V,VCC = 28 V

Figure 13

SKIP COMPARATOR HYSTERESIS VOLTAGEvs


7.0

7.2

7.4

7.6

7.8

8.0

8.2

8.4

8.6

8.8

9.0

−50 0 50 100 150

Vhy

s −

Ski

p C

ompa

rato

r H

yste

resi

sV

olta

ge −

mV

VCC = 4.5 V

VCC = 7 VVCC = 28 V


��

��

��




Figure 14

VREF5 OUTPUT VOLTAGEvs

OUTPUT CURRENT

4.50

4.60

4.70

4.80

4.90

5.00

5.10

5.20

−60−50−40−30−20−100IO − Output Current − mA

TJ = −40 °CTJ = −20 °C

TJ = 25 °C

TJ = 85 °C

TJ = 125 °C

V O −

VR

EF

5 O

utpu

t Vol

tage

− V

Figure 15

VREF5 SHORT-CIRCUIT OUTPUT CURRENTvs

JUNCTION TEMPERATURE−120

−100

−80

−60

−40

−20

0−50 0 50 100 150

I OS

− V

RE

F5

Sho

rt−C

ircui

t Out

put C

urre

nt −

mA

VCC = 4.5 V

VCC = 7 V

VCC = 28 V


Figure 16

UVLO THRESHOLD VOLTAGEvs


3.50

3.60

3.70

3.80

3.90

4.00

−50 0 50 100 150

V (TO

) −

UV

LO T

hres

hold

Vol

tage

− V

V(TO_H)

V(TO_L)


Figure 17

UVLO HYSTERESIS VOLTAGEvs


0

20

40

60

80

100

120

140

−50 0 50 100 150

V hys

− U

VLO

Hys

tere

sis

Volta

ge −

mV


��

��

��




Figure 18

REG5V_IN THRESHOLD VOLTAGEvs


4.4

4.5

4.5

4.6

4.6

4.7

4.7

−50 0 50 100 150

V (TO

)− R

EG

5V_I

N T

hres

hold

Vol

tage

− V

V(TO_L)

V(TO_H)


Figure 19

REG5V_IN HYSTERESIS VOLTAGEvs


0

20

40

60

80

100

120

140

−50 0 50 100 150

V hys

− R

EG

5V_I

N H

yste

resi

s Vo

ltage

− m

V


Figure 20

−50 0 50 100 150

SOFTSTART CURRENTvs

JUNCTION TEMPERATURE−2.30

−2.28

−2.26

−2.24

−2.22

−2.20

−2.18

−2.16

−2.14

−2.12

−2.10

Sof

tsta

rt C

urre

nt −

A

VCC = 4.5 V

µ


VCC = 7 V,VCC = 28 V

Figure 21

OVP THRESHOLD VOLTAGEvs


944

946

948

950

952

954

956

−50 0 50 100 150

V (TO

) − O

VP

Thr

esho

ld V

olta

ge −

mV

VCC = 4.5 V



��

��

��




Figure 22

POWERGOOD THRESHOLD VOLTAGEvs


750

775

800

825

850

875

900

925

950

−50 0 50 100 150

V (TO

)− P

ower

good

Thr

esho

ld V

olta

ge −

mV V(TO_H)

V(TO_L)


VCC = 4.5 V,VCC = 7 V,VCC = 28 V

VCC = 4.5 V,VCC = 7 V,VCC = 28 V

Figure 23

SCP (OVP) SOURCE CURRENTvs


−11.9

−11.8

−11.7

−11.6

−11.5

−11.4

−11.3

−11.2

−11.1

−11.0−50 0 50 100 150

SC

P (

OV

P)

Sou

rce

Cur

rent

−

VCC = 4.5 V



Aµ

Figure 24

SCP (OVP) SOURCE CURRENTvs


−2.38

−2.35

−2.33

−2.30

−2.28

−2.25

−2.23

−2.20−50 0 50 100 150

I (SO

UR

CE

) −

VCC = 4.5 VSC

P (

OV

P)

Sou

rce

Cur

rent

−



Aµ

Figure 25

TRIP SINK CURRENTvs

TRIP INPUT VOLTAGE

12.0

12.2

12.4

12.6

12.8

13.0

13.2

13.4

13.6

13.8

14.0

0 4 8 12 16 20 24 28 32

VI − TRIP Input Voltage − V

I (SIN

K)−

TR

IP S

ink

Cur

rent

−

A

TJ = −40 °C

TJ = −20 °C

TJ = 25 °C

TJ = 85 °CTJ = 125 °C

µ

��

��

��




Figure 26

OSCILLATOR FREQUENCYvs

CAPACITANCE

10

100

1000

0 50 100 150 200 250CT − Capacitance − pF

f OS

C −

Osc

illat

or F

requ

ency

− k

Hz

VCC = 7 V,

TJ = 25 °C

Figure 27

OUTPUT MAXIMUM DUTY CYCLEvs


81.0

81.5

82.0

82.5

83.0

83.5

84.0

84.5

85.0

−50 0 50 100 150O

utpu

t Max

imum

Dut

y C

ycle

− %

VCC = 7 V,

VCC = 28 V

VCC = 4.5 V


fosc = 300 kHz

Figure 28

SCP DELAY TIMEvs

CAPACITANCE

1

10

100

1 k

10 k

100 k

10 100 1 k 10 k 100 kSCP − Capacitance − pF

− S

CP

Del

ay T

ime

(O

VP

) −

st d

(SC

P)

µ

Figure 29

SOFTSTART TIMEvs

SOFTSTART CAPACITANCE

10

100

1 k

10 k

100 k

100 1 k 10 k 100 kSoftstart Capacitance − pF

t −

Sof

tsta

rt T

ime

− sµ

��

��

��




Figure 30

DRIVER DEAD TIME (OUT_u FALL)vs


162.5

165.0

167.5

170.0

172.5

175.0

−50 0 50 100 150

Driv

er D

ead

Tim

e −

ns

VCC = 4.5 V



Figure 31

DRIVER DEAD RISE TIME (OUT_u RISE)vs


70

75

80

85

90

95

100

−50 0 50 100

Driv

er a

nd D

ead

Ris

e Ti

me

(OU

T_u

RIS

E)

VCC = 4.5 V



PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TPS5120QDBTRQ1 ACTIVE TSSOP DBT 30 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS5120Q1

TPS5120QDBTRQ1G4 ACTIVE TSSOP DBT 30 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS5120Q1

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

OTHER QUALIFIED VERSIONS OF TPS5120-Q1 :

• Catalog: TPS5120

• Enhanced Product: TPS5120-EP

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

http://focus.ti.com/docs/prod/folders/print/tps5120.htmlhttp://focus.ti.com/docs/prod/folders/print/tps5120-ep.html

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

TPS5120QDBTRQ1 TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1

TPS5120QDBTRQ1G4 TSSOP DBT 30 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jul-2019

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS5120QDBTRQ1 TSSOP DBT 30 2000 350.0 350.0 43.0

TPS5120QDBTRQ1G4 TSSOP DBT 30 2000 350.0 350.0 43.0

PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jul-2019

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

C

28X 0.5

2X

7.15

30X

0.23

0.17

6.55

6.25

TYP

1.2 MAX

0.15

0.05

0.25

GAGE PLANE

-80

B

4.5

4.3

NOTE 4

A

7.85

7.75

NOTE 3

0.75

0.50

(0.15) TYP

TSSOP - 1.2 mm max heightDBT0030A

SMALL OUTLINE PACKAGE

1

15

16

30

0.1 C A B

PIN 1 INDEX AREA

SEE DETAIL A

0.1 C

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

SEATING

PLANE

A 20

DETAIL A

TYPICAL

SCALE 2.000

4220214/A 05/2020

www.ti.com

EXAMPLE BOARD LAYOUT

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

30X (1.5)

30X (0.3)

30X (0.5)

(5.8)

(R0.05) TYP



NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SYMM

SYMM

1

15 16

30

15.000

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

SOLDER MASK

OPENING

EXPOSED METALEXPOSED METAL

SOLDER MASK DETAILS

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

4220214/A 05/2020

www.ti.com

EXAMPLE STENCIL DESIGN

30X (1.5)

30X (0.3)

30X (0.5)

(5.8)

(R0.05) TYP



NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

SYMM

SYMM

1

15 16

30

4220214/A 05/2020

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2020, Texas Instruments Incorporated

http://www.ti.com/legal/termsofsale.htmlhttp://www.ti.com

Sheets and Views4220214-4220214_1_24220214-4220214_1_34220214-4220214_1_4

dual output, two-phase synchronous buck dc/dc controller ...these two modes, along with...

Documents