Download - Lecture 5 GPIO (1-28-14)(1) ECEN 442
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8/12/2019 Lecture 5 GPIO (1-28-14)(1) ECEN 442
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Lecture 5 : General Purpose I/O
ECEN442
DSP Based
Electromechanical Motion Control
Spring 2014
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GPIO Pins
GPIO = General Purpose Input/Output
Relevant TI reference document:
TMS320F2803x Piccolo System Control and Interrupts
GPIO pins are digital I/O pins
F28035 (80 pin package) has 45 digital I/O pins
Multiplexed with up to 3 other peripherals per pin
2 GPIO ports
Port A = GPIO0 to GPIO31
Port B = GPIO32 to GPIO 44
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Digital I/O
GPIO pins are digital
Must interface with external analog world
Ideally the input values to the pins would be exactly 0V or 3.3V
In reality there is a low value range, a high value range, and an
uncertain range in between
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Traditional vs. Structure-Based Coding
Traditional approach to coding
Single variable name corresponds to an entire register
Cumbersome to anything other than write an entire register at once
Structure-based approach to coding
Structure consists of a collection of related member variables ofdifferent data types grouped in consecutive memory locations
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F2803x Structure Naming Convention
The F2803x header files define all of the:
Peripheral structures
Register names
Bit field names
Register addresses
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PeripheralName.RegisterName.all // Access full 16 or 32-bit register
PeripheralName.RegisterName.half.LSW // Access low 16-bits of 32-bit register
PeripheralName.RegisterName.half.MSW // Access high 16-bits of 32-bit register
PeripheralName.RegisterName.bit.FieldName // Access specified bit fields of register
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GPIO Control Registers
6GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 00Example:
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GPIO Data Registers
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GpioDataRegs.GPADAT.bit.GPIO7=1Example:
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EALLOW Protection
EALLOW stands for Emulation Allow
Code access to protected registers allowed only when
EALLOW = 1 in the ST1 register
The emulator can always access protected registers
EALLOW bit controlled by assembly level instructions
EALLOW sets the bit (register access enabled)
EDIS clears the bit (register access disabled)
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EALLOW;
GpioCtrlRegs.GPBMUX1.bit.GPIO40 = ??
GpioCtr lRegs.GPBDIR.bit.GPIO40 = ??
EDIS;
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EALLOW Protected GPIO Registers
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Multiplexers (Mux)
Select an input value with one or more select bits
Selecting between 4 inputs requires 2 selection bits
Allow for conditional transfer of data
Or more specifically, in our case, conditional functionality
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Gate Level
Representation
Block Level
Representation
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Multiplexing
GPxMUX registers 1 and 2 control the selection for each pin
GPAMUX1 for GPIO0 to GPIO15
GPAMUX2 for GPIO16 to GPIO31
GPBMUX1 for GPIO32 to GPIO44
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01
00
Peripheral1
GPxMUX1GPxMUX2 10
11
Peripheral2
Peripheral3
GPIO
Pin
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Multiplexing
To set GPIO0 pin as an I/O:
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Pin 69 in 2803x
80-Pin Package
Pg 83 of TMS320F2803xPiccolo System Control andInterrupts Reference Guide
GpioCtrlRegs.GPAMUX1.bit.GPIO0=00
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Selecting Direction
I/O Pins can be programmed as input or output pins.
Practical examples
Output - LED
Input - Push-button
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Output Configuration
GPIO controls whether switch isconnected to Vdd or ground
Input Configuration
If the push-button is depressed, the GPIO isconnected to ground and reads 0 (active low)
If the push-button is untouched, the GPIO is
connected to Vdd and reads 1
PB
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Selecting Direction
GPxDIR register decides input/output functionality.
GPADIR for GPIO0-GPIO31
GPBDIR for GPIO32-GPIO44
Each bit in GPxDIR corresponds to an I/O pin
0configures GPIO as input (default at reset)
1configures GPIO as output
To set GPIO40 as output:
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GpioCtrlRegs.GPBDIR.bit.GPIO40=1
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GPIO Read
Use data register for reading from pins: one data register for
each portGPxDAT GPADAT for GPIO0 to GPIO31
GPBDAT for GPIO32 to GPIO44
To load the value of GPIO33 into variable a:
Each bit in data register reflects the state of corresponding pin
irrespective of pin configuration.
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a = GpioDataRegs.GPBDAT.bit.GPIO33
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GPIO Write
What happens when we write to data register?
Output latch is used as a buffer. Value of 1 is latched
If the pin has already been defined as output:
It is driven high
If the pin is defined as input
The data remains in the latch and the pin is unaffected
Using the data registers to write to the pins may cause
unexpected problems
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GpioDataRegs.GPADAT.bit.GPIO7 = 1
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Potential Error When Writing with GPxDAT
The GPxDAT registers reflect the state of the pins (actual pin
values), not the latches
There is a lag between when the register is written to and when
the new value is actually reflected back into the register
This lag can lead to problems when two consecutivestatements write to the same GPxDAT register
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GpioDataRegs.GPBDAT.bit.GPIO40 = 1;GpioDataRegs.GPBDAT.bit.GPIO41 = 1;
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Potential Error When Writing with GPxDAT
Simplified 2-bit Example:
What will happen:
Assume both register bits are initially 0
The 1st instruction will readthe register into the latch
The 1st instruction will modifythe values read into the latch
from: 00 to 01
Before the 1st instruction causes the new value (01) to bewritten
from the latch to the pin, the 2nd instruction will read the register
(actual pin values) into the latch
This will override the 01 in the latch with 00 (the original
pin values)
The 2nd instruction will modify the latch values from: 00 to 10
The value 10 will then be written from the latch onto the pins
The final pin values will be 10 instead of the 11 we would have
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GpioDataRegs.GPBDAT.bit.GPIO40 = 1;
GpioDataRegs.GPBDAT.bit.GPIO41 = 1; Latches Pins
GPIO41 GPIO40 GPIO41 GPIO40
0 0 0 0
0 0 0 0
0 1 0 0
0 0 0 0
1 0 0 0
1 0 1 0
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GPIO Write Registers to write to GPIO:
GPxSET
Writing a 1 forces the corresponding GPIO pin latch high (to digital 1)
GPxCLEAR
Writing a 1 forces the corresponding GPIO pin latch low (to digital 0)
GPxTOGGLE
Writing a 1 toggles the corresponding GPIO pin latch ( 0 1 and 1 0)
Writes of 0 to these registers are ignored
These registers always read back 0
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GpioDataRegs.GPASET.bit.GPIO7=1
GpioDataRegs.GPACLEAR.bit.GPIO7=1
GpioDataRegs.GPATOGGLE.bit.GPIO7=1
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Input Qualification
Bouncing of push buttons due to metal contacts/springs
The bouncing period is of the order of milliseconds
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Q f
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Input Qualification
Hardware solution: De-bouncing circuits
Software solution: Input qualification
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I Q lifi i
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Input Qualification
Signal is sampled for specified number of cycles before input
is changed.
Sampling period is fixed in GPxCTRL (16 bits for 8 pins).
Number of samples selected using GPxQSEL1 and GPxQSEL2.
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I t Q lifi ti S li P i d
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Input Qualification: Sampling Period
Sampling period is fixed relative to SYSCLKOUT in
GPxCTRL using QUALPRD#
Setting sampling period at 510 clock cycles for GPIO3:
Setting sampling period at 1clock cycles for GPIO29:
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GpioCtrlRegs.GPACTRL.bit.QUALPRD3=00
GpioCtrlRegs.GPACTRL.bit.QUALPRD0=0xFF
I t Q lifi ti N b f S l
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Input Qualification: Number of Samples
Number of samples selected using GPxQSEL1 and
GPxQSEL2. 2 bits allotted per GPIO pin
00synchronize to SYSCLKOUT only (Default at reset)
01qualify using 3 samples (sampling window of 2 qual periods)
10qualify using 6 sample (sampling window of 5 qual periods)
11asynchronous (this option should not be selected but defaults to 00 for GPIO)
Example: set GPIO9 to qualify the input using 3 samples:
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GpioCtrlRegs.GPAQSEL1.bit.GPIO9=01
I t Q lifi ti S li Wi d
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Input Qualification: Sampling Window
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GPxQSEL# = 01 (3 Samples)
Sampling Window Width
GPxQSEL# = 10 (6 Samples)
Sampling Window Width
If QUALPRD# = 02 T
SYSCLKOUT
5 TSYSCLKOUT
If QUALPRD# 02 2 GPxCTRL[QUALPRDn]
TSYSCLKOUT
5 2 GPxCTRL[QUALPRDn]
TSYSCLKOUT
I t Q lifi ti E l 1
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Input Qualification Example 1
Sampling period = TSYSCLKOUT
Number of samples = 6
Sampling window size = 5 x TSYSCLKOUT
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I t Q lifi ti E l 2
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Input Qualification Example 2
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