Download - FPGA Tutorial - LCD Interface
Interfacing FPGA to LCD 16x2Problem and Solution
Akhmad [email protected]
You are free:to Share to copy, distribute and transmit the workUnder the following conditions:Attribution You must attribute the work in the manner specified by the author or licensor (but not in any way that suggests that they endorse you or your use of the work).Noncommercial You may not use this work for commercial purposes.No Derivative Works You may not alter, transform, or build upon this work.
Block Diagram
Pin Description
Write Timing Diagram
LCD Command
LCD initialize Procedure from Datasheet
Implement to FPGA
NET "en" LOC = P62;NET "dataLCD" LOC = P72;NET "dataLCD" LOC = P73;NET "dataLCD" LOC = P83;NET "dataLCD" LOC = P84;NET "rs" LOC = p61;NET "clock" LOC = P43;NET "reset" LOC = P44;
Recommendate Data sheet Init LCD
Behaviour Simulation
Post Route Simulation
It shown that thereis many unknown data that differ from behaviour simulation
Post route Simulation
Unknown Condition
My testbench
LIBRARY ieee;USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned values--USE ieee.numeric_std.ALL; ENTITY LCDTestBench ISEND LCDTestBench; ARCHITECTURE behavior OF LCDTestBench IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT LCDTest PORT( dataLCD : OUT std_logic_vector(3 downto 0); en : OUT std_logic; rs : OUT std_logic; reset : IN std_logic; clock : IN std_logic ); END COMPONENT;
--Inputs signal reset : std_logic := '0'; signal clock : std_logic := '0';
--Outputs signal dataLCD : std_logic_vector(3 downto 0); signal en : std_logic; signal rs : std_logic;
-- Clock period definitions constant clock_period : time := 83.3 ns; BEGIN
-- Instantiate the Unit Under Test (UUT) uut: LCDTest PORT MAP ( dataLCD => dataLCD, en => en, rs => rs, reset => reset, clock => clock );
-- Clock process definitions clock_process :process beginclock pscOut -- Clock buffer input);
MYCNT : process(pscClk,reset)beginif (pscClk'event and pscClk = '1') thenif (reset = '0') thencntOut --delayEn