Chap. 6 Dataflow Modeling
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Dataflow Modeling
Continuous Assignments Delays Expressions, Operators and Operands Operator Types Examples Summary
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Continuous Assignments - I
Assign a logic value to a wire/net Syntax
Continuous_assign::= assign [drive_strength] [delay] list_of_assignments;
List_of_net_assignments::=net_assignment{, net_assignment}
Net_assignment::=net_lvalue = expression Default drive_strength: strong1 or strong0 Delay: propagation time from inputs to output
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Continuous Assignments - II
Constraints LHS of assignment (=) must be scalar net or vecto
r net (rather than reg or vector reg) Once the value of RHS expression changes, the v
alue of assigned wire also changes accordingly The expression of RHS can be reg, wire or functio
n Delay controls the update time of LHS when the v
alue of RHS has changed like gate delay
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An Example of Continuous Assignments
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Implicit Continuous Assignment Perform a wire assignment when declaring
the wire wire out;
assign out = in1 & in2; (equals the following) wire out = in1 & in2;
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Implicit Net Declaration
Perform assignment for an un-declared wire wire i1, i2;
assign out = i1 & i2; // wire out has not been
// declared
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Dataflow Modeling
Continuous Assignments Delays Expressions, Operators and Operands Operator Types Examples Summary
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Delays
Regular Assignment Delay Implicit Continuous Assignment Delay Net Declaration Delay
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Regular Assignment Delay
assign #10 out = in1 & in2;
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Implicit Continuous Assignment Delay wire #10 out = in1 & in2; (equals the
following) wire out;
assign #10 out = in1 & in2;
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Net Declaration Delay
wire #10 out;
assign out = in1 & in2; (equals the following) wire out;
assign #10 out = in1 & in2;
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Dataflow Modeling
Continuous Assignments Delays Expressions, Operators and Operands Operator Types Examples Summary
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Expressions
Combine operator and operand to output a result a^b addr1[20:17] + addr2[20:17] in1 | in2
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Operands
Data type - constants, integers, real, nets, registers, times, bit-select, part-select, memory or function calls
Integer count, final_count; final_count = count + 1; real a, b, c; c = a – b; reg [15:0] reg1, reg2; reg [3:0] reg_out; reg_out = reg1[3:0] ^ reg2[3:0]; reg ret_value; ret_value = calculate_parity(A, B);
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Operators
Perform an operation on operands d1 && d2 // && operates on operands d1 and d2 !a[0] B1>>1
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Dataflow Modeling
Continuous Assignments Delays Expressions, Operators and Operands Operator Types Examples Summary
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Operator Classes
Arithmetic Logical Relational Equality Bitwise Reduction Shift Concatenation Conditional
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Operation Types - I
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Operator Types - II
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Arithmetic Operators - I
Binary Operator (+, -, *, /, **, %) A = 4’b0011; B = 4’b0100;
D = 6; E = 4;
A * B
D / E
A + B
B – A
F = E ** F;
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Arithmetic Operators - II
Binary Operator (+, -, *, /, **, %) in1 = 4’b101x; in2 = 4’b1010; sum = in1 + in2; // sum is 4’bx 13 % 3 16 % 4 -7 % 2 7 % -2
Unary Operator (+, -) -4 +5
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Logical Operators
&&(logic-and), ||(logic-or), !(logic-not) A = 3; B = 0;
A && B
A || B
!A
!B A = 2’0x; B = 2’b10;
A && B ( a == 2) && (b == 3)
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Relational Operators
>, <, <=, >= A = 4, B = 3
X = 4’b1010, Y = 4’b1101, Z = 4’b1xxx
A <= B
A > B
Y >= X
Y < Z
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Equality Operators - I
Logic Equality (==, !=) Event Equality (===, !==)
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Equality Operators - II
A = 4, B = 3 X = 4’b1010, Y = 4’b1101 Z = 4’b1xxz, M = 4’b1xxz, N = 4’b1xxx A == B // 0 X != Y // 1 X == Z // x Z === M // 1 Z === N // 0 M !=== N // 1
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Bitwise Operators - I
~(Negation), & (and), | (or), ^ (xor), ^~ (xnor)
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Bitwise Operators - II
X = 4’b1010, Y = 4’b1101, Z = 4’b10x1 ~X // 4’b0101 X & Y // 4’b1000 X | Y // 4’b1111 X ^ Y // 4’b0111 X ^~ Y // 4’b1000 X & Z // 4’b10x0 X = 4’b1010, Y = 4’b0000 X | Y // 4’b1010 X || Y // 1
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Reduction Operator
&, ~&, |, ~|, ^, ~^ X = 4’b1010
&X // 1’b0
|X // 1’b1
^X // 1’b0, can be used to count even parity
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Shift Operator
>>(right shift), <<(left shift), >>>(arithmetic right shift), <<<
X = 4’b1100 Y = X >> 1; // 4’b0110 Y = X << 1; // 4’b1000 Y = X << 2; // 4’b0000 Integer a, b, c; a = 0; b = -10; c = a + (b >>> 3);
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Concatenation Operator
{, } A = 1’b1, B = 2’b00, C = 2’b10, D = 3’b110
Y = { B, C }
Y = { A, B, C, D, 3’b001 }
Y = { A, B[0], C[1] }
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Replication Operator
reg A;
reg [1:0] B, C;
reg [2:0] D;
A = 1’b1; B = 2’b00; C = 2’b10; D = 3’b110;
Y = {4{A}}
Y = {4{A}, 2{B}}
Y = {4{A}, 2{B}, C}
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Condition_expr ? ture_expr : false_expr;
assign addr_bus = drive_enable ? Addr_out : 36’bz; assign out = control ? in1 : in0; Assign out = ( A == 3 ) ? ( control ? x : y ) : ( control ? m : n );
Conditional Operator
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Operator Precedence
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Dataflow Modeling
Continuous Assignments Delays Expressions, Operators and Operands Operator Types Examples Summary
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Design 4-to-1 Multiplexer
Using logic expression Using conditional operator
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Using Logic Expression
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Using Conditional Operator
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Design 4-bit Full Adder
Using addition (+) and concatenation ({, }) Carry look ahead
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Using Addition and Concatenation Operator (DataFlow Modeling)
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Carry Look Ahead Full Adder - I
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Carry Look Ahead Full Adder - II
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4-bit ripple carry counter
4-bit Ripple Carry Counter
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Negative Triggered D Flip-Flop with Clear
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4-bit Ripple Carry Counter in Verilog
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T Flip-Flop in Verilog
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D Flip-Flop in Verilog
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Testbench for 4-bit Ripple Counter - I
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Testbench for 4-bit Ripple Counter - I
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Simulation Result
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Dataflow Modeling
Continuous Assignments Delays Expressions, Operators and Operands Operator Types Examples Summary
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Summary
Continuous Assignment (expression, operator and operand)
Define delays in continuous assignment Various operators in Verilog
Arithmetic, logical, relational, equality, bitwise, reduction, shift, concatenation, replication, conditional
Conditional operator is equivalent to “if-then-else” statement