chapter 3: dataflow modeling - john wiley & sons
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Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-1
Chapter 3: Dataflow Modeling
Department of Electronic Engineering
National Taiwan University of Science and Technology
Prof. Ming-Bo Lin
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-2
Syllabus
ObjectivesDataflow modelingOperandsOperators
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-3
Objectives
After completing this chapter, you will be able to:Describe what is the dataflow modelingDescribe how to use continuous assignmentsDescribe how to specify delays in continuous assignmentsDescribe the data types allowed in Verilog HDLDescribe the operation of the operators used in Verilog HDLDescribe the operands may be used associated with a specified operator
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-4
Syllabus
ObjectivesDataflow modeling
IntroductionContinuous assignmentExpressionsDelays
OperandsOperators
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-5
Why Dataflow ?
Any digital system interconnecting registers combinational logic circuits
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-6
Features of Dataflow
A powerful way to implement a designLogic synthesis tools can be used to create a gate-level netlistRTL (register transfer level) is a combination of dataflow and behavioral modeling
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-7
Syllabus
ObjectivesDataflow modeling
IntroductionContinuous assignmentExpressionsDelays
OperandsOperators
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-8
Basic Statements
Continuous assignmentsVariations
Net declaration assignmentsImplicit net declarations
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-9
Continuous Assignments
Syntaxassign [delay] net_lvalue = expression;assign [delay] net1_lvalue = expr1,
[delay] net2_lvalue = expr2, ...,
[delay] netn_lvalue = exprn;
assign #5 {c_out, sum[3:0]} = a[3:0] + b[3:0] + c_in;
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-10
Net Declaration Assignments
Only one net declaration assignment per net
wire out; // regular continuous assignment assign out = in1 & in2;
wire out = in1 & in2; // net declaration assignment
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-11
Implicit Net Declarations
A feature of Verilog HDL
wire in1, in2; assign out = in1 & in2;
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-12
Syllabus
ObjectivesDataflow modeling
IntroductionContinuous assignmentExpressionsDelays
OperandsOperators
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-13
Expressions
expression = operators + operandsOperatorsOperands
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-14
Operators
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-15
Operands
constantsparametersnets variables (reg, integer, time, real, realtime)bit-select part-selarray elementfunction calls
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-16
Syllabus
ObjectivesDataflow modeling
IntroductionContinuous assignmentExpressionsDelays
OperandsOperators
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-17
Three Ways of Specifying Delays
Regular assignment delayNet declaration assignment delayNet declaration delay
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-18
Regular Assignment Delays
The inertial delay model is defaulted
wire in1, in2, out; assign #10 out = in1 & in2;
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-19
Net Declaration Assignment Delays
To specify both the delay and assignment on the netThe inertial delay model is defaulted
// net declaration assignment delaywire #10 out = in1 & in2;
// regular assignment delaywire out;assign #10 out = in1 & in2;
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-20
Net Declaration Delays
Associate a delay value with a net declaration
// net delayswire #10 out; assign out = in1 & in2;
// regular assignment delaywire out;assign #10 out = in1 & in2;
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-21
Syllabus
ObjectivesDataflow modelingOperands
ConstantsData types
Operators
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-22
Types of Constants
integerreal string
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-23
Integer Constants
Simple decimal form
-12312345
Base format notation16’habcd2009 4’sb1001 // -7
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-24
Real Constants
Decimal notation 1.5 //.3 // illegal1294.872 //
Scientific notation15E1232E-626.176_45_e-12
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-25
String Constants
A sequence of characters enclosed by double quotes ("")Can only be specified in a single lineEach character is represented as an 8-bit ASCII code
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-26
Syllabus
ObjectivesDataflow modelingOperands
ConstantsData types
Operators
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-27
Data Types
NetsAny hardware connection points
VariablesAny data storage elements
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-28
Types of Variable Data Types
reginteger time realrealtime
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-29
The reg Variable
Hold a value between assignmentsMay be used to model hardware registersExamples
reg a, b; reg [7:0] data_a; reg [0:7] data_b; reg signed [7:0] d;
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-30
The integer Variable
Contains integer valuesHas at least 32 bitsIs treated as a signed reg variable with the LSB being bit 0
integer i, j; integer data[7:0];
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-31
The time Variable
Used for storing and manipulating simulation timeUsed in conjunction with the $time system taskOnly unsigned value and at least 64 bits, with the LSB being bit 0
time events; time current_time;
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-32
The real and realtime Variables
Cannot use range declaration Defaulted to zero (0.0)
real events; realtime current_time;
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-33
Vectors
A vector = multiple bit width[high:low] or [low:high]The leftmost bit is the MSBinclude nets and reg data types
A scalar = 1-bit vector
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-34
Bit-Select and Part-Select
integer and time are allowedreal and realtime are not allowed Constant part select: data_bus[3:0], bus[3]Variable part select:
[<starting_bit>+:width]: data_bus[8+:8] [<starting_bit>-:width]: data_bus[15-:8]
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-35
Array and Memory Elements
All net and variable data types are allowed An array element can be a scalar or a vector
wire a[3:0]; reg d[7:0]; wire [7:0] x[3:0]; reg [31:0] y[15:0]; integer states [3:0]; time current[5:0];
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-36
MemoryMemory
model ROM, RAM, or register filesReference
a whole word ora portion of a word of memory
reg [7:0] mema [7:0]; reg [7:0] memb [3:0][3:0]; wire sum [7:0][3:0];
mema[4][3] mema[5][7:4] memb[3][1][1:0] sum[5][0]
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-37
Syllabus
ObjectivesDataflow modelingOperandsOperators
Bitwise operatorsArithmetic operatorsConcatenation/replication operatorsReduction operatorsLogical operatorsRelational/equality operatorsShift operatorsConditional operator
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-38
Bitwise Operators
A bit-by-bit operationA z is treated as x The shorter operand is zero-extended
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-39
An Example --- A 4-to-1 MUX
// using basic and, or , not logic operatorsassign out = (~s1 & ~s0 & i0) |
(~s1 & s0 & i1) |(s1 & ~s0 & i2) |(s1 & s0 & i3) ;
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-40
Syllabus
ObjectivesDataflow modelingOperandsOperators
Bitwise operatorsArithmetic operatorsConcatenation/replication operators Reduction operatorsLogical operatorsRelational/equality operatorsShift operatorsConditional operator
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-41
Arithmetic Operators
The result is x if any operand bit has a value xNegative numbers are represented as 2’s complement
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-42
Syllabus
ObjectivesDataflow modelingOperandsOperators
Bitwise operatorsArithmetic operatorsConcatenation/replication operatorsReduction operatorsLogical operatorsRelational/equality operatorsShift operatorsConditional operator
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-43
Concatenation/Replication Operators
Concatenation operatory = {a, b[0], c[1]};Replication operatory = {a, {4{b[0]}}, c[1]};
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-44
An Example --- A 4-Bit Full Adder
// specify the function of a 4-bit adderassign {c_out, sum} = x + y + c_in;
sum_1[4:0]
+ sum[3:0]
[3:0]
[4:0][3:0] [3:0][3:0]
c_out[4]
sum[3:0][3:0]
c_in
y[3:0] [3:0]
x[3:0] [3:0]
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-45
A 4-Bit Two’s Complement Adder
// specify the function of a two's complement adderassign t = y ^ {4{c_in}}; assign {c_out, sum} = x + t + c_in;
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-46
Syllabus
ObjectivesDataflow modelingOperandsOperators
Bitwise operatorsArithmetic operatorsConcatenation/replication operatorsReduction operatorsLogical operatorsRelational/equality operatorsShift operatorsConditional operator
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-47
Reduction Operators
Perform only on one vector operandCarry out a bit-wise operationYield a 1-bit resultWork bit by bit from right to left
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-48
A 9-Bit Parity Generator
// dataflow modeling using reduction operatorassign ep = ^x; // even parity generatorassign op = ~ep; // odd parity generator
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-49
An All-Bit-Zero/One Detector
// dataflow modelingassign zero = ~(|x); // all-bit zero assign one = &x; // all-bit one
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-50
Syllabus
ObjectivesDataflow modelingOperandsOperators
Bitwise operatorsArithmetic operatorsConcatenation/replication operatorsReduction operatorsLogical operatorsRelational/equality operatorsShift operatorsConditional operator
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-51
Logical Operators
Always evaluate to a 1-bit value, 0, 1, or xThe result is x (a false condition) if any operand bit is x or z
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-52
Syllabus
ObjectivesDataflow modelingOperandsOperators
Bitwise operatorsArithmetic operatorsConcatenation/replication operatorsReduction operatorsLogical operatorsRelational/equality operatorsShift operatorsConditional operator
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-53
Relational Operators
The result is 1 if the expression is true and 0 if the expression is false
Return x if any operand bit is x or z
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-54
Equality Operators
Compare the two operands bit by bitThe shorter operand is zero-extendedReturn 1 if the expression is true and 0 if the expression is false
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-55
Equality Operators
The operators (==, !=) yield an x if any operand bit is x or z
The operators (===, !==) yield a 1 if the two operands exactly match 0 if the two operands not exactly match
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-56
A 4-B Magnitude Comparator
// dataflow modeling using relation operatorsassign Oaeqb = (a == b) && (Iaeqb == 1); // =assign Oagtb = (a > b) || ((a == b)&& (Iagtb == 1)); // >assign Oaltb = (a < b) || ((a == b)&& (Ialtb == 1)); // <
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-57
Syllabus
ObjectivesDataflow modelingOperandsOperators
Bitwise operatorsArithmetic operatorsConcatenation/replication operatorsReduction operatorsLogical operatorsRelational/equality operatorsShift operatorsConditional operator
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-58
Shift Operators
Logical shift operatorsArithmetic shift operators
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-59
An Example of Shift Operators
input signed [3:0] x;output [3:0] y;output signed [3:0] z;
assign y = x >> 1; assign z = x >>> 1;
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-60
Syllabus
ObjectivesDataflow modelingOperandsOperators
Bitwise operatorsArithmetic operatorsConcatenation/replication operatorsReduction operatorsLogical operatorsRelational/equality operatorsShift operatorsConditional operator
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-61
The Conditional Operator
Usage: condition_expr ? true_expr: false_expr;If condition_expr = x or z: the result = true_expr & false_expr (0 and 0 gets 0, 1 and 1 gets 1, others gets x )
For example
assign out = selection ? in_1: in_0;
Chapter 3: Dataflow Modeling
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 3-62
An Example --- A 4-to-1 MUX
// using conditional operator (?:)assign out = s1 ? ( s0 ? i3 : i2) : (s0 ? i1 : i0) ;