Download - 04 Pipelined
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M. Dessouky - Integrated Circuits Lab. 1
PipelinePipelinedd ADCADC
Mohamed DessoukyAin Shams University
I.C. Lab.
M. Dessouky - ASU - ICL2
Flash
Two-step
Pipelined
Interpolating
Folding
Time-interleaved
Successive Approximation
Algorithmic
Integrating(Rampfunction)
Delta-Sigma
High Speed,Low-to-Medium Resolution
Medium Speed,Medium Resolution
Low-to-Medium Speed,High Resolution
ADC ArchitecturesADC Architectures
Speed ↑↑↑↑ , Resolution ↓↓↓↓
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ADC ApplicationsADC Applications
M. Dessouky - ASU - ICL4
ADC ArchitecturesADC Architectures
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OutlineOutline
• Introduction
• Stage Errors
• Digital Error Correction
• Example
M. Dessouky - ASU - ICL6
Flash ADC (Flash ADC (ParallelParallel) )
• Input is simultaneously compared with 2N–1 reference voltages.• Reference voltages typically derived from a resistor string.
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TwoTwo--StepStep ADC ADC –– OperationOperation
0111 Result_____ 0011 LSB0100 MSB
+ 1 10
1
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2nd ADCFine
DAC
V -DACin
1st ADCCoarse
M. Dessouky - ASU - ICL8
TwoTwo--StepStep ADCADC
• Number of comparators = 2M + 2Q – 2.• Example: # of comparators for 8 bits
– Flash = 28 – 1 = 255– Two-Step (5-5) = 24 + 24 – 2 = 30
• Compared to the Flash A/D converter, the two-step A/D converter trades speed for reduced complexity and power.
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PipelinedPipelined ADCADC
• General extension of the two-step ADC with interstage gain.• Trade conversion speed for latency using interstage SHA• Speed is limited by conversion speed of one stage.
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Multiplying-DAC (MDAC)
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PipelinedPipelined ADCADC
• Throughput is independent of the number of stages.• Number of components grows linearly with resolution.
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Stage Transfer Stage Transfer FunctionFunction
• Consider a 3-bit pipeline, based on a 1 bit per stage topology.
refnrefninout VDVDVV +−= 2
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Residue
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Precision MultiplyPrecision Multiply--byby--TwoTwo AmplifierAmplifier
21 CC =
floating
floating
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• Phase φφφφ1: both capacitors are charged to Vin0.
• Phase φφφφ2: Since node X is floating, the second capacitor charge istransferred to the first one such that
02 inout VV =
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Pipeline 1Pipeline 1--Bit Stage Bit Stage ImplementationImplementation
• In CMOS technologies, the gain, subtraction, and SHA functions are readily merged into a single SC block.
• A precision multiply-by-two amplifier. Instead of grounding C1, it is connected to ±Vref to perform the required subtractionthrough an inverting amplifier configuration.
• Digital correction is used to alleviate comparator requirements.
refnrefnnn VDVDVV +−=− 21
M. Dessouky - ASU - ICL14
OutlineOutline
• Introduction
• Stage Errors
• Digital Error Correction
• Example
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The Contribution of Stage ErrorsThe Contribution of Stage Errors
• Input referred error:
• Each error must be < LSB/2:
• The first stage error is the most significant
∑
1e
∑
ke
∑
2e
∑=
−+=k
iii
in Geee
211
×G ×G×G
112
−+≤ i
Ni GFSe
M. Dessouky - ASU - ICL16
Stage Stage ErrorsErrors
inVε
sfcycleDuty _ t
Settling error
ADC comparator errors
+
Offset
Residue
Gain/Nonlinearity error
AV
SV
DAC output errors
SHA2M
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SubSub--ADC ErrorsADC Errors
• Offset, Gain, and Nonlinearity
• All move the decision levels of the ADC
• Digital correction & redundancy can eliminate such errors
• Only the last stage errors are not corrected. However, their
contribution to the overall ADC errors are divided by the
product of all inter-stage gains.
M. Dessouky - ASU - ICL18
SubSub--DAC ErrorsDAC Errors
• Offset: – Equivalent to an offset in the sub-ADC– Can be corrected by digital correction/redundancy
• Gain error:– Equivalent to gain error in the sub-ADC + inter-stage
gain error– Gain error in the sub-ADC can be corrected by digital
correction/redundancy– Inter-stage SHA gain error, see later
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SubSub--DAC Errors (contd.)DAC Errors (contd.)
• Nonlinearity: Error that depends on the DAC output– Must be < LSB/2
N-M(i-1) ≡ The number of bits remaining to be determined by the stage i and the following stages
– The DAC in each stage must be at least as linear as the combined resolution of this and the later stages.
– The first stage DAC must be as linear as the entire ADC.– 1-bit DACs are inherently linear
1111 22 +−+− ≤≤∴ Nii
Nii FS
GFS
Gδδ or
( )[ ] 1122 +−−≤∴= iMNi
M FSG δ s
M. Dessouky - ASU - ICL20
SHA Gain ErrorsSHA Gain Errors
• Offset:– Equivalent to DAC offsets– Can be corrected by digital correction/redundancy
• Gain error:– In the first stage, no quantization has occurred yet, SHA
gain error just causes ADC gain error.– In the following stages, the resulting error must be at
least as linear as the combined resolution of this and the later stages.
• Nonlinearity error:– Same as the gain error, but includes also the first stage.
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Errors SummaryErrors Summary
≤ Resolution of this and following stagesNonlinearity
≤ Resolution of this and following stagesGain
digital correctionOffsetSHA
≤ Resolution of this and following stagesNonlinearity
digital correction + SHA Gain errorGain
digital correctionOffsetDAC
digital correctionOffset, Gain, & Nonlinearity
Sub-ADC
RequirementErrorBlock
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OutlineOutline
• Introduction
• Stage Errors
• Digital Error Correction
• Example
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Input rangeextension withone additionalbit
Digital Digital ErrorError Correction in 2Correction in 2--stepstep ADC: ADC: IdeaIdea
Out of range(underflow)
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Offset
Digital Digital ErrorError Correction in 2Correction in 2--stepstep ADC: ADC: ProcedureProcedure
0111 Result_____ 0010 Offset0001 LSB1000 MSB
−+
10 1
100
0
Input rangeextension withone additionalbit��
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�� ±2 LSB of comparator offset can be tolerated in the coarse ADC.
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Digital Digital ErrorError CorrectionCorrection
• 1-bit pipeline stage.• Offset in sub-ADC transition level (Vth = 0V) causes the output
to exceed the output range ±±±±Vref.• To solve this problem
– Extend output range and use extra bit for correction! – Decrease the interstage gain to maintain the output range
±±±±Vref.
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Residue 2nd stage
V1
Residue 1st stage
V1
Digital Digital ErrorError Correction: Correction: IdeaIdea3-bit PipelinedADC
Digital Correction
110 Result_____ 001 Offset001 LSB110 MSB
−+ 1
10 1
10
1 extra bit for correction
Lower gain2 instead of 22 = 4
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V1
2 bits 1 bit
refV=×∆ 2
222
2 2refref
N
VVFS ===∆
2refV
+
2refV
−
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Residues
Digital Digital ErrorError Correction: Correction: withwith OffsetOffset
1/4 Vref
1/4 Vref
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110 Result_____ 001 Offset011 LSB100 MSB
−+ 1
1
10
0 1
• First ADC error can be as large as ¼ Vref and still in input range.• Both addition and subtraction operations are needed.• To use only addition, subtract the offset from the input signal
directly.• Offset = 1 LSB = 2 Vref / 23 = Vref / 4.
Same input 110
M. Dessouky - ASU - ICL28
Digital Digital ErrorError Correction: Correction: ModifiedModified StageStage
• To use only adders in the digital error correction circuit.• Add intentional –¼ Vref = 1 LSB offset at the input.• Can be transferred as –¼ Vref offset at input and output of
ADC/DAC in circuit implementations.��
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Digital Digital ErrorError Correction: Correction: ModifiedModified StageStage
Residues
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• With ¼ Vref offset at input, no need for offset subtraction.• First ADC error can be as large as ¼ Vref and still corrected.• Since the last segment in the first stage (11) is redundant,
i.e. can be corrected for, we can totally remove it.
110 Result_____ 010 LSB100 MSB
+ 10
10
Same input 110
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M. Dessouky - ASU - ICL30
Digital Digital ErrorError Correction: 1.5 bit/stageCorrection: 1.5 bit/stage
• Only two levels or 1.5 bits.• Equivalent to 2 bits with correction in the following stage.• Most popular pipeline stage. Only 2 comparators.• For N-bit converter with 1.5 bit/stage, N-1 stages are
required: The first stage provides 2 bits, while other stages provide only 1 bit each reserving the second bit for digital correction.
Residue
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001
d1
2* Vin + Vref-Vref0Vin<-Vref/42* Vin01-Vref/4<Vin<Vref/4
2* Vin - VrefVref0Vin>Vref/4
ResidueDAC Outputd0Vin
1.5 bit/stage: Transfer 1.5 bit/stage: Transfer FunctionFunction
Vref
-Vref
Vref/4
-Vref/400
01
10
thresholds
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1.5 bit/stage: SC 1.5 bit/stage: SC ImplementationImplementation
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OutlineOutline
• Introduction
• Stage Errors
• Digital Error Correction
• Example
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ExampleExample: 10: 10--bit ADC bit ADC –– 1.5 bit/stage1.5 bit/stage
• 9 stages.• First stage gives two bits• Stage 2 to 9 give one bit + one bit for digital correction of
the previous stage.
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ExampleExample: 10: 10--bit ADC bit ADC –– Last StageLast Stage
• The Nth stage cannot be digitally corrected (since there are no following stages)
• It is implemented by only a Flash ADC– have standard thresholds. – If digitally corrected offsets are used, the top code
1111… will be missing which is typically not critical.
Vref
-Vref
Vref/4
-Vref/400
01
10Vref
-Vref
Vref/2
-Vref/2
0
00
01
10
11
2-bit flash standard thresholds2-bit digital-correction thresholds
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Number of bits/StageNumber of bits/Stage
• Tradeoff between speed, power, and accuracy of each stage. • For fewer number of bits per stage,
+ the sub-ADC comparator requirements are more relaxed+ the inherent speed of each stage is faster because the
inter-stage gain is lower allowing higher speed due to the fundamental gain-bandwidth tradeoff of amplifiers.
– more stages are required if there are fewer bits per stage. – the noise and gain errors of the later stages contribute
more to the overall converter inaccuracy because of the low inter-stage gain.
• High-speed, low-resolution specifications favor a low number of bits per stage.
• Low-speed, high-resolution specifications tend to favor higher number of bits per stage.
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ReferencesReferences• Bruce Wooley & Katelijn Vleugels, « EE315: VLSI Data Conversion
Circuits – Handouts », Department of Electrical Engineering, Stanford University, http://www.stanford.edu/class/ee315/
• Paul G. A. Jespers, « Integrated Converters: D to A and A to D Architectures, Analysis and Simulation », Oxford University Press, 2001.
• Georges Chien, «High-Speed, Low-Power, Low Voltage PipelinedAnalog-to-Digital Converter », M.Sc., University of California, Berkeley, 1996.
• S. Lewis, «Optimizing the Stage Resolution in Pipelined, Multistage, Analog-to-Digital Converters for Video-Rate Applications», IEEE TCAS-II, Vol. 39, No. 8, August 1992.
• Andrew Masami Abo, «Design for Reliability of Low-voltage, Switched-capacitor Circuits », Ph.D., University of California, Berkeley, 1999.
• Behzad Razavi, « Design of Analog CMOS Integrated Circuits », McGraw-Hill, 2001.