PIPELINED ADC

A 10 bit Pipelined ADC using Time-Interleaved SAR ADC for Front-End Stages

Under the guidance ofMr. Noorullah Khan

By Ghouse Pasha Shaik 1604-12-744-010

AimTo design a pipelined ADC of 10 bit 300MSamples/s using time interleaved SAR ADC.

To achieve low power consumption at 300MHz sampling rate at 1.8V power supply.

AbstractA 10 bit 300 MSamples /s pipelined ADC using time interleaved SAR ADC.

By replacing front end pipelined stages with energy efficient SAR-ADC, power hungry S & H can be removed.

Rail to rail input can be used.

In addition feedback factor of the first MDAC can be increased which reduces the power consumption of the first opamp.

Problem StatementDemand for high speed (300MHz), high resolution(10 bit) and low power ADCs. As Sampling rate increases the energy efficiency of pipelined ADC decreases drastically.To mitigate these limitations we use time interleaving techniques.

Literature survey Systematic design of 10 bit 50 MS/s pipelined ADC, by kehan Zhu, Sakkarapani Balgopal, and Vishal Saxena.2013technique: opamp sharingPower consumption reduced drasticallySNR:58.9dBENOB:9.3SFDR:64 dBPower: 24mWTechnology: 130nm

A 10 bit 40 MS/s pipelined ADC with a wide range operating temperature for wave applications by Ghil-Geun Oh, Chang Kyo Lee, and Seung-Tak Ryu.2014 suitable for wireless access in vehicular environment applications.This technique is temperature sensitive.Technology:180nmPower:23.4mWSNDR: 55dB

A 27mW 10 bit 125MSPS Charge Domain pipelined ADC by Zhenhai Chen, Songren huang, Zongguang Yu.2010It uses PVT boosted charge transfer circuit is used.Power: 27mWSpeed: 125 MSPSTechnology: 180nmSupply: 1.8VSFDR: 67.7dBSNDR: 57.3dBENOB: 9

A 10 bit 300MSamples/s Pipelined ADC using Time-Interleaved SAR ADC for front-end Stages by Young Hwa Kim, Jaewon Lee and Seong Cho.2010. By replacing the front end pipelined stages with energy efficient SAR-ADC, power hungry sample and hold amplifier can be removed.Technology: 90nmENOB: 8.88Figure of merit: 545 fJ/ Conv

ADC TYPESNyquist-Rate ADCs Flash ADCs Sub-Ranging ADCs Folding ADCs Pipelined ADCs Successive Approximation (Algorithmic) ADCs Integrating (serial) ADCsOversampling ADCs Delta-Sigma based ADCs

ADC Architectures Flash ADCs: High speed, but large area and high power dissipation. Suitable for low-medium resolution (6-10 bit).

Sub-Ranging ADCs: Require exponentially fewer comparators than Flash ADCs. Hence, they consume less silicon area and less power.

Pipelined ADCs: Medium-high resolution with good speed. The trade-offs are latency and power.

Successive Approximation ADCs: Moderate speed with medium-high resolution (8-14 bit). Compact implementation.

Integrating ADCs or Ramp ADCs: Low speed but high resolution. Simple circuitry.

Delta-Sigma based ADCs: Moderate bandwidth due to oversampling, but very high resolution thanks to oversampling and noise shaping.

FLASH ADCHigh SpeedMedium resolutionResolution is 6-10 bits

Drawbacks:More hardwareNeed more comparators

3 bit Flash ADC architecture

Pipelined ADCLow powerHigh speedLow voltageGood resolution upto 14 bits

Block diagram of pipelined ADC

Pipelined ADC operation

Architecture 1.5bits/stage1 bit stage implementation leads to offset error in comparator.So 1 bit stage is not used in practical pipelined ADCs.A 1.5 bit is actually 2 bit stage, 0.5 bit is redundant value which is removed by correction logic.

Latency and Correction AlgorithmFor a 8 bit pipelined ADC with 1.5 bit stage resolution latency is 7 clock cycles.Correction algorithm circuitry is to reduce the effects of offset errors non linearity in sample and hold and sub-ADC.

Architecture of proposed Pipelined ADC

AdvantagesReplace S & HRail to rail input so that we can reduce the power supplySAR ADC consists only passive components except comparator and thus achieve more energy efficient.The feedback factor of MDAC can be reduced by 2.(2^m/2)

Timing diagram of front end stage and the following stages

Expected ResultsReduce the power consumption using SAR ADC allows rail to rail input capability.It eliminates the need for SHA in conventional ADCs.ENOB 8.8 t0 9 bits SNDR 55.1dB to 59dBFOM 545 fJ/Conv to 600fJ/Conv

Comparator

Comparator Output

Thermometer to binary encoder

Truth Table

Flash ADC Output

Design of op-ampOpamp schematicOpamp specifications

Design of op-ampDesign summary of op-ampSimulation of op-amp

AC Analysis

Open loop Gain (Avo) = 4216.96 = 72.5 dB Unity Gain Bandwidth = 49.79 MHz Phase Margin = 180 + Phase at 0 dB gain = 180 + (-117.9) = 62.1 deg From Phase Margin, it is clear that the Op-Amp is Stable

Thank You