DOM Input Issues:PMT Output, ATWD input,

and Trigger ComparatorDesign Criteria

ICENOTE105 DOM input issues

Gerald Przybylski

Lawrence Berkeley National LaboratoryAugust 22, 2002

Rev: May 14, 2003

Rev: Aug 25, 2004

Input Referenced Noise

The input amplifier to the most sensitive input of the ATWD contributes the dominant noise (excluding the PTM itself) in that channel. For the selected device, the manufacturer’s data sheet specifies 3.5nV/Hz noise. The x3 gain configuration of the amplifier results in a bandwidth of about 200 MHz. Therefore, the input referenced noise is about 50 uV. The resistor in series with the inputs of the ATWD, however, limit the bandwidth to about 100 MHz.

The criteria for acceptance is that the input referenced noise be a small fraction of the PMT response to a single photon (photoelectron), or mean SPE amplitude.

ATWD Input Noise

• The RMS noise of an ATWD input is about one ADC count, or 2 mV.

• Each event is captured on a set of 128 sample capacitors, each of which is digitized by a dedicated ADC channel. Each ADC channel has its own threshold variation which adds to the (Wilkinson) common ramp voltage. The RMS variation of an ATWD channel is about five counts (10 mV at a typical gain setting).

Criteria for acceptance is that the digitizer quantization noise, the input noise, and the pattern noise be a small fraction of the mean SPE amplitude measured in ADC counts of the ATWD.

Mean SPE in ADC Counts

The arbitrary decision has been made that the mean SPE amplitude should be 40 ADC counts, or about 80 mV for typical ATWD, and PMT operating conditions.

ATWD Input Dynamic Range

1. The arbitrary decision has been made that the a 200 SPE signal delivered to the ATWD should have an amplitude of 1Volt peak.

2. The arbitrary decision has been made that the PMT output for saturated pulse height should not exceed the span of the ATWD.

The Least Sensitive ATWD Input

Item 1 dictates the PMT HV setting which will produce a mean SPE amplitude of 5mV delivered to the amplifiers preceding the ATWD.

Item 2 dictates the scaling of the PMT signal in the least sensitive input of the ATWD. AMANDA string 18 experience leads us to expect that the PMT output will saturate at about 2V. If so, the net gain between the PMT anode and the least sensitive input of the ATWD is unity. Kael Hanson’s measurements of IceCube standard PMTs suggests that rescaling will be necessary to accommodate the higher output of the tube. The net gain is set at 0.25.

The Most Sensitive ATWD Input

The mean SPE amplitude in ADC counts times the ADC step size divided by the mean SPE amplitude in volts gives the net gain preceding the ATWD input. (40count/SPE x 2mV/count) / 5mV/SPE = 16.

Given the first stage (AD8014) gain of 3.0, the second stage (HFA1135) gain must be 5.33.

Actually, the gains of the two stages were selected so that both amplifiers had approximately the same bandwidth at the maximum output amplitude they were expected to deliver.

Additionally, the second stage has limiting/clamping which are protects the ATWD input from excessive drive. [RampTop +0.7V..0.24V]

The Mid-level ATWD Input

• The arbitrary decision has been made that the second most sensitive input to the ATWD should have a stage roughly the gain of the geometric mean between the most and least sensitive input. Therefore, the stage gain is a factor of 2. Since the expected signal amplitude is high, amplifier noise is negligible compared with quantization noise, amplifier noise, ATWD input noise, and pattern noise.

ATWD Pedestal Pattern

• As explained before, the ATWD pedestal pattern is a systematic source of measurement error.

• The same ADC subsystem is used to digitize each ATWD input.

• The pedestal pattern can be recorded, and subsequently subtracted from the digitized signal as a correction.

• The correction can be performed in firmware, in software in the DOM, in software, in the string processor, or off-line. Each option has advantages…

• Pedestal subtraction before compression or zero suppression or feature extraction is attractive.

PMT Anode “Compression”Past experience with similar photomultiplier tubes leaves the

impression that the the anode output is linear to about half of saturation amplitude.

If the non-linear performance of the PMTs can be characterized, and is similar from one PMT and another, then effective dynamic range of the DOM can be extended above 200 PE, at the sacrifice of some precision.

The characterization of the non-linearity is beyond the scope of this discussion, however, the characterization of the compression may yield valuable physics information.

In-ice calibration using flasher boards designed and fabricated by U of Wisconsin is part of the IceCube calibration suite.

Dynamic Range Revisited

• Since the gain of the photomultiplier depends on its anode voltage, the PMT HV must be adjusted to deliver the correct value of mean SPE to the DOM analog input. The adjustment and calibration procedures are beyond the scope of this discussion.

• Choosing a different (lower or higher) mean SPE value will result in different PMT saturation characteristics, which might, or might not, be advantageous for physics data acquisition, compression, and analysis.

Event Trigger InputRapid response to PMT signals places great demands on the trigger system, motivating

the selection of fast voltage comparators to initiate the ATWD capture circuitry. The flattest, lowest ‘propagation delay vs. input overdrive’ is most desirable. The input overdrive specification is indicative of the comparator input noise band and gain. For small pulse input, one must overcome the noise band to induce the comparator to change state. 3 to 5 mV signal is necessary to cause the comparator change its output state. Additionally, the comparators are wired to latch into the triggered state until reset (a feature precluding oscillation). Latching may also be done in the FPGA

To insure that the mean SPE reliably triggers the comparator, the mean SPE amplitude at the comparator should be several times the comparator threshold. A factor of five seems to be a satisfactory compromise between overdrive to the comparator, and bandwidth reduction related to the gain at which the stage operates.

The recovery time from saturation for the amplifier preceding the trigger comparator can pose a problem if it exceeds the capture time of an event. Recent wide-band, low power products meet the requirements. (e.g., for the AD8014, the 60ns recovery time << 450ns ATWD capture time)

Input Delay

The discriminator preamplifier input is picked off at the input of the strip-line delay line in order to insure that the capture trigger signal reaches the ATWD before the signal itself.

The strip-line delay offsets the triggering propagation delay of: o the discriminator input preamp, and comparator,o gate and I/O cell delay through the FPGA,o 25ns (one clock cycle), maximum, synchronous trigger delay, ando four cascaded gate delays in the ATWD trigger input before cell C0

The strip-line delay line has a distributed resistance series resistance of about 14 resulting in an attenuation factor of about 95/(95+14)= 0.87, or 1.2dB.

Triggering ThresholdsThe two-stage trigger discriminator preamp has a gain of about 10, which

enhances the resolution, in units of PE, of the comparator threshold by a like factor.

The trigger discriminator preamp drives two comparators, each with its own 10-bit, 5V span, controlling DAC, and resolution scaling.

SPE Discriminator Threshold:VTH = (VPEDESTAL – VDAC9)/10

SPE Discriminator Threshold in units of PE:dVTH/step = ((5/1024) x (1/10) x (1/10))/(5mV/PE) = 0.01 PE/step

Multi-PE Discriminator Threshold: VTH = (VPEDESTAL – VDAC8)

Multi-PE Discriminator Threshold in units of PE: dVTH/step = ((5/1024) x (1/10))/(5mV/PE) = 0.1 PE/step

Typical VPEDESTAL is roughly in the middle of the span of the threshold control DACs

The Fast ADC Input Gain and Shaping.

Discussion:The fast ADC signal is picked off at the DOM MB input connector, amplified, and shaped by two cascaded second-order active filter amplifier stages. The cascaded stages have unity gain at DC, so the Fast ADC input tracks the ATWD pedestal voltage. The stage gains are tuned to deliver the desired pulse height of 8 counts for an SPE input. The stage gains are x 2.66 x 3.0 x 3.0

2nd Order Filter Effects

• Preserves the area of a pulse (unity gain).

• Spreads the pulse in time.

• Fall time longer than rise time.

• Suppresses high frequency noise.

• Separable component of 4th order filter.

Gain Configuration Strategy

• If any stage in the fADC analog amplifier chain is to saturate, it should be the last one.

• Gain of 3 for each of the two 2nd order filters yields acceptable values of circuit components. (circuit strays insignificant)

• Use the input buffer stage for isolation and gain adjustment. Tuning yields a value of x 2.66.

• Prudent to design in gain >1 for stability.

• Filtering suppresses the effects of peaking.

Limiting Parameters

• 5mV SPE, 10ns FWHM ≈ triangle pulse with area 50mVns.

• Optimum pulse sampling: 3 or more samples above baseline or pedestal.

• Sampling period = 25 ns

• Mean SPE signal = 8 Counts

• 2mV per ADC count

fADC Operating Parameters• Non-inverting (negative going signals)

• Output biased to ATWD input pedestal

• 50ns rise-time => RC = 22.5e-9 (~ 6 MHz BW) (verified by spice simulation)

• 2 samples on rising edge => 50 ns rise-time

• Stage gains yielding desired signal:Buffer: x 2.66First filter: x 3Second filter: x 3(verified by spice simulation)

The fADC

• Analog Devices AD9215BRU-65- Rated to 65 MSPS- 10 bit parallel output (1023 counts)- Differential input => inverted off-set operation - 80 mW power consumption- Span configurable (=2V for IceCube)- 12-bit pin-for-pin substitute (@~2x power)

Considerations and Restrictions

As the requirements are written, the fADC signal path gain is fixed relative to the ATWD signal path gain.

If the PMT HV changes to alter the dynamic range of the ATWD signal path could (are likely to) result in non-optimal pulse amplitude at the fADC input.

fADC Topics for Reconsideration

• Testing in ’03 and ’04 has not produced pressure to change the fADC amplifier chain gains.

• STF Testing has shown the performance to be satisfactory and consistent.

• Since PMT HV adjustments to extend the dynamic range are possible, a gain controllable amplifier should be considered for the buffer stage of the fADC signal path, however, at this late date (summer ’04), caution precludes radical, speculative changes.i.e. A programmable gain amplifier, like the Analog Devices AD8369 is off the table for IceCube.