performance-optimized gate-first 22-nm soi technology with embedded dram

Performance-optimizedgate-first 22-nmSOI technology withembedded DRAM

G. FreemanP. Chang

E. R. EngbrechtK. J. GiewontD. F. Hilscher

M. LagusT. J. McArdleB. MorgenfeldS. NarasimhaJ. P. Norum

K. A. NummyP. ParriesG. Wang

J. K. WinslowP. AgnelloR. Malik

IBM’s high-performance 22-nm silicon-on-insulator (SOI)technology is the enabling physical foundation of IBM POWER8iprocessors. This paper describes, for the first time in detail, someof the unique aspects of the silicon processing, the features thatenabled the industry-leading chip-level performance, and someaspects of the collaborative approach between technology and designteams that enabled both first-time-right silicon and rapid yieldimprovement. Most critical to the processor functional capabilityand power-performance achievements are the high-density on-chipmemory in the form of embedded DRAM and the high-performanceFET device designs based on a low-parasitic-capacitance gate-firstFET architecture. Extensive on-chip analog functions are enabledby an additional comprehensive set of devices available in thetechnology. Fifteen levels of metal with five metal levels at an80-nm pitch provide the interconnect and power distribution.We describe the pattern resolution enhancement strategy aswell as motivation and structural aspects of the innovative features,from the low-resistance N+ epitaxy substrate under the SOI toa dual-embedded source-drain architecture and a highly scaledgate dielectric.

IntroductionEvery successive generation of semiconductor technologyis crafted with a feature set that combines conventionalBscaling[ (i.e., shrinking dimensions) with increasing levelsof innovation in order to overcome the barriers that materialsand physics present to scaling. Differentiating choices aremade in the technology design to enable the needed productfunctionality, power, and performance, and to facilitatemanufacturability. In this paper, we present the salientfeatures of IBM’s 22-nm silicon-on-insulator (SOI)technology, designed to fulfill the requirements ofhigh-performance processor design, and provide unparalleledon-chip functional integration and transistor performance.IBM POWER8* systems enjoy the industry-uniquebenefits of high-density on-chip memory, through IBM’strench-based embedded dynamic random-access memory

(eDRAM) technology. From a transistor performancestandpoint, the POWER8 processor chip employsaggressively scaled high-� metal gate (HKMG) logictransistors in a gate-first architecture. Compared to agate-last alternative, the low capacitance of these transistorsdelivers high switching speed together with differentiatinglow-active power and high voltage-range capability. Inaddition, an optimized 15-layer metal stack with bothultra-low capacitance minimum-pitch levels and otherultra-low resistance levels is crucial in maximizingchip-level performance while managing switching powerat high frequencies.Central to the design of the technology was the choice

of gate-first instead of gate-last FET architectures. It wasimperative that the technology provide a significant systemperformance improvement with respect to the 32-nm nodewhile keeping cost competitive and both AC and DCpower consumption acceptable. As described in this paper,scaling of IBM’s 32-nm technology gate-first architecture,

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G. FREEMAN ET AL. 5 : 1IBM J. RES. & DEV. VOL. 59 NO. 1 PAPER 5 JANUARY/FEBRUARY 2015

0018-8646/15 B 2015 IBM

Digital Object Identifier: 10.1147/JRD.2014.2380252

combined with innovative transistor solutions likedual-embedded epitaxial films, led to industry-leadingpower-performance across a range of threshold-voltageand dielectric thickness offerings without having to relyon costly three-dimensional device solutions. Severalperformance aspects to this choice are not obvious.First, as mentioned earlier, the lower transistor-to-contactcapacitance provides benefits in power and performance [1].Second, operation at higher voltage, demanded byhigh-frequency processors, is enabled by excellent reliabilityat those desired voltages (in particular through smallerpFET bias-temperature instability) [2]. And third, acomprehensive channel length and threshold voltage menu,offering a range of devicesVfrom ultra-high speed transistorsto be used in delay-critical paths (at the expense of highleakage) to a suite of higher threshold voltages with lowerleakagesVallows tuning of performance while managingthe leakage power of the chip. As described in a later sectionof this paper, the fabrication of the broad device suiteofferings is more straightforward and fabricated withlarger process robustness. This enables a full-featuredsystem-on-chip (SoC) capability with confident yieldprojections and compact model projections, makingpossible a range of first-time-right analog functions tosupport both the processor and the memory buffer chip [3].This node has also continued IBM’s tradition of providing

distinguishing value in its silicon offerings in the form ofembedded memory. The 22-nm SOI node represents the thirdgeneration of SOI-based eDRAM that not only employsthe smallest bitcell in the industry (0.026 �m2), but alsocontinues to provide a chip-level performance boost via theuse of extremely high-density trench capacitors for noisedecoupling. The IBM product portfolio has capitalized onthese unique silicon solutions to integrate a variety offunctions such as L3 cache, on-chip decoupling, voltageregulators, and critical aspects of serial input-output designswithin the POWER8 family of chips.Early in the development process, the IBM team addressed

the dual challenge of increasingly complex technologyconstraints and increasingly demanding design requirementsby launching a formal design-technology co-optimization(DTCO) effort requiring close collaboration across the designand technology areas of the Systems and TechnologyGroup at IBM [4]. In later stages, continued collaborationbetween technology and design groups resulted in effectiveimprovement plans, responding to yield and parametriclimitations learned through the development activities. Suchplans included physical design modifications in responseto systematic process yield limiters or to device parametriclearning, as well as process modification in response toproduct application concerns. These early and continuousengagements were essential to repeatedly achievingBfirst-time-right[ design, with each chip verified withina few days of delivery after silicon fabrication.

Pattern transfer challenges and innovationsIn the 22-nm SOI technology, resolution requirementspush aggressively against the fundamental limits of availableoptical-lithography tooling. This shrinking gap betweenphysical limits and tool capability forces a well-consideredcompromise between performance requirements and thecostly multi-patterning solutions as part of technologydefinition.Historically, lithography resolution has improved as a

function of either decreases in the wavelength of light,�, or increases in the numerical aperture ðNAÞ of thelithographic exposure system. From the onset, it was clearthat industry activity to improve either � or NA could notintercept the 22-nm technology timeline, and thereforeinnovations in RETs (resolution enhancement techniques)would be required to reduce the process factor, k1, to enablea manufacturable patterning process for the 22-nm node,bearing in mind the following equation:

resolution ¼ k1�

NA(1)

The physical limit of diffraction-based optics dictatesthat k1 ¼ 0:25 is the lower limit for imaging a simpleone-dimensional line-space grating. Any smaller resolutionrequires the use of pitch splitting through double patterning(i.e., patterning alternating lines in separate steps) to achievethe desired scaling. The unique challenge faced by 22-nmtechnology development was to achieve the necessary scalingwith k1 G 0:3 for complex two-dimensional logic layouts.Operating on the cliff of this physical limitation requiredan extensive amount of co-optimization including devicelayout limitations and other restrictive design rules in order toavoid more costly double-patterning solutions [5].A key aspect of this design and process development

synergy in 22-nm technology has centered on the useof global source-mask optimization (SMO). Throughseveral technology nodes, RETs have been used to improvelithographic imaging performance and a lower k1. Themost beneficial RET improvements have involved changesto the mask or illumination source in order to increase theamount of diffracted image intensity that can be collected inthe lens and used to generate the aerial image at the resistplane. Such innovations as phase-shift masks and off-axisillumination had been used in prior technology nodes,but further improvements were required to supportthe 22-nm technology. The use of a computationallyintensive co-optimization process, like SMO, was a majoradvancement in improved lithographic process capability.In this co-optimization flow the most critical layouts,such as high density eDRAM or SRAM (static randomaccess memory) cells, are used as inputs. With theseinput layouts, a single complex source and maskcombination is determined to provide the best possibleperformanceVtypically minimizing the critical dimension

5 : 2 G. FREEMAN ET AL. IBM J. RES. & DEV. VOL. 59 NO. 1 PAPER 5 JANUARY/FEBRUARY 2015

(CD) variation in response to process variables such asexposure dose or focus [6]. Although SMO computationalmethods had been developed prior to the 22-nm node,their implementation had been restricted by the time andcost of learning cycles associated with the use of a staticdiffractive-optical element inserted into the lithographicexposure tool for achieving a complex pixelated illuminationsource. However, new advancements in the industry enabledthe capability of using a fully programmable microarrayof mirrors to produce a freeform illumination source for usein the 22-nm technology manufacturing environment [7].IBM has heavily leveraged this new capability to definecritical-level lithography processes and corresponding designrules that enable the use of single patterning processes.

Patterning challenges in pre-metal processesIn the 22-nm technology, deep trench lithographyperformance is significantly enhanced through the useof complex pixelated sources optimized around theaggressive (i.e., likely process-limiting) eDRAM anddecoupling-capacitor design layouts. Gate-level patterningfor the 22-nm node is similar to the 32-nm node in that itagain makes use of a secondary cut mask; additionalcapability is also provided through SMO-based optimizationaround SRAM and device-design constructs. Figure 1 showsthe illumination sources for deep trench and gate.Contact-to-gate and contact-to-source-drain patterningin the 22-nm node (illumination not shown in the figure)utilizes a litho-etch-litho-etch (LELE) patterning scheme.Relative to IBM’s 32-nm technology, only this layerhas migrated to a true pitch-split double-patterning process.Avoiding double patterning for all other critical layerswas a tremendous accomplishment relative to the scalingrequirements for the 22-nm node.

Patterning challenge in metal and via levelsThe challenges in metal-level patterning demanded thelargest shift in lithographic strategy relative to prior IBMtechnologies. The first metal layer, M1, uses dual-dipolelithography (DDL) and model-based decomposition

of the design level to support minimum pitch in both Xand Y orientations [8]. In this process flow, the designlevel is split through model-based decomposition withinoptical-proximity correction (OPC). This orientationdecomposition is split between two photomasks and isimaged sequentially in situ on the lithographic exposuretool, with opposite X- and Y-oriented dipoles (Figure 2).This method presents cost savings over pitch-split doublepatterning, as it requires only a single pass through thelithography and etch steps, as well as presenting no majorchanges to resist or other lithographic tooling systems.The success of the M1 DDL scheme was heavily dependentupon the model accuracy used for decomposition, especiallyin complex two-dimensional layouts. This complex DDLsolution for the M1 level is justifiable as a result of designdemand for bidirectional layout. The complexity is reduced(at the cost of design limitation) in subsequent Mx levels(where x ¼ 2, 3, 4, 5) that use a combination of SMO andpreferred orientation to overcome low k1 imaging challenges.In this scenario, M2 and M4 only allow the minimum pitch ina horizontal preferred orientation, and M3 and M5 have avertical preferred orientation (Figure 1).

Memory technologies and optimizationMicroprocessor main-clock frequency scaling has beenlimited due to power density constraints, while insteadmulticore designs with ever higher core counts and threadcounts have become the main source of chip performanceimprovement. Since the size of a chip is limited, as thenumber of cores increases, the area available to implementthe on-chip cache memory shrinks. If the amount of cacheavailable to each core becomes too small, the computeefficiency of the multicore system will suffer. Therefore, it isimportant to implement the majority of the cache using thehighest-density memory solution available. Modern CPUsutilize a hierarchy of multiple levels of cache memory(L1, L2, and L3). The lowest levels require high speedbut limited memory capacity, while the last level needsto provide maximum capacity at more modest speeds.Choosing the right balance of memory type and capacity

Figure 1

Complex illumination sources for 22-nm technology critical layers as derived from source mask optimization (SMO).


at each level is key to achieving a highly efficient cachehierarchy.In modern microprocessors, SRAM is typically the only

memory offering for implementing all levels of the on-chipcache. IBM’s POWER7* processor manufactured withthe 45-nm SOI technology marked the first time eDRAMwas adopted as on-chip cache memory in a state-of-the-arthigh-performance microprocessor. The 32-nm POWER7+*processor, and now the 22-nm POWER8 processor, haveextended this implementation using scaled SRAM andeDRAM in the cache solution.

SRAMSRAM, especially in smaller arrays, is faster than eDRAMand thus is most suitable for lower-level caches and cachedirectory applications. In the 22-nm SOI technology,three SRAM cells are used in the POWER8 processor [9].An eight-transistor dual-port 0.192 �m2 cell is used formost of the smaller arrays in the core and on-chipaccelerators, and in the core-support circuitry. A 0.160 �m2

performance-optimized six-transistor (6-T) cell is used inthe L1 data arrays and the L2 cache directory. A 0.144 �m2

density optimized 6-T cell is used in the L2 cache dataarrays and L3 cache directory.

eDRAMA 0.026 �m2 eDRAM cell is used in shared L3 cache dataarrays that consist of 768 1-Mb arrays. A high-� metal gatestack and high-� metal inner electrode deep-trench (DT)capacitor were both introduced in the 32-nm node, allowingscaling of both the access device and the storage capacitor,and delivering a better than historical 59% scaling factor

for that generation [10]. Additional innovative approacheswere needed in the 22-nm node to continue the eDRAMcell scaling.

Pre-doped substrate and deep trenchThe IBM deep-trench memory capacitor requires adeeply-etched trench hole, a heavily-doped outer electrodein the bulk wafer, a high-capacitance dielectric, and aconductive inner electrode that connects to the access device.Prior to the 45-nm SOI technology, the heavily dopedouter electrode was formed using arsenic diffusedfrom arsenic-silicate glass (ASG) film deposited on thedeep-trench surface. With the SOI substrate, the ASG dopingprocess was replaced with an ion-implanted plate processbecause the wet-etch strip of the ASG film would undercutthe buried oxide (BOX). The implanted-plate processwas adequate for the 45-nm and 32-nm technology nodesbut presented two problems to further scaling. First, withDT diameter scaling, the required implant dose would haveto be raised substantially to achieve the same plate dopinglevel, creating a processing throughput problem. Second,a protective film must be deposited on the sidewalls ofthe SOI and BOX after DT mask-open reactive-ion etching(RIE) to protect the SOI device region from the heavy N+doping. The presence of this blocking layer constricts thediameter of the top of the trench limiting the depth to which itcan be etched, reducing the surface area and therefore thecapacitance of the trench structure. A custom pre-dopedSOI substrate was developed to solve this problem. Anepitaxial layer of N+ doped silicon is sandwiched betweenthe BOX and bottom P-substrate. The thickness of thisepitaxial layer is such that the deep trenches are fully

Figure 2

Construction of first-metal level patterning using dual-dipole lithography (DDL) to enable minimum pitch in both orientations: (a) Metal (M1)orientation decomposition using DDL; (b) two-dimensional layout demonstration of M1 model-based decomposition.


contained within it (Figure 3). With this pre-doped substrate,no additional process steps for plate doping are needed.Doping levels in this epitaxial layer can be quite high,resulting in a four-fold improvement in buried-plate sheetresistance over the 32-nm technology node. Improved DTdecoupling-capacitor frequency response was predicted andverified [11]. The low-resistance epitaxial layer is continuousover the whole wafer. This epitaxial layer is biased to groundwith a substrate contact but there are circuit applicationswhere an off-ground bias is desirable. Therefore, a schemewhich can isolate regions of the N+ epitaxial layer was alsodeveloped. It is well known that a larger width trench willbe etched deeper during the RIE process. Based on thisphenomenon, a ring-trench feature (deep-trench Bmoat,[ orDTMOAT) was designed to enclose and isolate a regionin the N+ substrate for above-ground biasing. Requiringno additional process steps, this DTMOAT is formed at thesame time as the memory deep trenches and with its largerwidth, it slices through the N+ epitaxial layer and into theP-substrate, separating the enclosed N+ region from theoutside. This DTMOAT trench is filled with the samedielectric and inner electrode as the memory trench andcreates a U-shaped MOSFET: trench node dielectric is thegate dielectric, TiN metal and DT poly-silicon inside thetrench are the gate, the epitaxial layer enclosed in theDTMOAT rectangle is the drain, and the extended N+epitaxial layer outside of DTMOAT ring is the source. Tyinggate and source of this structure both to ground keeps theMOSFET off and provides the desired isolation (Figure 3).Room temperature leakage current less than 1 pA=�m at

1.3 V Bdrain[ bias is accomplished. This feature allowsimplementation of trench-capacitor blocks where both endsof the capacitor can be biased independently and is alsoused to create noise-isolated regions for analog circuitapplications.A HfO2 trench node dielectric was used in the 32-nm node.

In order to meet the scaling requirement in the 22-nm node,a higher-� film is employed in the deep-trench capacitorto achieve a 10% capacitance gain per unit area withbetter reliability. With scaled deep-trench diameter andconsequently shallower trench depth, the 12 femto-faradper trench capacitance requirement for the 22-nm nodeeDRAM applications is successfully met.

eDRAM access deviceDue to reliability and process commonality considerations,the 22-nm technology eDRAM access device maintainedthe same electrical gate dielectric thickness as in the 32-nmtechnology node. Active-area (i.e., patterned SOI) pitchand particularly active-area space and contacted-gate-pitchscaling offered a path to cell scaling despite the needto maintain the electrical gate length and width forshort-channel control and minimization of threshold variationdue to random-dopant fluctuation (RDF) [12]. In situ-dopedepitaxial Si:C (eSiC) stressor diffusions are used as aperformance-enhancement feature for all nFET devices inthe 22 nm technology. eSiC is also incorporated into theeDRAM array, where it provides superior short-channelbehavior and enables strong Bbutting[ of the N+ junctionto the bottom of the SOI (Figure 3). The 22-nm technology

Figure 3

Pre-doped SOI substrate-enabled 22-nm technology eDRAM cell scaling and provided superior bottom-plate conductivity relative to the 45-nm and32-nm nodes. An electrically isolated region in the substrate with very low leakage can be created with a ring DTMOAT design. DT decoupling capacitors,for example, can be implemented in the isolated region and both the top and the bottom plates of the capacitors can be independently biased. TheeDRAM cell image (at the right) shows the additional cell features including the access FET and the eSiC embedded layer on one side.


continues the historical �60% cell-area scaling over theprior generation. Circuit design efficiency further increasesthe density of the eDRAM functional memory blocks,which achieves twice the bits per area compared to theprevious 32-nm technology node offering.

Decoupling capacitorIn addition to memory use, deep-trench capacitors areused as highly-efficient on-chip power-supply decouplingcapacitors. Three-dimensional trench capacitors providemuch more capacitance per area than conventional planarmetal-oxide-semiconductor (MOS) capacitors or evenspecialized metal-insulator-metal (MIM) capacitorsembedded within the metal wiring levels of the chip.Since deep-trench capacitors are located beneath the wiringlevels, they can be flexibly placed and connected withoutrestricting the logic wiring passing above them. Havinga large reservoir of decoupling capacitance on the powersupplies reduces power-supply voltage fluctuations,benefiting both performance and power of the chip. In the22-nm technology, deep-trench decoupling capacitors areoffered at a density of 470 fF=�m2, and are integratedwithout additional processing since they are created withthe same process steps as the eDRAM memory. POWER8implements a total of 31.5 �F of DT decoupling capacitance,or about 2.7 billion deep trenches. These decouplingtrenches are so critical to system performance that onthe POWER8 processor they outnumber deep-trenchmemory capacitors by nearly three to one. Lower activeand standby power of the eDRAM cache compared to anSRAM cache solution, higher cache efficiency from thevery dense eDRAM memory, and power-supply noisereduction due to the large amount of on-chip powerdecoupling provided by trench capacitors all contributeto a power and performance uplift roughly equivalent to

implementing a given microprocessor in the next technologygeneration [9].

Technology innovations for logicdevice performanceLogic performance in this technology is built on a secondgeneration of IBM’s gate-first HKMG transistor architecture[13]. By leveraging the 32-nm technology HKMG learningin compact-model projections and process-yield learning,significant time-to-market benefits were realized. In addition,multiple new process elements and optimizations ofexisting elements were developed to drive higher deviceperformance. Continued optimization of the gate-firstprocess enables gate length ðLgateÞ scaling via aggressivereduction of effective gate dielectric thickness ðTinvÞ,while simultaneously minimizing gate-coupled parasiticcapacitance. To enhance carrier mobilities, advancedstressors are incorporated via a new, dual-embeddedsource-drain integration. The resulting AC performanceof this technology underpins the server-class leading clockrates demonstrated by the POWER8 microprocessor.Among the benefits of a gate-first HKMG flow is the

process flexibility allowed within the gate module. Incomparison to the replacement-gate integration schemeused in other technologies [14] where the critical gatefilms are deposited after the source-drain definition, thegate-first HKMG flow deposits the gate films early in theprocess. Since the substrate remains planar during gate-stackprocessing (without critical gate dimensions or junctionsdefined) there are minimal constraints on thermal budgetand wet processing [Figure 4(a)]. Here this flexibilitywas leveraged for multi-step optimization of surface cleans,silicon-to-dielectric interfacial-layer (IL) formation, andpost-dielectric anneals. Both the IL and the high-� dielectricare aggressively scaled as a result, with minimal mobility

Figure 4

Front-end process overview. (a) General process flow showing gate before source-drain process steps. (b) TEM image of pFET source-drain in situ-doped epitaxy, showing undoped buffer, graded main layer, and low Ge% cap. (c) TEM image of nFET source-drain in situ-doped epitaxy.


degradation in both nFETs and pFETs. The Tinv achievedfor nFET and pFET logic devices, is 1.04 nm and 1.2 nm,respectively. These values are 7% and 10% thinner thanthe 32-nm technology, and the thinnest reported formanufactured high-performance CMOS technologies [1].Short-channel effect (SCE) improvements are demonstratedwith drain-induced barrier lowering (DIBL) improving upto 8%. Combined with downstream SCE optimizations,the overall gate scaling returns to classical trends withLgate scaling commensurate with Tinv scaling. Physicallogic Lgate is scaled by up to 5 nm relative to the 32 nmtechnology. Reliability at these scaled Tinv values ismaintained, with time-dependent dielectric breakdown(TDDB) and bias-temperature instability (BTI) thresholdvoltage shift both meeting server-class requirements. Theserequirements include both standard technology lifetimespecifications as well as supporting in excess of 1.25 Vmaximum FET operating voltages at 85 �C.In addition to gate length, gate height was also scaled

to minimize gate-coupled parasitic capacitances. Whencombined with the comparatively low intrinsic parasiticcapacitance offered by a planar, gate-first SOI devicearchitecture, simulation results show over a 20% reductionin total parasitic capacitance compared to gate-last finFETdesigns at matched density [1]. The dual impact oflower capacitance, increasing AC frequency as well asdecreasing AC power at fixed frequency, result in substantialpower-performance benefit achieved as both gate lengthand height are scaled.Another core gate-first HKMG component (employed

on all pFET devices on the chip) is the thin channel-regionepitaxial silicon-germanium (cSiGe) film deposited on topof the silicon transistor body. The primary motivation forcSiGe is the valence band offset that allows for effectiveHKMG work function tailoring supporting the wide rangeof threshold voltages required of a high-performancesystem-on-chip. However multiple other benefits havebeen demonstrated including high hole mobility and strainresponse [15], low negative-bias temperature instability(NBTI) characteristics [16], and hole carrier confinement[17]. In optimizing a second generation of cSiGe, a focuswas placed on the tradeoffs between carrier confinementcharacteristics and effective work-function requirements.Close interaction with product design resulted in refinedthreshold voltage specifications and well-implantdesign modifications that enabled a scaling of cSiGethickness. The resulting improvement in confinement andhence SCE enables both gate-length scaling as well ashigher Ieff at constrained leakage [Ieff being a transistordrive-current metric, defined as the average of thedrain-source currents at different drain-source andgate-source voltages IDSðVDS ¼ VDD;VGS ¼ VDD=2Þ andIDSðVDS ¼ VDD=2;VGS ¼ VDDÞ]. Reduced cSiGe thicknessalso mitigates challenges in optimizing boron-doped

junctions. The diffusivity differences of boron in silicon andsilicon-germanium present a challenge when engineeringan abrupt and low-resistance junction overlapping channeland source-drain. By reducing the thickness of the cSiGethe impact of boron diffusivity in silicon is reduced, andthe junction can be engineered to improve the spreadingresistance of the boron extension at fixed SCE. Together,this resistance improvement and the SCE enhancementsresulted in a net Ieff improvement of 10% attributed tocSiGe optimization [18].In order to enhance carrier mobilities, a dual-embedded

source-drain integration was developed incorporatingin situ-doped source-drain stressors for both nFETs andpFETs. In pFETs embedded silicon-germanium source-drain(eSiGe) has been leveraged for inducing channel strain formultiple generations [19]. To better address several inherentdevice and process tradeoffs, a new multilayered eSiGeprocess was engineered. Close proximity between stressorand gate is optimal for maximizing channel strain. Highlevels of dopant in the source-drain are also desired, bothto minimize spreading resistance between source-drainand gate-overlap region, and to minimize silicide contactresistance. However, when combined in an in situ-dopedsource-drain, the close proximity of high dopantconcentrations can have a negative impact on SCE. Themulti-layered process implemented in this technologyfirst nucleates a conformal undoped buffer layer, whichis then followed by epitaxy with a graded dopantprofile [Figure 4(b)]. Both doping and structuralprofiles required optimization in order to tailor the finalpost-thermal-processing dopant profile. The resultingdopant profile isolates the highest concentration of dopantsnear the cSiGe channel region, delivering resistancebenefits while minimizing undesired out-diffusion awayfrom the channel. Taken with the cSiGe optimizationsdescribed previously, the resulting devices exhibit over15% linear-mode resistance reduction compared to the32-nm technology, while also exhibiting reduced DIBLand sub-threshold slope.A similar tradeoff is presented by the desire to increase

channel strain via higher germanium concentration (%Ge)in the eSiGe source-drain epitaxy. High %Ge fraction canprovide unique challenges post epitaxy due to differing etchrates and silicidation behavior between the silicon (nFET)and silicon germanium (pFET) source-drains. In order tofacilitate high %Ge, the multi-layered approach was extendedto a capping layer, reducing %Ge toward the top surface ofthe epitaxy. The resulting process increases peak %Ge overthe 32-nm technology, with effective strain and measuredmobility increased by over 40% and 15%, respectively [1].nFETs in this technology also incorporate an

embedded-epitaxial stressor in the form of silicon-carbon(eSiC) [Figure 4(c)]. While previous work has shownpotential for eSiC to generate significant channel strain,


the low solid solubility of carbon in silicon has remaineda challenge for preserving high carbon incorporationpost-epitaxy [20, 21]. The dual-embedded source-drainintegration practiced here is engineered to minimize thermalprocessing post eSiC formation. By doping the nFETsource-drain in situ, a gate-first process can eliminateboth implantation anneals and gate-stack dielectric annealspost eSiC formation. Eliminating these anneals alsominimizes dopant out-diffusion from the nFET source-drain,preserving ideal SCE behavior at close proximity to the gate.The substitutional carbon concentration in this processis measured at �1.5% with minimal loss in strainpost-processing, generating an additional �340 MPa oftensile channel stress in the logic device. This representsan 80% stress increase with electron mobility improvementof �20% [1]. These logic performance benefits areobtained while simultaneously meeting the additionalrequirements of the scaled eDRAM access device,including extremely low (i.e., picoamp level) junctionleakages and strong body-to-body isolation.At an offstate leakage of 100 nA=�m, nFETs and pFETs

in this technology demonstrate saturation currents up to1.75 mA=�m and 1.48 mA=�m at 1.0 V and 25 C,respectively (Figure 5). When combined with SCEimprovements, this translates to an improvement in Ieffof over 15% and 30% compared with 32-nm SOI technology[13], for nFETs and pFETs. Gate capacitance is reducedvia Lgate and width scaling, and parasitic capacitanceis reduced via gate-height scaling, resulting in an overallcapacitance per circuit reduction averaging �10%. Theresulting AC performance improvement is demonstratedby standard-cell fan-out-of-three ring oscillators withstage delays below 7 ps, at leakages of 50 nA=�m(0.9 V 25 �C). To facilitate high-performance server designs,these logic devices are offered across a wide range of

threshold voltages, spanning a 0.9 V leakage range of 1 to300 nA=�m.

Extended device suite for system-on-chipEnabling a broad range of functionality on-chip is alsocritical to achieving high-performance processors. Thismeans the technology offering must incorporate, in additionto logic and memory, a breadth of device offerings as wellas accurate compact modeling to ensure first-time success.For example, resonant clocking [9] is achieved withinductors designed hand-in-hand with circuit andcompact-modeling engineers. Also, voltage regulatorsare enabled with thick-oxide higher-voltage FET offerings.High-frequency PCIe** (PCI Express**) serial-bit circuitsare implemented with a critical 40-nm channel-lengthfloating-body thin-oxide FET offering, with substantialquantities of deep-trench capacitor for both decoupling andto facilitate the hold-voltage requirements of the standard.Analog phase-locked loops and temperature sensorsleverage the low substrate-noise capability provided bythe low-resistance substrate and DTMOAT isolation,and on-chip resistive fuses provide capability for storingredundancy information as well as on-chip electronicchip-identification.Thus, the device menu made available on-chip within the

22-nm technology includes multiple discrete channel lengths(variable widths) in thin-oxide (1.04 nm Tinv) as well asthick-oxide (2.25 nm Tinv) nFET and pFET, a 350 �/squareprecision resistor with þ=�10% range, an ideal diode, athin-oxide variable capacitor, a thick-oxide accumulationcapacitor, an ultrahigh-capacitance-density deep-trenchcapacitor (previously described), and several electrostaticdischarge protection devices.Compared with the 32-nm technology with a three

dielectric solution [22], the 22-nm technology design hassimplified to two dielectrics with the same dielectric sharedbetween the access FET of the eDRAM and the analogthick-oxide FET. This presented unique challenges todeliver both the performance required by the eDRAM andhigh-performance analog FETs (favoring a substantiallythin dielectric), and the low leakage of the eDRAM and thehigh-voltage reliability requirements of I/O devices (favoringa thick dielectric). By engineering the devices with carefulwell engineering and atomic layer deposition (ALD) oxidewith post-deposition anneal, we provide high performance,control, and excellent reliability.As noted earlier, the gate-first choice provides integration

simplicity advantage to delivering this required breadthof device offerings. One example is the long-channel FETintegration, where in the alternative gate-last integration,the chemical-mechanical polishing and planarizationprocesses are challenged by longer Lgate offerings. Thisresults either in process constraints and complexity or inreduced technology device offerings. In addition, due to the

Figure 5

DC saturation versus off-state ðIon=Ioff Þ currents at 1.0 V and 25 �C fornFET (red circles) and pFET (blue circles).


complexity of the gate-last gate film deposition structure ina three-dimensional trench (i.e., the replacement steps), thegate workfunction as a function of length has additionaldependencies that can be less predictable compared withthe gate-first planar structure, and thus challenged to provideaccurate long-channel compact-model projections. Thethick-oxide dielectric film integration is also morecomplicated. Compared with gate-first integration wherethe removal of the thick-oxide dielectric film before thethin-IL growth impacts a simple and robust planarisolation film, in the gate-last integration the removalof this dielectric unevenly etches a more complex set of films.The necessary planarity compensation or mitigation againeither requires additional process complexity or limits therange of dielectric properties supported. By making an earlyadoption of a gate-first architecture, our fast technologylearning and performance coupled with accurate compactmodel and design rule projections supported the criticaltime-to-market criteria for the POWER8 processors.

Wiring implementation to meet performanceand reliabilityIn order to meet the wiring and performance requirements ofthe processor designs, the technology provides 15 copperwiring levels along with a far-back-end-of-line (BEOL,or metal levels) mixed copper via and aluminum padpassivation as shown in Figure 6. The stack comprisesfive 80-nm pitch metal wiring layers (1X level), two layersat 144-nm pitch (2X level) in ultralow-� (ULK, � ¼ 2:5),three layers at 288-nm pitch (4X level) in low-� ð� ¼ 2:7Þ,three layers at 640-nm pitch (8X level) in low-� ð� ¼ 3:0Þ,and 2 layers at 2,400-nm pitch (30X level). The M1 wiringis a single-damascene copper in low-� dielectric ð� ¼ 2:7Þ,allowing bidirectional 80-nm pitch, achieved lithographicallywith dual-dipole lithography using two M1 masks asdescribed earlier. The M2 to M5 wiring levels are

dual-damascene copper in ultra-low-� (ULK, � ¼ 2:5)that allow preferred-orientation 80-nm pitch (nonpreferredorientation is allowed at 160-nm pitch).Major changes for via patterning took place in the 22-nm

node with the introduction of a trench first metal hard maskintegration scheme to enable self-aligned via (SAV)patterning. With scaling, the traditional via-first trench-last(VFTL) integration scheme has become challenged torobustly meet reliability and yield. The self-aligned processaddresses this challenge by controlling the spacing betweenthe via top and the neighboring metal line using themetal-line pattern transfer in a metal hardmask, improvingTDDB performance. Figure 7 shows how the SAV processuses a larger via lithography pattern by relying on via etch

Figure 6

BEOL. Left: The BEOL levels by pitch and interlayer dielectric (ILD) material. Right: the full POWER8 BEOL 15-level metal stack with Al padpassivation (at very top of image).

Figure 7

Self-aligned via (SAV). (a) Cartoon showing the self-aligned Vx (orange)and Mx metal above (blue) through design, process lithographypatterning target in resist, and post-etch bottom size relative to metalabove. The rightmost SEM image shows the real post-etch via bottom(the oval in SEM center is the via opening to copper metal below).(b) TEM cross sections in the self-aligned via direction [i.e., horizontaldirection on the post-etch image on the left] and the non-SAV direction[i.e., vertical direction on the post-etch image on the right].


selectivity to the metal line. In this method, the metalpattern is first transferred into a hardmask layer. Due toreactive-ion etch (RIE) selectivity of the hardmask films,only the union between via lithography shapes and theopening in the underlying hardmask from the priortrench-pattern transfer step will define the final criticaldimension of the via. Both via and trench patterns canthen be etched into the dielectric film to generate the finaldual damascene structure. As a result of using SAV, vialithography resolution and CD control requirements arerelaxed, placing a majority of the burden on metal linepatterning variability control.To achieve server-class reliability requirements, extensive

use of CuMn alloy metallization is implemented to reducecopper electromigration (EM) at 1X and 2X levels [23].The use of CuMn increases EM lifetime more than fourfoldcompared with pure Cu metallization, with only �10%higher line resistance. The challenging 1X level TDDBrequirements were robustly achieved with self-aligned viaintegration. The self-aligned via process transfers the vialithography pattern through etch with minimal change inVx to Mxþ 1 spacing, improving via-to-metal TDDB.This structural improvement leads directly to enhancedvia-to-metal TDDB, which has been a critical challengewith prior via-first trench-last integration.The BEOL definition included many elements to improve

the manufacturability of the technology to enable fasteryield ramp. The BEOL metal-fill designs (the noncircuitpatterns placed to improve pattern uniformity for the process)were expanded to include smaller and more product-likefeatures to further improve metal-density uniformity. Thisdensity improvement enables better within-chip resistanceuniformity, and increases lithography process windowfor subsequent patterning levels.Extensive use of design retargeting (dimension

modification after design) was included on the 1X levels.This enabled a more simplified design space and allowedprocess learning to be captured with minimal layout tuning,thus reducing design iterations. This retargeting infrastructureallowed the implementation of design-for-manufacturingsolutions for longer line-end extensions past vias, andincreasing via sizes where there were no reliabilityconstraints (e.g., fully landing larger vias on metal below).

Meeting product schedule with rapidyield learningThe road to robust POWER8 manufacturing yields beganin the initial phase of technology definition and continuedthroughout the technology development phases. Specialattention was given to identifying and eliminatingtechnology-specific systematic yield limiters ahead ofproduct-design tape-outs. Throughout, close collaborationwith the POWER8 design teams proved critical to theprogram’s success, enabling both optimized design

constructs, and definition of design-representative testvehicles for studying complex yield challenges.As an example, from its initial stages, 22-nm SOI

technology development heavily leveraged our DTCOprocess [4], evaluating design-style choices in the contextof restrictive patterning solutions and technology processelements. DTCO represents a departure from previoustechnology definition methodologies that relied primarilyon shrinks of existing rules and designs as the technologystarting point. Rather than designing only from a setof rules, the teams refined a set of high-value circuits,co-optimizing such designs with the patterning andintegration capabilities available. The close collaborationcontinued into the early technology development phaseas the teams found and improved upon problem constructs.The end result was shorter cycles of design learning,improved manufacturability, and a more robustdesign that meets the power and performance goalsof the technology.Further, in comparison to prior technology development

efforts, a significantly greater investment was made intest structures (and accompanying testing and analysisinfrastructure) for both simple structural-integrity-evaluationstructures as well as more complex functional designs.The simple (yet extensive) first-metal level (M1) testablestructures were systematically designed to modulate physicallayouts in ways which mimicked (or even enhanced) thebreadth of possible design constructs and process variation.The functional structures, testable at seventh-metal level(M7), were built in collaboration with design groups toevaluate the yield-ability of routed logic and routingsolutions using the same Blarge block structured synthesis[(LBSS) tools employed by the design groups [9, 24].The 22-nm technology development team then employedthese M7-testable structures not only to identify criticalfunctional-relevant failure mechanisms, but also tocorrelate against and identify the most critical signatureson the M1-testable designs. This defined an earlier detectionpoint and thus enhanced cycles of yield learning.Other techniques were employed for the first time.

For instance, to assist understanding of complex processinteractions, virtual-fabrication process emulation wasemployed [25]. We also made use of innovative detectioncapability such as high-resolution electron-beam hotspotinspection on complex two-dimensional constructs atthe 1X metal levels [26].These innovations enabled rapid learning about problem

constructs early in the technology development phase.Combined with rapid hardware movement and aggressivereduction of random-defect failure-modes, the resultis a sustained two-fold rate of process change andaccelerated defect learning over previous technologynodes, providing robust technology yields ramping intovolume manufacturing.


ConclusionIn this paper, we have described IBM’s 22-nm SOItechnology in which POWER8 microprocessors arefabricated. Dense eDRAM, innovative and optimized devicearchitecture, and a yield-optimized and RC-optimized metalstack involving cutting-edge patterning techniques are its keydistinguishing features. The resulting technology offeringdelivers industry-unique capability, providing criticaltechnical advantage to the POWER8 processor. Designs alsoleverage the comprehensive set of Bsystem-on-chip[ deviceofferings including thick-oxide FETs and passive devices.Close collaboration with design groups along with enhancedyield improvement methodologies have been critical inachieving first-time-right silicon and a successful yield ramp.

AcknowledgmentsWe acknowledge the enormous efforts made in developingthis technology, including the organizations involved withthe patterning, unit process, characterization, enablement,manufacturing, integration, and device design, as well astheir dedication over years of effort and problem solving thathave made the technology and the POWER8 functionalitya reality. We especially appreciate the early contributionsand leadership of David Fried. Thanks also to Ed Nowak,Wilfried Haensch, and the Editor-in-Chief Cliff Pickoverfor the review of the manuscript, and Phil Flaitz on theimaging shown in Figure 6.

*Trademark, service mark, or registered trademark of InternationalBusiness Machines Corporation in the United States, other countries,or both.

**Trademark, service mark, or registered trademark of PCI-SIG in theUnited States, other countries, or both.

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Received May 2, 2014; accepted for publication May 31, 2014

Greg Freeman IBM Microelectronics, Hopewell Junction,NY 12533 USA ([email protected]). Dr. Freeman is an IBM seniortechnical staff member and manager of the 22-nm SOI device designdepartment. He received his Ph.D. degree from Stanford University in1991 and has been with IBM at the East Fishkill, New York, facilitysince then with various involvement in characterization, SiGe bipolardevice design, and starting with 65-nm SOI technology, CMOStechnology development. Dr. Freeman is a senior member of theIEEE and has authored or coauthored over 60 publications. He holdsapproximately 26 patents.

Paul Chang IBM Microelectronics, Hopewell Junction,NY 12533 USA ([email protected]). Dr. Chang is a Senior Engineerin the 22-nm SOI device design department. He received B.S., M.S.,and Ph.D. degrees in electrical engineering from the University ofCalifornia-Berkeley in 2000, 2004, and 2005, respectively. Hesubsequently joined IBM Microelectronics and has worked in 22-nmdevice design since 2008. He is a coauthor on over 20 technical papersand 20 U.S. patents.

Edward (Ward) R. Engbrecht IBM Microelectronics,Hopewell Junction, NY 12533 USA ([email protected]).Dr. Engbrecht is a Senior Engineer in the BEOL Process Integrationgroup at the Semiconductor Research and Development Center(SRDC). He received a B.S. degree in chemical engineering fromthe University of Illinois at Urbana-Champaign in 1995 and aPh.D. degree in the same from The University of Texas in 2004.He subsequently joined TI and in 2007 joined IBM, where he hasworked on BEOL integration for the 45-nm and 22-nm technologies.He is author or coauthor of 3 patents and 18 technical papers.

Kenneth J. Giewont IBM Microelectronics, Hopewell Junction,NY 12533 USA ([email protected]). Mr. Giewont is a SeniorTechnical Staff Member and engineering manager in the SemiconductorManufacturing Solutions organization supporting the 300-mmfabricator in East Fishkill, New York. He received a B.S. degree inengineering science from Pennsylvania State University in 1985 and an


M.S. degree in electrical engineering from Syracuse Universityin 1992. Mr. Giewont joined IBM in 1985 and has worked inseveral engineering roles for semiconductor technology qualificationsand manufacturing yield ramp, which include physical failure analysis,in-line electrical characterization, and FEOL (front-end-of-line)process integration. Since 2002, Mr. Giewont has held engineeringmanager roles in manufacturing spanning FEOL process integration,ASIC (application-specific integrated circuit) product qualification,and most recently 22-nm SOI technology and product introduction.Mr. Giewont is author or coauthor on 13 patents and hasreceived 2 IBM Corporate Awards.

David F. Hilscher IBM Microelectronics, Hopewell Junction,New York 12533 USA. Mr. Hilscher is the lead surface preparationengineer within the IBM 300-mm development area, with over18 years of experience gained working for MiCRUS, Philips,and now IBM. He received his B.S. degree in chemical engineeringand chemistry from Carnegie-Mellon in 1989. Mr. Hilschermanaged the IBM wet-process manufacturing engineering teamfrom 2007 to 2010, during which time his department installedthe first 200 �C sulfuric-peroxide single-wafer production tool,qualified the use of electrolyzed sulfuric acid to extend bath life, andled an extended development and manufacturing team to reduce overallsulfuric acid usage by 70%; IBM East Fishkill received an MVP2(Most Valuable Pollution Protection) Award from the NationalPollution Prevention Roundtable in 2010 based on that work.Since joining the 300-mm development area in 2010, Mr. Hilscherhas worked with 32-nm and smaller generation technologyteams to proliferate the use of single-wafer cleaning to improveyields.

Mark Lagus IBM Microelectronics, Hopewell Junction,NY 12533 USA ([email protected]). Dr. Lagus is currentlyleading the 22-nm SOI yield ramp into manufacturing. He receivedB.A. degrees in mathematics and physics from St. Olaf Collegein 1989 and his Ph.D. degree in Physics from The University ofWisconsin-Madison in 1995. He has been with IBM at the East Fishkill,New York, facility since 1996 where he has held a wide range ofengineering and management roles from process engineering tocharacterization and yield learning. Immediately preceding hiscurrent role, Dr. Lagus led the detection and elimination of systematicfailure modes in the 22-nm SOI technology development phase.Dr. Lagus has authored or coauthored several papers, and his nameappears on five U.S. patents.

Timothy J. McArdle IBM Microelectronics, Hopewell Junction,NY 12533 USA ([email protected]). Dr. McArdle joined theepitaxy unit process group at IBM’s Semiconductor Research andDevelopment Center (SRDC) in 2011, after working as a postdoctoralscientist at the IBM Thomas J. Watson Research Center since 2009.He received a B.S. degree in engineering physics as well as M.S.and Ph.D. degrees in physics from the University of Illinois atUrbana-Champaign in 2003, 2004, and 2009, respectively. At theSRDC, he has focused on developing channel and embeddedSiGe processes for IBM’s 22-nm SOI program and receivedconsecutive Eminence and Excellence Awards for that workin 2012 and 2013. Dr. McArdle is a member of the AmericanPhysical Society (APS) and is author or coauthor of 5 patentsand 10 technical papers.

Bradley Morgenfeld IBM Microelectronics, Hopewell Junction,NY 12533 USA ([email protected]). Mr. Morgenfeld joinedIBM in 2006 after earning a B.S. degree in chemical engineering fromCornell University. He has worked as a process engineer for 45-nm,32-nm, and 22-nm nodes to develop patterning solutions for deeptrench, contact, and BEOL levels. He holds a patent and has authoredor coauthored 10 publications. Mr. Morgenfeld has most recentlyserved as the patterning technical lead for BEOL for 22-nm technologydevelopment to support IBM POWER8 processors.

Shreesh Narasimha IBM Microelectronics, Hopewell Junction,NY 12533 USA ([email protected]). Dr. Narasimha received hisPh.D. degree (in 1999) in electrical engineering from the GeorgiaInstitute of Technology. He is currently a Distinguished Engineer inthe IBM Semiconductor Research and Development Center (SRDC)within the Systems and Technology Group business unit. Overthe course of his career, his focus has been on the developmentof SOI CMOS technologies for use in IBM’s high-performanceserver, custom logic, and ASICs applications, as well as third-partyofferings. He holds over 50 U.S. patents in the area of semiconductorinnovation.

James P. Norum IBM Microelectronics, Hopewell Junction,NY 12533 USA ([email protected]). Mr. Norum is a Senior Engineerand manager of the 22-nm Semiconductor Process Integrationdepartment in East Fishkill, New York. He received a B.S. degreein electrical engineering from Yale University in 1987 and anM.E. degree in electrical engineering from Cornell University in 1989.Mr. Norum joined IBM in 1987 and has worked in a variety of rolesincluding self-aligned bipolar technology, reactive ion etch processdevelopment, manufacturing engineering, and equipment engineering.He entered technology development in 2000 and has been involvedin four generations of bulk embedded DRAM technologies, for whichhe received an IBM Corporate Award, as well as two generations ofhigh-performance SOI CMOS/eDRAM technologies. He is a memberof the IEEE and has coauthored eight U.S. patents and seven technicalpublications.

Karen A. Nummy IBM Microelectronics, Hopewell Junction,NY 12533 USA ([email protected]). Ms. Nummy is a SeniorTechnical Staff Member at IBM in East Fishkill, New York. Shereceived B.S. and M.S. degrees in material science and engineeringfrom MIT (Massachusetts Institute of Technology) in 1980 and 1981,respectively. Ms. Nummy joined IBM in 1981 and has worked in manyaspects of front-end process development. Most recently she led the45-nm eDRAM process development for which she won an IBMCorporate Award, and is currently the lead front-end integrator for the22-nm SOI technology. Ms. Nummy is an author of 15 papers andholds 16 U.S. patents.

Paul Parries IBM Microelectronics, Hopewell Junction, NY 12533USA ([email protected]). Dr. Parries is a Senior Technical StaffMember working in embedded DRAM technology and productdevelopment in East Fishkill, New York. He has had over 25 yearsof experience working on commodity DRAM and embedded DRAMtechnologies and has expertise in process development, DRAMprocess integration, and circuit design and characterization. Dr. Parriesreceived his B.S. and Ph.D. degrees in electrical engineering fromthe University of Minnesota and joined IBM in Burlington, Vermont,in 1985. He has been involved in developing DRAM and eDRAMtechnology beginning with IBM’s first trench 0.8 �m 4 Mb technologyto the latest embedded eDRAM nodes. Dr. Parries has receivedIBM Corporate Awards for his work in embedded DRAMdevelopment and for his contributions to IBM’s patent portfolio.Dr. Parries holds over 45 patents and has coauthored numeroustechnical papers.

Geng Wang IBM Microelectronics, Hopewell Junction, NY 12533USA ([email protected]). Dr. Wang received his B.S. degree inphysics from Peking University, China, in 1995, and M.S. and Ph.D.degrees in electrical engineering from the University of Texas at Austin,in 1997 and 2001, respectively. He is currently a senior engineer andhas been with IBM’s Microelectronics Division since 2001. As aTCAD (Technology Computer Aided Design) engineer, he workedon the 110-nm and 90-nm vertical access transistor DRAM cell andstudied the scalability of planar access device for DRAM cells. In 2003,he worked on the access device design of IBM’s first generation ofhigh-performance eDRAM, which eventually led to the successfulintegration of eDRAM on the POWER7 multicore processor. The


access device design principles he developed continue to guideeDRAM cell scaling.

Jonathan K. Winslow IBM Microelectronics, HopewellJunction, NY 12533 USA ([email protected]). Mr. Winslowis an engineer in the Manufacturing Integration Group supporting theIBM 300-mm Fab. He received B.S. and M.E. degrees in electricalengineering from Cornell University in 2000 and 2001, respectively.He subsequently joined IBM where he worked on Product Diagnostics.He also worked on product power performance optimization on thedevice integration team and is currently the lead manufacturingintegrator for the 22-nm SOI technology. He is author or coauthorof three patents and five technical papers.

Paul Agnello IBM Microelectronics, Hopewell Junction,NY 12533 USA ([email protected]). Dr. Agnello is a DistinguishedEngineer and Functional Manager at IBM’s Semiconductor Researchand Development Center at Hopewell Junction, New York, responsiblefor 14-nm SOI technology development. He received his B.S., M.S.,and Ph.D. degrees, all from the Electrical, Computer and SystemsEngineering Department of Rensselaer Polytechnic Institute and joinedthe IBM Thomas J. Watson Research Center in 1988 and the IBMMicroelectronics Division in 1992. Over his career at IBM, hehas worked on developing and bringing to manufacturing over11 generations of high-performance microprocessor technology.He has authored or coauthored more than 60 publications and holdsmore than 15 U.S. patents.

Rajeev Malik IBM Microelectronics, Hopewell Junction,NY 12533 USA ([email protected]). Dr. Malik received hisB.Tech. degree at the Indian Institute of Technology, Bombay, andhis M.S. and Ph.D. degrees at the University of Michigan, Ann Arbor.He is currently the Project Manager for the 22-nm SOI Technologyteam in the Advanced Microelectronics Solutions Group withresponsibility for completing the development and transfer tomanufacturing of this node. Since joining IBM in 2003, Dr. Malikhas held several engineering and management positions in themicroelectronics organization. His work has resulted in the inventionand productization of the first dual-stress-liner technology, for whichhe received an IBM Corporate Award. He holds more than 25 patentsand has authored or coauthored more than 30 publications.


performance-optimized gate-first 22-nm soi technology with embedded dram

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