Performance of

70nm Strained-Silicon CMOS DevicesJ.R. Hwang, J.H. Ho, W.T. Shiau, et.al,

Advanced Device Development,Central Research and Development Division,

United Microelectronics Corporation

+AmberWave Systems, *Strategic Technology, AMD

Outline• Introduction• Mobility and drive current performance• Id-sat and Id-lin enhancement• Self-heating & temperature effect• Gate oxide & junction leakage• Unit channel resistance vs. lateral-field• Ring oscillator power delay• Summary

Introduction• Strained-Si improves mobility by the tensile stress induced energy

band split and reduced electron scattering rate.

• Band split also causes a narrow bandgap and Vt shift.

• Vt shift was compensated to obtain fair comparisons of mobility, drive current, and speed.

• Junction leakage due to both defects and Si0.2Ge0.8 virtual substrate are investigated.

• Both vertical and lateral field dependency of mobility on gate and drain biases are explored by detail comparison of Id-lin and Id-sat gain.

Strained Silicon Device Structure

Strained-Si ChannelRelaxed Si 0.8 Ge 0.2

Poly Gate

• Optimized strained-Si structure on standard 0.13um foundry process with a heavily nitrided 16A gate oxide.

• IntroductionMobility and drive current performance

• Id-sat and Id-lin enhancement• Self-heating & temperature effect• Gate oxide & junction leakage• Unit channel resistance vs. lateral-field• Ring oscillator power delay• Summary

NMOS Vt Roll-off Characteristics

Channel width = 0.3 um

NMOS

Bulk

Strained-Si

Vt(

V)

0

0.1

0.2

0.3

0.4

0.5

0.065 0.07 0.16 0.5 10Lpoly (um)

•The Vt of strained-Si NMOS devices are well matched with bulk-Si devices within 30 mV for gate length from 65 nm to 10 um.

Short-channel NMOS Performance

0

200

400

600

800

1000

0 0.2 0.4 0.6 0.8 1 1.2Vd (V)

Id (u

A/u

m)

Strained-Si

Bulk

23%

Vg=1.2 V

(W = 0.3 um, Gate CD ~70 nm)

1.E-10

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

-0.2 0 0.2 0.4 0.6 0.8 1 1.2Vg (V)

Id (A

/um

)

Strained-Si

Bulk

Vd=1.2 V

• Vt of strained-Si device well matched with bulk’s (<20 mV).• Ioff of strained-Si device about 3 times larger than bulk’s.• Short channel drive current increases 23%.

Electron Mobility Enhancement

• Long channel electron mobility of strained silicon devices increased by 86% over bulk devices with matched Vt at high field.

W/L=10um/10umwith same Vt

0

100

200

300

400

500

600

0.2 0.4 0.6 0.8 1 1.2 1.4

Vertical Field (MV/cm)

Mob

ility

(cm2 V-1

s-1)

86%

StrainedSilicon

Bulk

W/L= 10um/10um

PMOS Vt Roll-off Characteristics

Channel width = 0.3 um0

0.1

0.2

0.3

0.4

0.5

0.065 0.07 0.16 0.5 10Lpoly (um)

Vt(

V)

PMOS

Bulk

Strained-Si

•The Vt of strained-Si PMOS devices are matched with bulk-Si devices within 50 mV for gate length from 65 nm to 10 um.

Short-channel PMOS Performance

1.E-11

1.E-09

1.E-07

1.E-05

1.E-03

-1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2Vg (V)

Id (A

/um

)

Strained-SiBulk

Vd=-1.2 V

(W = 0.3 um, Gate CD ~70 nm)

0

100

200

300

-1.2 -1 -0.8 -0.6 -0.4 -0.2 0Vd (V)

Id (u

A/u

m)

4% Vg-Vt= 0.8V

Strained-Si

Bulk

• Short channel PMOS drive current increases 4% for samples with the same Vg -Vt.

• Introduction• Mobility and drive current performance

Id-sat and Id-lin enhancement• Self-heating & temperature effect• Gate oxide & junction leakage• Unit channel resistance vs. lateral-field• Ring oscillator power delay• Summary

NMOS Transconductance@ linear region

0

100

200

300

0 0.2 0.4 0.6 0.8 1 1.2Vg (V)

Tra

nsco

nduc

tanc

e, G

m (u

S/um

)

Strained-Si

Bulk

41%

Vd = 50mV

(Gate CD ~70 nm)

• Short Channel Gm-max increases 41% at linear region for Vd = 50 mV.

NMOS Id-lin Performance

(Gate CD ~70 nm)

Id (u

A/u

m)

Id e

nhan

cem

ent (

%)

0

200

400

600

800

1000

Vd (V)

01020304050

Strained-Si

Bulk

Id-satGain ~ 23%

Id-linGain > 30%

0 0.2 0.4 0.6 0.8 1.0 1.2

Vg = 1.2V

•Larger Id-lin gain ( >30% for Vd < 0.6V) than Id-sat gain (23%). better driving capability for the switching cycle.

•Larger Id gain ( >40%) for medium gate field (i.e. Vg=0.6V). better driving capability for the switch cycle.

(Gate CD ~70 nm)

Id e

nhan

cem

ent (

%)

Vd (V)

0

30

60

90

120

150

180

0 0.2 0.4 0.6 0.8 1 1.2

Id (u

A/u

m)

01020304050

Strained-Si

Bulk

>40%

Vg = 0.6V

NMOS Drive Current @ Medium Gate Field

• Introduction• Mobility and drive current performance• Id-sat and Id-lin enhancement

Self-heating & temperature effect• Gate oxide & junction leakage• Unit channel resistance vs. lateral-field• Ring oscillator power delay• Summary

W/L=10 um/0.07um

Id (u

A/u

m)

0

200

400

600

800

1000

0 0.2 0.4 0.6 0.8 1 1.2Vd (V)

Bulk-Si

Strained -Si7% self-heating

Vg = 1.2 V

100ns PulseDC

Self-heating Effect- Pulsed vs. DC measurements

• Pulsed strained-Si NMOS Id-sat increases 7% than DC results while bulk devices exhibit no self-heating effect.

Gate CD ~ 75 nm

Vd (V)

0

200

400

600

800

1000

1200

0 0.2 0.4 0.6 0.8 1.0 1.2

Id (u

A/u

m)

Bulk

Vg = 1.2 V

Strained-Si23%

@25 C29%

@100 C

(W = 0.3 um, Gate CD ~70 nm)

Temperature Effect on Drive Current

•Strained NMOS Id-sat gain over bulk increases from 23% to 29% as temperature rises from 25C to 100C due to less degradation of strained-Si mobility at high temperature.

• Introduction• Mobility and drive current performance• Id-sat and Id-lin enhancement• Self-heating & temperature effect

Gate oxide & junction leakage• Unit channel resistance vs. lateral-field• Ring oscillator power delay• Summary

Junction Leakage Comparison

•Strained-Si shows a 25 X junction leakage increase under normal circuit operation condition @1.2V. •A large junction leakage was observed for reversed bias greater than 2.5V.

1.E-18

1.E-16

1.E-14

1.E-12

1.E-10

1.E-08

1.E-06

0 1 2 3 4 5Reversed Bias (V)

Lea

kage

Cur

rent

(A/u

m2 )

N+/P-well

Bulk-Si

Strained-Si

25X

Temperature Effect on Junction Leakage -12

1000/T (1/Kelvin)

-18

-17

-16

-15

-14

-13

1.8 2.3 2.8 3.3

Log

(Jr/

T^3

)

Strained-Si

Bulk

Reversed bias = 5VOverstressed P+/N junction Area = 80um*450um

25C100C

Intrinsic limit defect limit

narrowerbandgap

• Threading defect reduction is required to reach minimal junction leakage set by strained-Si narrower bandgap.

Gate and Junction Leakage Comparison

1.E-18

1.E-16

1.E-14

1.E-12

1.E-10

1.E-08

1.E-06

0 0.2 0.4 0.6 0.8 1 1.2Bias (V)

Lea

kage

Cur

rent

(A/u

m )2

NMOSGate oxide leakage

Bulk-Si

Strained-Si

Junction leakage

• Strained-Si demonstrated comparable gate leakage as bulk-Si.• Junction leakage of strained-Si remains much smaller than gate oxide leakage under normal circuit operation condition.

• Introduction• Mobility and drive current performance• Id-sat and Id-lin enhancement• Self-heating & temperature effect• Gate oxide & junction leakage

Unit channel resistance vs. lateral-field• Ring oscillator power delay• Summary

Unit Channel Resistance - Linear Region200

Vd=0.05V0

40

80

120

160

40 80 120 160Lpoly (nm)

tota

lR

=Vd/

Id (o

hm)

Strained-SiBulk-Si

Vg-Vt= 0.7V

Vg-Vt= 0.3V

Vg-Vt= 0.5V

slope

•By shift-and-ratio method, resistance slope dRtotal/dLpoly is extracted and defined as unit channel resistance without Leffand parasitic resistance uncertainties.

Unit Channel Resistance - Saturation Region1500

Lpoly(nm)

Vd=1.05V

tota

lR

=Vd/

Id (o

hm)

Vg-Vt= 0.3VStrained-SiBulk-Si

Vg-Vt= 0.7V

Vg-Vt= 0.5V

slope

0

300

600

900

1200

40 80 120 160

• Unit channel resistance can be extracted for various Vg and Vd.• At saturation region, unit channel resistance increases due to pinch-off.

4000 160

0

1000

2000

3000

0 0.2 0.4 0.6 0.8 1 1.2Vd (V)

dR/d

Lpo

ly(o

hm/u

m)

110

120

130

140

150

dR/d

Lpo

lyR

atio

(%)

Strained-Si

Vg-Vt = 0.4V

Bulk-Si

Linear -> Saturation regime

Unit Channel Resistance - Linear vs. Saturation

• Strained-Si short channel devices show a 32% smaller unit channel resistance at linear region.• The improvement decreases to 18% at saturation.

• Introduction• Mobility and drive current performance• Comparison of Id-sat and Id-lin enhancement• Self-heating & temperature effect• Gate oxide & junction leakage• Unit channel resistance vs. lateral-field

Ring oscillator power delay• Summary

5

10

15

20

25

30

35

40

45

0 500 1000 1500 2000 2500 30001/Icc (1/A)

Tpd

(ps)

bulk-Si

Strained-Si

0.9V

1.2V

1.0V

1.1V0.9V

1.2V

1.0V1.1V 2.2 ps faster

at the same Icc

0.8V

0.8V

Strained-Si Ring-Oscillator Gate Delay vs. Drive Current

151 stagesWp/Wn=3.25um/2.5um

Gate Length ~70nm

• Gate delay of ring oscillator for the same Icc current is improved over 2.2 ps due to better Id-lin gain of strained-Si.

Summary• Short channel strained-Si devices demonstrated including

self-heating/temperature effect.

• Strained-Si has a 25X larger Junction leakage due to defect which is still much smaller than gate oxide leakage.

• Larger Id-lin gain than Id-sat gain gives strained-Si device better driving capability over bulk-Si devices for circuit operation.

• Ring oscillator power-delay performance of strained-Sishows its great potential on high-performance low-power applications.