Neural Networks 60 (2014) 74–83

Contents lists available at ScienceDirect

Neural Networks

journal homepage: www.elsevier.com/locate/neunet

Noise cancellation of memristive neural networksShiping Wen a,b, Zhigang Zeng a,b,∗, Tingwen Huang c, Xinghuo Yu d

a Department of Control Science and Engineering, Huazhong University of Science and Technology, Wuhan 430074, Chinab Key Laboratory of Image Processing and Intelligent Control of Education Ministry of China, Wuhan 430074, Chinac Texas A & M University at Qatar, Doha 5825, Qatard Platform Technologies Research Institute, RMIT University, VIC 3001, Australia

h i g h l i g h t s

• Scalable massively parallel architecture improves the hardware functionality.• The state of A-GST memristive devices will decay over long time.• The computation results can be read out without altering the states of synapses.• A-GST memristive devices make the memristive synapses robustness.

a r t i c l e i n f o

Article history:Received 2 May 2014Received in revised form 20 June 2014Accepted 31 July 2014Available online 8 August 2014

Keywords:MemristorStabilityNeural network

a b s t r a c t

This paper investigates noise cancellation problem of memristive neural networks. Based on thereproducible gradual resistance tuning in bipolar mode, a first-order voltage-controlled memristivemodel is employed with asymmetric voltage thresholds. Since memristive devices are especially tiny tobe densely packed in crossbar-like structures and possess long time memory needed by neuromorphicsynapses, this paper shows how to approximate the behavior of synapses in neural networks using thismemristive device. Also certain templates of memristive neural networks are established to implementthe noise cancellation.

© 2014 Elsevier Ltd. All rights reserved.

1. Introduction

The sequential processing of fetch, decode, and executionof instructions through the classical von Neumann bottleneckof conventional digital computers has resulted in less efficientmachines as their eco-systems have grown to be increasinglycomplex (Jo et al., 2010). Though the current digital computerscan now possess the computing speed and complexity to emulatethe brain functionality of animals like a spider, mouse, and cat(Ananthanarayanan, Eser, Simon, &Modha, 2009; Smith, 2006), theassociated energy dissipation in the system grows exponentiallyalong the hierarchy of animal intelligence. For example, to performcertain cortical simulations at the cat scale even at 83 times slowerfiring rate, the IBM team in Ananthanarayanan et al. (2009) has

∗ Corresponding author at: Department of Control Science and Engineering,Huazhong University of Science and Technology, Wuhan 430074, China. Tel.: +8618971124190; fax: +86 27 87543130.

E-mail addresses: wenshiping226@126.com (S. Wen), zgzeng527@126.com(Z. Zeng), tingwen.huang@qatar.tamu.edu (T. Huang), x.yu@rmit.edu.au (X. Yu).

http://dx.doi.org/10.1016/j.neunet.2014.07.0140893-6080/© 2014 Elsevier Ltd. All rights reserved.

to employ Blue Gene/P (BG/P), a super computer equipped with147,456 CPUs and 144 TBs ofmainmemory. On the other hand, thehuman brain not only contains more than 100 billion neurons andeach neuron has more than 20,000 synapses, but also consumesinfinitesimal power and maintains its memory for a long period,even decades. Therefore, it is very important to build a brain-likemachine.

Furthermore, the implementation of neuromorphic circuits andchips has long been hindered by challenges related to area andpower consumption restrictions. More than tens of transistors andcapacitors are needed to estimate a synapse (Rachmuth & Poon,2008). In particular, when neural connections become high level, alarge part of neuromorphic chips are utilized for synapses, whereasneurons take only a small portion compared to that of synapses.However, shrinking the current transistor size is very difficult.Therefore, it is critical to introduce a more efficient approach toimplement neuromorphic circuits and chips.

Memristors, as the fourth electrical elements theoretically pro-posed by Leon Chua in 1971 (Chua, 1971), are two-terminal elec-tronic devices that memorize the flowing charge. In fact, they areresistive in essence, but their resistance can be altered electrically

S. Wen et al. / Neural Networks 60 (2014) 74–83 75

with nonlinear properties. Since the first realization of a work-ingmemristorwas announced in a Pt/TiO2/Pt by Hewlett–PackardLaboratories (Strukov, Snider, Stewart, & Wiliams, 2008), memris-tors and memristive devices have been widely investigated anddiscussed for their prospective applications in nonvolatile mem-ories (Kwon et al., 2010; Muenstermann, Menke, Dittmann, &Waser, 2010), logic devices (Borghetti et al., 2010; Linn, Rosezin,Tappertzhofen, BÖttger, & Waser, 2012), neuromorphic devices(Chang, Jo, & Lu, 2011; Jo et al., 2010; Krzysteczko,Münchenberger,Schäfers, Reiss, & Thomas, 2012), and neuromorphic self-organizedcomputation and learning (Snider, 2007, 2011). Furthermore, re-searchers have packed memristors into crossbars to form densememories (Shin, Kim, & Kang, 2012), and designed integrated cir-cuitry compatible with CMOS processes (Xia et al., 2009). There-fore, memristors can be integrated with conventional integratedcircuitry. Although the state of memristor will decay over time, thetime constant can be as long as weeks to decades, Kim et al. re-ported stable retention characteristics for more than 104s at 85 °C(Kim, Park et al., 2011). All these make the memristors candidatesto be used as synaptic circuits.

Due to the promising applications in wide areas, various mem-ristive materials, such as ferroelectric materials (Jiang et al., 2011),chalcogenide materials (Li et al., 2013; Pandian et al., 2009;Soni et al., 2011; Sun, Hou, Wu, & Tang, 2009), metal oxides(Yang et al., 2010; Yu, Wu, & Wong, 2011), have been attractedgreat attention. And several physical mechanisms are proposedto illustrate the memristive behaviors, such as electronic barriermodulation from migration of oxygen vacancies (Chang et al.,2011; Kim, Siddik et al., 2011; Krzysteczko et al., 2012; Yang et al.,2008, 2010), voltage-controlled domain configuration (Chanth-bouala et al., 2012), formation and annihilation of conducting fila-ments via diffusion of oxygen vacancies (Kwon et al., 2010; Yan,Guo, Zhang, & Liu, 2011), trapping of charge carriers (Fujimoto,Koyama, Nishi, & Suzuki, 2007; Peng et al., 2012) and metal ionsfrom electrodes (Bishop et al., 2011; Huang, Shi, Yeo, Yi, & Zhao,2012). The model of voltage controlled memristor with thresholdswas first introduced by Pershin and Ventra (2010).

As an example to illustrate the feasibility of memristor model,the memristance of an Ovonic chalcogenide device was selectedby Chua (1971), and has been investigated recently, such asthe filamentary bipolar memristive switching in Ge2Sb2Te5 (GST)(Woo et al., 2011). And GST has been proved to be an idealchoice formemristivematerials, however, the resistance switchingbehaviors in Sb-rich GST based devices rely on the formationof conductive paths (Pandian, Kooi, Palasantzas, & De Hosson,2007). The intrinsic memristance of stoichiometric crystalline GSTwas revealed by Li et al. (2013). A voltage-controlled memristivesystem with symmetric voltage thresholds is considered as theresistance which could be modulated within a certain rangedepending on the voltage polarity and amplitude to make thefilament conduct or rupture.

It is worth noting that neural networks have been widelyinvestigated in recent years, for their immense applicationprospective (Guo, Wang, & Yan, 2013, 2014; He, Li, Huang, & Li,2014; He, Li, & Shu, 2012; Li, Liao, Li, Huang, & Li, 2011; Liu &Wang, 2008, 2013; Luo & Wu, 2012; Wen, Zeng, & Huang, 2013a,2013b;Wu & Luo, 2012). A creative information processing systemcalled cellular neural network (CNN) was proposed by Chua andYang in 1988, which came from the HNN and cellular automataas an effective combination of both characteristics (Chua & Yang,1988a, 1988b).Many applications have been developed in differentareas such as combinatorial optimization, knowledge acquisitionand pattern recognition. In recent years, more andmore attentionshave been attracted to the design and analysis of memristiveneural networks, such as memristor-based spiking neuromorphic

networks to implement the Spike-Timing-Dependent-Plasticity(STDP) rule (Afifi, Ayatollahi, & Raissi, 2009), using memristorsto implement the neighborhood connections of a cellular neuralnetwork (Ebong & Mazumder, 2012; Lehtonen & Laiho, 2010), anddesign of simple associative memory circuit based on memristor-based synapses (Pershin & Ventra, 2010). These pioneering worksare meaningful for further investigation of memristive neuralnetworks, and provide novel ideas to implement memristiveartificial intelligences.

However, there also exist several concerns in the design ofmemristive neural networks, such as

• which specific materials can be used as memristive devices inthese networks;• how to solve the problems of memristive device variation;• how to realize real-time monitoring the memristor state and

off-line training, as directly programming the resistance of asinglememristor to the target value is likely impossible (Jo et al.,2010);• how to design the memristive neuromorphic circuits to

implement the function of noise cancellation.

To overcome these difficulties, GST memristors are used asbinary memories, and corresponding algorithms are proposedto implement the transfer function. Meanwhile, employing thestable retention and threshold characteristics, GST memristors aretaken into account to implement the synaptic circuits for neuralnetworks. Furthermore, the state evolution is implemented via theadvantages of the voltage-controlled threshold properties.

2. Memristance of amorphous-Ge2Sb2Te5 (A-GST)

A typical crossbar-structure A-GST based memristor is fabri-cated by micro/nano processes as shown in Fig. 1. A-GST is sand-wiched between Cu and Cu/Ag, where Ag layer serves as the cationsource. This two terminal device can be used as a neuromorphicsynapse. And an electrical system is built up to perform electricalmeasurements. The states of this device can be switched to amor-phous or crystalline ones. To investigate thememristance of A-GST,this memristive device is first set to behavior in crystalline state.Then, the memristive behavior can be observed in crystalline-GST under clockwise voltage sweep 0.6 V→−1.5 V→ 0.6 V, asdemonstrated in Fig. 1.

It is obvious that the resistance can bemodulatedwith a certainrange via switching the voltage polarity. The lowest resistancestate (LRS) is below 3 K�, while the highest resistance state (HRS)is over 18 K�. And the switching voltage is 0.35 V. To simplifythemodel of the A-GSTmemristive device, a thresholdmemristivemodel (Pershin & Ventra, 2010) is considered as follows:

I = M−1VM ,

M = f (VM)

θ(VM)θ

MR1− 1

+ θ(−VM)θ

1−

MR2

,

f (V ) = −βV +β − α

2

|V + VL| − |V − VR| + VR − VL

, (1)

where I and VM represent the current through and voltage dropon the device, respectively, M is the internal state variable asthe memristance R, α and β characterize the rate of memristancechange when |VM | is less or greater than threshold voltage,respectively, there VL and VR are threshold voltages, and the unitstep functions θ(·) guarantee the memristance can change onlybetween R1 and R2. According to (1), if VL ≤ V ≤ VR, M = 0, thedevice keeps constant resistance under relatively low operationvoltage.

Based on the threshold feature, Querlioz et al. investigated can-cellation to device variations in a spiking neural network with

76 S. Wen et al. / Neural Networks 60 (2014) 74–83

Fig. 1. I-V characteristics of the device, exhibiting amemristive hysteresis loop. Theblue arrows show the directions of sweeping voltage, and HRS and LRS representhigh and low resistance states respectively.

memristive nanodevices (Querlioz, Bichler, Dollfus, & Gamrat,2013), Gao et al. proposed a hybrid CMOS/memristor implemen-tation of a programmable threshold logic gate (Gao, Alibart, &Strukov, 2013). These mentioned works develop a new way to in-vestigate in the application field of memristive devices. Based onthese excellentworks, this paper proposes a scheme to realize real-time monitor of the memristor state and off-line training in thecase that directly programming the resistance of a single memris-tor to the target value is likely impossible.

3. Neuromorphic learning and circuit implementation

As memristor can record the electrical excitations on itselfand occur corresponding resistance change like the biologicsynapses with very little decay for long periods of time. Severalbreakthroughs have been motivated in the design of memristiveneuromorphic systems and neural networks (Jo et al., 2010).However, it is difficult to realize real-time monitoring thememristor state and off-line training, as directly programmingthe resistance of a single memristor to the target value is likelyimpossible. Then it is necessary to discretely implement thememristive synapses in order to maximize noise cancellation,minimize power dissipation and so on. Therefore, it is particularlydesirable to implement the weights through binary memristivedevices that communicate via spikes rather than analog voltages,as biology itself takes discrete spikes to communicate. Hence, ascheme is needed to approximate continuous signals and modelswith discrete ones.

Based on the threshold A-GST memristive device, each A-GSTmemristive device is used to store a single bit, such as using HRSto present a logic 0 bit value, and the LRS to present a logic 1 bitvalue. As the existence of threshold voltages, these devices can berapidly altered their resistance, and low voltages have negligibleeffect on this kind of memristive devices, while larger voltages canmake them rapidly change their resistance. Therefore, a positivevoltage more than the positive ‘On’ threshold will make A-GSTmemristive devices switch into the LRS, meanwhile, a negativevoltage below the negative ‘Off’ threshold will make A-GST switchinto HRS. When an analog voltage input x drops through an A-GSTmemristive synapse whose memconductive is ω, we can get theoutput

y = ωx. (2)

where y denotes the desired synaptic current. An abstract circuit isgiven to implementmemristive synapses in Fig. 2. This schematic isa clocked or synchronous circuit that is evaluated at discrete-timesteps. First, the continuous analog input signal x is transformedto a discrete digital approximation by a ‘Thermometer’ code. This

Fig. 2. (a) Memristive synapse, (b) discrete approximation implementation of thissynapse, much of this circuitry can be shared by multiple synapses.

coding method can convert the analog signals within the range[0 1] into a discrete version. Although this encoding is less efficientthan a binary numerical one, it ismuch simpler to be implemented,and an example is given in Table 1.

In this coding method, we set the first M bits of an N bitcodeword to be 1 and the rest to be 0, where

M = x(N + 1), (3)

x is the analog input value. Hence, the precision of the discreteapproximation of the analog input value x is determined by thevalue chosen for N . An auxiliary continuous variable x can bedefined as

x ≡1N

Ni=1

xi, (4)

where x ∼= x. In the same way, the weight variable ω will bereplaced with N binary variables ω1, . . . , ωN , then

ω ≡1N

Ni=1

ωi, (5)

where ω ∼= ω.To implement the circuit in Fig. 2, an analog input x is encoded

by thermometer code to produce the code vector (x1, . . . , xN),which is sent in parallel to a circular shift register. Then, thisshift register is clocked N times to send spikes through thebinary switches ωi to an integrator which accumulates the spikesweighted in variable y. The algorithm is presented as follows:

Algorithm 1 Discrete implementation of transfer functionInitialization:

Encode x→ x1, . . . , xN ; ω→ ω1, . . . , ωN ;Set y← 0; i← 1; j← 0;

Iteration:1: while i = N do2: while j = N − 1 do3: y← y+ 1

N2 xmod(i+j,N)ωi;j← j+ 1;

4: end whilei← i+ 1;

5: end while

S. Wen et al. / Neural Networks 60 (2014) 74–83 77

Table 1An example of 4 bit thermometer code.

Analog in 0.00 0.25 0.35 0.41 0.65 0.80 0.99Digital out 0000 1000 1000 1100 1110 1111 1111

Fig. 3. Circuit implementation of a single memristive switch.

From this algorithm, we can get

y =1N2

N−1j=0

Ni=1

xmod(i+j,N)wi

=1N

Ni=1

ωi1N

N−1j=0

xmod(i+j,N)

=1N

Ni=1

ωix

= ωx≈ ωx. (6)

For a single memristive switch as shown in Fig. 3, during theevaluation of the transfer function, S1 is switched to state positionand S2 is closed. A narrow spike is sent in each step when xi = 1,otherwise, no spike is sentwhen xi = 0, and these spikes are belowthe threshold voltages that cannot alter the value of the A-GSTmemristive device. And during the learning stage, which occursat last in a major cycle, S1 is switched to learn position, f (xi) andg(xi) cooperate to refresh the state of ωi. S2 keeps closed in orderto discharge the integrator and reset variable y to 0.

To implement Fig. 2, eachmajor cycle is divided intoN+1 stepsas shown in Fig. 4. The first N steps are used to implement theevaluation of the transfer function an approximation of the desiredoutput signal xω can be computed, and the final step is used toimplement the synaptic weight update.

4. Memristive neural networks and applications

In this section, a circuit scheme of a two-dimensional memris-tive neural network is designed, An MNN is composed of severalprocessing units, and each unit, denoted as U(i, j) is connected toits adjacent ones, therefore, only the neighboring ones can interactdirectly with each other. Meanwhile, all units are arranged in gridswithM rows andN columns as shown in Fig. 5. For each processingunit U(i, j), the following set Nr(i, j), named r-neighborhood, canbe defined as follows:

Nr(i, j) =U(i, j)| max

1≤k≤M,1≤l≤N(|k− i|, |l− j|) ≤ r

(7)

where r is a positive integer denoting the neighborhood radius ofeach unit, and the pairs (i, j) and (k, l) are indices which expressthe position of units in the grid. In practice, the units which belongto the r-neighborhood of U(i, j) are arranged in a maximum (2r +1)× (2r + 1) grid whose central element coincides with U(i, j).

Fig. 4. Circuitry input signals f (xi) and g(xi) (N = 4).

Fig. 5. Two-dimensional memristive neural network grid.

One unit of the connected neural networks can be presented asin Fig. 6. The node voltage Vxij ofU(i, j) denotes the state of the unitand its initial state is assumed to be not greater than 1. The nodevoltage Vuij presents the input of U(i, j), and is assumed to be lessthan or equal to 1. And Vyij is the output of U(i, j).

After certain mathematical transformation, we can get thedynamics of each processing unit as following equations:

xij = −xij(t)+

U(k,l)∈Nr (i,j)

Aij,klykl(t)

+

U(k,l)∈Nr (i,j)

Bij,klukl(t)+ Iij,

yij(t) = f (xij(t)) =12(|xij(t)+ 1| − |xij(t)− 1|),

(8)

where i = 1, . . . ,M, j = 1, . . . ,N; xij(t), uij(t) and yij(t) are thestate, the input and the output of the (i, j)th processing unit in

78 S. Wen et al. / Neural Networks 60 (2014) 74–83

Fig. 6. (a) The structure of memristive unit circuit, where C, Rx , and Ry are the capacitor and resistors; I is an independent current source; Ixu(i, j; k, l) and Ixy(i, j; k, l) arelinear voltage-controlled current sources with the characteristics Ixy(i, j; k, l) = A(i, j; k, l)Vykl and Ixu(i, j; k, l) = B(i, j; k, l)Vukl,∀U(i, j) ∈ N(i, j); Iyx =

f (Vxij)Ry

is a piecewise-linear voltage-controlled current source; (b) a simplified unit with the basic elements and Ixy(i, j; k, l) = A(i, j; k, l)Vykl; (c) a possible circuit implementation of above unit,in which the controlled current source Ixy(i, j; k, l) can be presented as Ixy(i, j; k, l) =

−M1VyklR1R2

under the condition that M1R1=

R2+R3M2

, then the transmission weights of Vykl

can be adjusted through the memristorsM2 and M1 . The piecewise function can be realized by op amps as Vxij(M3+R4)

R4=

Vyij(M4+R5)

R5+ |Vcc |, Vcc is the supply voltage.

the grid. The initial condition |xij(0)| ≤ 1 and static input |uij| ≤

1. Aij,kl, Bij,kl denote the connection weight from processing unitU(k, l) to unitU(i, j); Ii,j represents the bias of the (i, j)th unit in thegrid. From Eq. (8), it infers that the state and the output of each unitare affected by the inputs and the outputs of its adjacent units. Theworking structure of Eq. (8) and the output function are depictedin Fig. 7.

Eq. (8) can be rewritten in a compact form by the followingmatrix equation:x = −x(t)+ Ay(x(t))+ Bu+ I,

y(x(t)) = f (x(t)) =12(|x(t)+ 1| − |x(t)− 1|),

(9)

orxi = −xi(t)+

nj=1

aijyj(xj(t))+n

j=1

bijuj + I,

yi(xi(t)) = f (xi(t)) =12(|xi(t)+ 1| − |xi(t)− 1|),

(10)

where the state vector x(t) = [x1(t) . . . , xn(t)]T , the output vectory(x(t)) = [y1(x1(t)) . . . , yn(xn(t))]T , the static input vector u =[u1 . . . , un]

T , the output function vector f (x(t)) = [f1(x1(t)) . . . ,

fn(xn(t))]T , A = {aij} ∈ Rn×n, B = {bij} ∈ Rn×n are feedback andcontrol matrices respectively, n = M × N . I = [I, . . . , I]T is thevector containing the bias of each unit.

S. Wen et al. / Neural Networks 60 (2014) 74–83 79

Fig. 7. (a) System structure of U(i, j); (b) its corresponding output function.

Suppose the templates A, B and the bias I are given as

A =

a−1,−1 a−1,0 a−1,1a0,−1 a0,0 a0,1a1,−1 a1,0 a1,1

,

B =

b−1,−1 b−1,0 b−1,1b0,−1 b0,0 b0,1b1,−1 b1,0 b1,1

,

I = Ii,j.

Then the entries of the matrices A = {ai,j} ∈ Rn×n, and B = {bi,j} ∈Rn×n can be computed as follows:

ai,j =aq−k,w−l, if |q− k| ≤ 1 and |w − l| ≤ 1,0, otherwise, (11)

and

bi,j =bq−k,w−l, if |q− k| ≤ 1 and |w − l| ≤ 1,0, otherwise, (12)

where i = 1, . . . ,M, j = 1, . . . ,N; k, l, q and w are given asfollows:

k = iN

, l = i− (k− 1)N,

q = jN

, w = j− (q− 1)N,

in which operator [·] denotes the ceiling function and the pairs(k, l) and (q, w) indicate the position of the interconnected unitsin the r-neighborhood.

In this paper, an approach is proposed to design templates usedto reduce the noise in the images. The templates are trained by

a noisy image (represented as the static input vector u) and acorresponding desired image (represented as the output vector y∗that we want at steady state). The nonlinear output function ofmemristive neural network always guarantees the existences ofequilibrium point of system (9). In order to simplify the analysis,we shift the equilibrium point x∗ = [x∗1, . . . , x

∗n]

T of (9) to theorigin. Let zi(t) = xi(t)− x∗i , system (9) can be transformed intoz = −z(t)+ AΦ(z(t)),y(z(t)+ x∗) = f (z(t)+ x∗),

(13)

where z(t) = [z1(t), . . . , zn(t)]T is the state vector, Φ(z(t)) =[Φ1(z1(t)), . . . , Φn(zn(t))]T represents the output vector of thetransformed system and Φi(zi(t)) = yi(zi(t) + x∗) − yi(x∗i ), |Φi(zi(t))| ≤ |zi(t)|, which implies

Φ2i (zi(t)) ≤ zi(t)Φi(zi(t)), ∀i,

or

ΦT (z(t))Φ(z(t)) ≤ ΦT (z(t))z(t). (14)

In order to derive the main result, Schur Complement Lemmawill be utilized.

Lemma 1 (Boyd, Ghaoui, Feron, & Balakrishnan, 1994). Givenconstant matrices Y1, Y2 and Y3 of appropriate dimensions, where Y1and Y3 are symmetric and Y2 > 0, then Y1 + Y T

2 Y−13 Y2 < 0 if and

only ifY1 Y T

2Y2 −Y3

< 0, or

−Y3 Y2

Y T2 Y1

< 0. (15)

In the next step, a criterion for the uniqueness and globalasymptotic stability of the equilibrium point of the memristiveneural network (9)will be derived on the base of Lyapunov stabilitytheorem (the template A is solved).

80 S. Wen et al. / Neural Networks 60 (2014) 74–83

Theorem 1. Consider the dynamical behavior of memristive neuralnetwork (9), if there exists

AT+ A < 0, (16)

then, the equilibrium point x∗ of system (9) is uniquely and globallyasymptotically stable for every Bu+ I .

Proof. The proof of this theorem is divided into two steps: in thefirst step the uniqueness of the equilibrium point is discussed, andin the second step the proof of global asymptotic stability criterionof the equilibrium will be accomplished.

• Step 1. The uniqueness of the equilibrium point will be provedby the contradiction method. The equilibrium point z∗ ofsystem (10) satisfies the following equation

z∗ − AΦ(z∗) = 0, (17)

which implies that if Φ(z∗) = 0. In the following part, weassume that Φ(z∗) = 0. From (14), we can get

2ΦT (z∗)z∗ − 2ΦT (z∗)AΦ(z∗) = 0. (18)

which can be rewritten as

2ΦT (z∗)AΦ(z∗) = 2ΦT (z∗)z∗

= 2ΦT (z∗)[z∗ − Φ(z∗)] + 2ΦT (z∗)Φ(z∗).(19)

With inequality (14), we can infer from Eq. (19) that

ΦT (z∗)(AT+ A)Φ(z∗) ≥ 0. (20)

On the other hand, from the criterion (16) for the globalasymptotic stability, it follows

ΦT (z∗)(AT+ A)Φ(z∗) < 0. (21)

Obviously, (20) contradicts with Eq. (21), which implies thatΦ(z∗) = 0 and z∗ = 0. Thus, Eq. (10) has a unique equilibriumfor every u.• Step 2. In order to prove the global asymptotic stability of

the origin, we choose the following positive definite Lyapunovfunctional

V (z(t)) = zT (t)z(t)+ 2ϕn

i=1

zi(t)

0Φi(s)ds, (22)

where ϕ is a positive constant. The time derivative of V (z(t))along trajectory of system (9) is obtained as

V (z(t)) = −2zT (t)z(t)+ 2ΦT (z(t))AT z(t)

− 2ϕΦT (z(t))z(t)+ 2ϕΦT (z(t))AΦ(z(t))

= −2zT (t)z(t)+ 2ΦT (z(t))AT z(t)

+ 2ϕΦT (z(t))AΦ(z(t))− 2ϕΦT (z(t))Φ(z(t))− 2ϕΦT (z(t))[z(t)− Φ(z(t))]

≤ −2zT (t)z(t)+ 2ΦT (z(t))AT z(t)

+ 2ϕΦT (z(t))AΦ(z(t))

− 2zT (t)z(t)+ 2ΦT (z(t))AT z(t)

+ϕΦT (z(t))AΦ(z(t))+ ϕΦT (z(t))ATΦ(z(t))

≤zT (t) Φ(z(t))

−2I AAT ϕ(AT

+ A)

z(t)

Φ(z(t))

.

(23)

Therefore, if−2I AAT ϕ(AT

+ A)

< 0 (24)

Fig. 8. Training images. (a) Corrupted image with 5% noise; (b) corrupted imagewith 10% noise; (c) desired image.

then V (z(t)) < 0,∀z(t) = 0. By Lemma 1, inequality (24) holdsif and only if

ϕ(AT+ A)+

12AT A < 0 (25)

which implies

AT+ A < 0. (26)

It is obvious V (z(t)) < 0,∀z(t) = 0. Thus V (z(t)) ≤ 0. More-over, V (z(t)) = 0 if and only if z(t) = Φ(z(t)) = 0. On theother hand, V (z(t)) is radially unbounded as ∥z(t)∥ → ∞ thenV (z(t)) → ∞. Therefore, under the conditions in Theorem 1,the equilibrium point x∗ of Eq. (10) is globally asymptoticallystable for any Bu+ I . The proof is completed.

Then, via the mathematical analysis approach, template B andbias I of memristive neural network (9) is designed to achievedesirable output y∗ at steady state. The equilibrium equation of(10) can be written as−x

∗

i +

nj=1

aijy(x∗j )+n

j=1

bijuj + I = 0,

y∗i = yi(x∗i ) = f (x∗i ),(27)

where ui is the input that depends on the noisy image of trainingsample, y∗i is the output at steady state that depends on thecorresponding desired image of training sample, A is the feedbackmatrix that can be calculated by (16), and B is the inputmatrix thatcan be obtained at this step.

Based on the property of saturation nonlinearity, Eq. (10) can berewritten as the following inequalities

nj=1

aijy(x∗j )+n

j=1

bijuj + I ≥ 1, if y∗i = 1,

nj=1

aijy(x∗j )+n

j=1

bijuj + I ≤ −1, if y∗i = −1,(28)

where i = 1, . . . ,MN.Combining (16) and (28) forms the main result in this section,

and this can be utilized to design the templates of memristiveneural networks to reduce noise. The image is coded in this waysuch that+1 corresponds to white pixels and−1 to black ones.

S. Wen et al. / Neural Networks 60 (2014) 74–83 81

Fig. 9. (a) Desired images; (b) corrupted image with 5% noise; (c) image aftermemristive neural networkwith templates in (29)–(31); (d) image aftermemristiveneural network with templates in (32)–(34).

Fig. 10. (a) Desired images; (b) corrupted image with 10% noise; (c) image aftermemristive neural networkwith templates in (29)–(31); (d) image aftermemristiveneural network with templates in (32)–(34).

5. Illustrative simulations

In this section, an example is presented to illustrate theeffectiveness of the proposed design method. Different binarytraining samples shown in Fig. 8 (with smaller size 16 by 16) areutilized to train the templates of noise cancellation memristiveneural network. Firstly, the binary training sample, that consists ofan image corruptedwith 5% noise in Fig. 8(a), 10% noise in Fig. 8(b),and desired image in Fig. 8(c), is employed to train the templatesof memristive neural networks.

Consider the corrupted imagewith 5% noise and its correspond-ing desired image in Fig. 8(a) and (b), by Eqs. (16) and (28), we canget the corresponding templates of thememristive neural networkas

A =

−12.8401 6.4487 −9.53710.4919 −10.1734 0.3370−9.9858 7.6064 10.8957

, (29)

B =

16.4018 12.7333 11.005610.6774 34.1425 12.295312.1814 13.6522 7.4701

, (30)

Fig. 11. (a) Desired images; (b) corrupted image with 5% noise; (c) image aftermemristive neural networkwith templates in (29)–(31); (d) image aftermemristiveneural network with templates in (32)–(34).

Fig. 12. (a) Desired images; (b) corrupted image with 10% noise; (c) image aftermemristive neural networkwith templates in (29)–(31); (d) image aftermemristiveneural network with templates in (32)–(34).

I = 11.4319. (31)

Similarly, using the samples in Fig. 8(a) and (c), we can get thefollowing templates to reduce the noise in corrupted images with10% noise

A =

−4.5128 −7.8407 −9.2239−5.7617 −19.2628 −5.4550−7.8025 −9.7782 7.7817

, (32)

B =

14.8357 27.3136 23.642319.0975 35.7279 17.691424.2931 47.2548 13.3251

, (33)

I = 37.0287. (34)

By the training templates, we can get the processing results inFigs. 9–12.

In order to analyze the performance of noise cancellation ofmemristive neural networks under different levels of noise ratio,

82 S. Wen et al. / Neural Networks 60 (2014) 74–83

Fig. 13. (a) RER values for various templates of memristive neural networks; (b) REN values for various templates of memristive neural networks.

the reconstruction error rate is introduced

RER =1

2MN

Mi=1

Nj=1

|yij − yij| × 100%, (35)

where yij is the pixel of the desired images, yij is the pixelof the reconstruction image at the output of the memristiveneural network, M and N are the horizontal and vertical horizons.Moreover, the reconstruction error rate can be compared with thenoise ratio of the input noisy image by the following index

REN =NR− RER

NR× 100%, (36)

where NR denotes the noise ratio of the corrupted image. Obvi-ously, the smaller RER and larger REN are, the performance of thetemplatesworks better. The values of the RER and REN for differenttemplates under different levels of noise ratio are shown in Fig. 13.

From Fig. 13, it is obvious that the noise in the image waseliminated greatly, which demonstrates the effectiveness of theproposed method, and the templates trained by samples withhigher noise ratio perform better than the those trained by lowernoise ratio.

6. Discussion and summary

Neural networks are used widely in different areas such ascombinatorial optimization, knowledge acquisition and patternrecognition. It requires to adjust the weight between the twoneurons it connects during the training process. Memory needs tobe held in the synaptic weights; and if the memory were volatile,then in the case of power loss, what have been learned will be lost.Both problems will appear to store synaptic weights in external,nonvolatile memory, such as flash with high bandwidth. Then itdeserves to investigate how synapses can be trained and storedlearning information without external memory.

A-GST memristive devices provide a preferable choice as theyare non-volatile, nanoscale, can be fabricated with CMOS circuitryand to form dense memories in crossbars. A scheme is given inthis paper to exploit the features to build such neuromorphicsynapses, and this will promote the development of neuromorphicintegrated circuitry which are close to the level of biologicaldensity and power. Compared with conventional neural networks,the advantages of A-GST memristive neural networks are obviousas follows:1. Scalablemassively parallel architecturewith entwinedmemory

and computation, makes it possible to achieve higher integra-tion densities and complex connectivity to improve the hard-ware functionality.

2. The state of A-GST memristive devices will decay over longtime, which means information can be stored for sufficientlylong times.

3. Discrete approximation implementation of memristive synap-ses makes memristive neural networks be able to initializememory states, this is quite different from the case dependingon pulse polarity, which applies a high-amplitude pulse of suf-ficient length to guarantee the device switches to one of its lim-iting states.

4. The computation results can be read out without altering thestates of memristive synapses.

5. The threshold property of A-GSTmemristive devices makes thememristive synapses robustness against small variations andnoises as small variations or perturbations cannot come overthe threshold values.

6. The circuit elements inA-GSTmemristive neural networks neednot to be replaced when the training samples changed whichmeans the update of connection weights and implemented byre-organized the connecting resistances in convention.

In summary, this paper concerns several problems in the designof memristive neural networks to take A-GST memristive devicesto cancellation the variation and perturbation problems andrealize real-time monitor of the memristor’s state and off-linetraining. And this will promote the development of neuromorphicintegrated circuits to imitate biological-scale brains.

Acknowledgments

This work was supported by the Natural Science Foundationof China under Grant 61125303, National Basic Research Programof China (973 Program) under Grant 2011CB710606, the Programfor Science and Technology in Wuhan of China under Grant2014010101010004, the Program for Changjiang Scholars andInnovative Research Team in University of China under GrantIRT1245. This publication was made possible by NPRP grant #4-1162-1-181 from the Qatar National Research Fund (a memberof Qatar Foundation). The statements made herein are solely theresponsibility of the author[s].

References

Afifi, A., Ayatollahi, A., & Raissi, F. (2009). Implementation of biologically plausiblespiking neural network models on the memristor crossbar-based CMOS/nanocircuits. In European conference on circuit theory and design, Aug. 23–27 (pp. 563-566).

Ananthanarayanan, R., Eser, S., Simon, H., & Modha, D. (2009). Proceedings of2009 IEEE/ACM conference high performance networking computing Portland, OR,November.

S. Wen et al. / Neural Networks 60 (2014) 74–83 83

Bishop, S., Bakhru, H., Novak, S., Briggs, B., Matyi, R., & Cady, N. (2011).Ion implantation synthesized copper oxide-based resistive memory devices.Applied Physics Letters, 99, 202102.

Borghetti, J., Snider, G. S., Kuekes, P. J., Yang, J. J., Stewart, D. R., & Williams, R.S. (2010). ‘Memristive’ switches enable ‘stateful’ logic operations via materialimplication. Nature, 464, 873–876.

Boyd, S., Ghaoui, L., Feron, E., & Balakrishnan, V. (1994). Linear matrix inequalitiesin system and control theory. Philadelphia: Society for Industrial and AppliedMathematics.

Chang, T., Jo, S. H., & Lu, W. (2011). Short-term memory to long-term memorytransition in a nanoscale memristor. ACS Nano, 5, 7669–7676.

Chanthbouala, A., Garcia, V., Cherifi, R. O., Bouzehouane, K., Fusil, S., Moya, X., et al.(2012). A ferroelectric memristor. Nature Materials, 11, 860–864.

Chua, L. O. (1971). Memristor-the missing circuit element. IEEE Transactions onCircuit Theory, 18, 507–519.

Chua, L., & Yang, L. (1988a). Cellular neural networks: theory. IEEE Transactions onCircuits and Systems, 35(10), 1257–1272.

Chua, L., & Yang, L. (1988b). Cellular neural networks: application. IEEE Transactionson Circuits and Systems, 35(10), 1273–1290.

Ebong, I. E., & Mazumder, P. (2012). CMOS and memristor-based neural networkdesign for position detection. Proceedings of the IEEE, 100(6), 2050–2060.

Fujimoto, M., Koyama, H., Nishi, Y., & Suzuki, T. (2007). Resistive switchingproperties of high crystallinity and low-resistance Pr0.7Ca0.3MnO3 thin filmwith point-contacted Ag electrodes. Applied Physics Letters, 91, 223504.

Gao, L., Alibart, F., & Strukov, D. (2013). Programmable CMOS/memristor thresholdlogic. IEEE Transactions on Nanotechnology, 12(2), 115–119.

Guo, Z., Wang, J., & Yan, Z. (2013). Global exponential dissipativity and stabilizationof memristor-based recurrent neural networks with time-varying delays.Neural Networks, 48, 158–172.

Guo, Z.,Wang, J., & Yan, Z. (2014). A systematicmethod for analyzing robust stabilityof interval neural networks with time-delays based on stability criteria. NeuralNetworks, 54, 112–122.

He, X., Li, C., Huang, T., & Li, C. (2014). Neural network for solving convex quadraticbilevel programming problems. Neural Networks, 51, 17–25.

He, X., Li, C., & Shu, Y. (2012). Bogdanov–Takens bifurcation in a single inertialneuron model with delay. Neurocomputing , 89, 193–201.

Huang, J., Shi, L., Yeo, E., Yi, K., & Zhao, R. (2012). Electrochemical metallizationresistive memory devices using ZnS–SiO2 as a solid electrolyte. Electron DeviceLetters, IEEE, 33, 98–100.

Jiang, A. Q., Wang, C., Jin, K. J., Liu, X. B., Scott, J. F., Hwang, C. S., et al. (2011).A resistive memory in semiconducting BiFeO3 thin-film capacitors. AdvancedMaterials, 23, 1277–1281.

Jo, S., Chang, T., Ebong, I., Bhadviya, B., Mazumder, P., & Lu, W. (2010). Nanoscalememristor device as synapse in neuromorphic systems. Nano Letters, 10,1297–1301.

Kim, S., Park, J., Jung, S., Lee, W., Woo, J., Cho, C., et al. (2011). Excellent resistiveswitching in nitrogen-doped Ge2Sb2Te5 devices for field-programmable gatearray configurations. Applied Physics Letters, 99, 192110.

Kim, I., Siddik, M., Shin, J., Biju, K. P., Jung, S., & Hwang, H. (2011). Low temperaturesolution-processed graphene oxide/Pr0.7Ca0.3MnO3 based resistive-memorydevice. Applied Physics Letters, 99, 042101.

Krzysteczko, P., Münchenberger, J., Schäfers, M., Reiss, G., & Thomas, A. (2012). Thememristive magnetic tunnel junction as a nanoscopic synapse-neuron system.Advanced Materials, 762–766.

Kwon, D. H., Kim, K. M., Jang, J. H., Jeon, J. M., Lee, M. H., Kim, G. H., et al. (2010).Atomic structure of conducting nanofilaments in TiO2 resistive switchingmemory. Nature Nanotechnology, 5, 148–153.

Lehtonen, E., & Laiho, M. (2010). CNN using memristors for neighborhoodconnections. In 12th international worshop on cellular nanoscale networks andtheir applications, Feb 3–5, Berkeley CA (pp. 1–4).

Li, H., Liao, X., Li, C., Huang, H., & Li, C. (2011). Edge detection of noisy images basedon cellular neural networks. Communications in Nonlinear Science andNumericalSimulation, 16, 3746–3759.

Li, Y., Zhong, Y., Xu, L., Zhang, J., Xu, X., Sun, H., et al. (2013). Ultrafast synaptic eventsin a chalcogenide memristor. Scientific Reports, 3(1619), 1–7.

Linn, E., Rosezin, R., Tappertzhofen, S., BÖttger, U., & Waser, R. (2012). Beyondvon Neumann-logic operations in passive crossbar arrays alongside memoryoperations. Nanotechnology, 23, 305305.

Liu, Q., & Wang, J. (2008). A one-layer recurrent neural network with adiscontinuous hard-limiting activation function for quadratic programming.IEEE Transactions on Neural Networks, 19(4), 558–570.

Liu, Q., &Wang, J. (2013). A one-layer projection neural network for nonsmooth op-timization subject to linear equalities and bound constraints. IEEE Transactionson Neural Networks and Learning Systems, 24(5), 812–824.

Luo, B., & Wu, H. N. (2012). Approximate optimal control design for nonlinear one-dimensional parabolic PDF systems using empirical eigenfunctions and neuralnetwork. IEEE Transactions on Systems, Man and Cybernetics, Part B (Cybernetics),42, 1538–1549.

Muenstermann, R., Menke, T., Dittmann, R., & Waser, R. (2010). Coexistence offilamentary and homogeneous resistive switching in Fe-doped SrTiO3 thin filmmemristive devices. Advanced Materials, 22, 4819–4822.

Pandian, R., Kooi, B. J., Oosthoek, J. L. M., Dool, P., Palasantzas, G., & Pauza, A. (2009).Polarity-dependent resistance switching in GeSbTe phase change thin films:the importance of excess Sb in filament formation. Applied Physics Letters, 95,252109.

Pandian, R., Kooi, B. J., Palasantzas, G., & De Hosson, J. T. M. (2007). Polarity-dependent reversible resistance switching in Ge–Sb–Te phase-change thinfilms. Applied Physics Letters, 91, 152103.

Peng, P., Xie, D., Yang, Y., Zhang, Y., Gao, X., Zhou, C., et al. (2012). Resistive switchingbehavior in diamond-like carbon films grown by pulsed laser deposition forresistance switching random access memory application. Journal of AppliedPhysics, 111, 084501.

Pershin, Y. V., & Ventra, M. D. (2010). Experimental demonstration of associativememory with memristive neural networks. Neural Networks, 23(7), 881–886.

Querlioz, D., Bichler, O., Dollfus, P., & Gamrat, C. (2013). Immunity to devicevariations in a spiking neural network with memristive nanodevices. IEEETransactions on Nanotechnology, 12(3), 288–295.

Rachmuth, G., & Poon, C. S. (2008). Transistor analogs of emergent iono-neuronaldynamics. Human Frontier Science Program Journal, 2, 156–166.

Shin, S., Kim, K., & Kang, S. (2012). Analysis of passive memristive devicesarray: data-dependent statistical model and self-adaptable sense resistance forRRAMs. Proceedings of the IEEE, 100(6), 2021–2032.

Smith, L. (2006). Handbook of nature-inspired and innovative computing: integratingclassical models with emerging technologies. (pp. 433–475). New York: Springer.

Snider, G. (2007). Self-organized computation with unreliable, memristivenanodevices. Nanotechnology, 18, 365202.

Snider, G. (2011). Instar and outstar learning with memristive nanodevices.Nanotechnology, 22, 015201.

Soni, R., Meuffels, P., Staikov, G., Weng, R., Kugeler, C., Petraru, A., et al. (2011).On the stochastic nature of resistive switching in Cu doped Ge0.3Se0.7 basedmemory devices. Journal of Applied Physics, 110, 054509.

Strukov, D. B., Snider, G. S., Stewart, D. R., & Wiliams, R. S. (2008). The missingmemristor found. Nature, 453, 80–83.

Sun, H. J., Hou, L. S., Wu, Y. Q., & Tang, X. D. (2009). Reversible resistance switchingeffect in amorphous Ge1Sb4Te7 thin films without phase transformation.Chinese Physics Letters, 26, 024203.

Wen, S., Zeng, Z., & Huang, T. (2013a). Global exponential synchronization ofmemristor-based recurrent neural networks with time-varying delays. NeuralNetworks, 48, 195–203.

Wen, S., Zeng, Z., & Huang, T. (2013b). Exponential adaptive lag synchronizationof memristive neural networks via fuzzy method and applications inpseudo random number generators. IEEE Transactions on Fuzzy Systems,http://dx.doi.org/10.1109/TFUZZ.2013.2294855.

Woo, J., Jung, S., Siddik, M., Cha, E., Sadaf, S. M., & Hwang, H. (2011). Effect ofinterfacial oxide layer on the switchinguniformity ofGe2Sb2Te5-based resistivechange memory. Applied Physics Letters, 99, 162109.

Wu, H., & Luo, B. (2012). Neural network based online simultaneous policyupdate algorithm for solving the HJI equation in nonlinear H∞ control. IEEETransactions on Neural Networks and Learning Systems, 23(12), 1884–1895.

Xia, Q., Robinett, W., Cumbie, M. W., Banerjee, N., Cardinali, T. J., Yang, J. J., et al.(2009). Memristor-CMOS hybrid integrated circuits for reconfigurable logic.Nano Letters, 9(10), 3640–3645.

Yan, Z., Guo, Y., Zhang, G., & Liu, J. (2011). High-performance programmable mem-ory devices based on Co-doped BaTiO3 . Advanced Materials, 23, 1351–1355.

Yang, J. J., Pickett, M. D., Li, X., Ohlberg, D. A. A., Stewart, D. R., & Williams, R. S.(2008). Memristive switching mechanism for metal/oxide/metal nanodevices.Nature Nanotechnology, 3, 429–433.

Yang, J. J., Zhang, M. X., Strachan, J. P., Miao, F., Pickett, M. D., Kelley, R. D., et al.(2010). High switching endurance in TaOx memristive devices. Applied PhysicsLetters, 97, 232102.

Yu, S.,Wu, Y., &Wong,H. S. (2011). Conductionmechanismof TiN/NfOX/Pt resistiveswitchingmemory: a trap-assisted-tunnelingmodel. Applied Physics Letters, 98,103514.