kỹ thuật số,dhbkhcm

© DHBK 2005 1/Chapter7

1

NỘI DUNG

1. Giới thiệu chung về hệ vi xử lý

2. Bộ vi xử lý Intel 8088/8086

3. Lập trình hợp ngữ cho 8086

4. Tổ chức vào ra dữ liệu

5. Ngắt và xử lý ngắt

6. Truy cập bộ nhớ trực tiếp DMA

7. Các bộ vi xử lý trên thực tế

CuuDuongThanCong.com https://fb.com/tailieudientucntt

http://cuuduongthancong.com?src=pdf

https://fb.com/tailieudientucntt


2

Chương 7: Các bộ vi xử lý trên thực tế

• General purpose microprocessors

Intel 80x86

Xu hướng phát triển

• Microcontrollers

Vi điều khiển của Motorola

Họ vi điều khiển 8051

Họ vi điều khiển AVR

PSOC


• Digital signal processors

Texas Instruments

Motorola

Philips






3



Intel 80x86






PSOC



Texas Instruments

Motorola

Philips






4

Intel 4004

• First microprocessor

(1971)

• 4-bit processor

• 2300 Transistors (P-

MOS), 10 mm

• 0.06 MIPS, 108 KHz, 640

bytes addressable

memory

• -15V power supply





5

Intel 8008

• First 8-bit processor (1972)

• Cost $500; at this time, a 4-

bit processor costed $50

• Complete system had 2

Kbyte RAM

• 200 KHz clock frequency, 10

mm, 3500 TOR, 0.06 MIPS,

16 Kbyte addressable

memory

• 18 pin package, multiplexed

address and data bus





6

Intel 8080

• Second gen. 8-bit

processor, introduced

in 1974

• 40 pin package,

NMOS, 500K

instructions/s, 6 mm, 2

MHz, ±5V & +12V

power supply, 6

KTOR, 0.64 MIPS

• 64 Kbyte address

space (“as large as

designers want”, EDN

1974)

• 10X the performance

of the 8008





7

Intel 8088

• 16-bit processor

• introduced in 1979

• 3 mm, 5 - 8 MHz, 29

KTOR, 0.33 a 0.66 MIPS,

1 Mbyte addressable

memory

• 10X the performance of

the 8008





8

Intel 8086

• Introduced: 1978

• Clock frequency: 8 - 10 MHz

16 bit integer CPU

address

data16

20





9

Intel 80286


• 1.5 mm, 134 KTOR, 0.9 to 2.6 MIPS


• 16MB addressable, 1GB virtual memory

• 3-6X the performance of the 8086

16 bit integer CPU

address

data16

24

MMU





10

Intel 80386sx


• 1 mm, 275 KTOR, 5 to 11 MIPS


• Software support and hardware protection for multitasking

32 bit integer CPU

address

data16

24

MMU





11

Intel 80386dx



• 4GB addressable memory, 64 TB virtual memory


32 bit integer CPU

address

data32

32

MMU





12

Intel 80486dx



• 1 mm, 1200 KTOR


• Support for parallel processing

• Cache required: external memory is not fast enough

address

data32

32

8 Kbyte cache 32 bit integer CPU

64 bit FPUMMU





13

Intel 80486sx


• 0.8 mm, 1.2 MTOR, 20 to 41 MIPS





address

data32

32


MMU





14

Intel 80486dx2


• Clock frequency: internal: 50 - 66 MHz, external: 25 - 33 MHz




address

data32

32


64 bit FPUMMU





15

Intel Pentium


• (.8 mm, 3.1 MTOR) up to (.35 mm, 4.5 MTOR incl. MMX)

• Clock frequency: internal: 60 - 166 MHz, external: 66 MHz

• Support for parallel processing: cache coherence protocol

• Super scalar ->5X the performance of the 33MHz Intel486 DX

address

data64

32

64 bit FPUStatic branch

prediction unit

32 bit integer

pipelined CPU

32 bit integer

pipelined CPU

MMU

8 Kbyte

program cache

8 Kbyte

data cache





16

Intel Pentium Pro

• Introduced: 1995, 0.35 mm, 3.3 V, 5.5 MTOR, 35W, 387 pin

• Clock frequency: 150 - 200 MHz Internal, 60 - >100 MHz External

• Super scalar (4 Instr./cycle), super pipelined (12 stages)

• Support for symmetrical multiprocessing (4 CPU)

• MCM: 256-1024 Kbyte L2 4-way set associative cache

Dynamic branch

prediction unit

MMU

Instruction

dispatch unit

32 bit integer

pipelined CPU

64 bit

pipelined FPU

Address

generation unit

32 bit integer

pipelined CPU

32 bit integer

pipelined CPU address

data64+ECC

36

8 Kbyte L1

program cache

8 Kbyte L1

data cache

to L2 cache





17

Intel Pentium II

• Introduced: 1997, 0.25 mm, 2.0 V, 9 MTOR, 43 W, 242 pin

• Clock frequency: 200 - 550 MHz Internal, 100 - 225 MHz L2 cache, 66 - 100 MHz External



• Single Edge Contact Cartridge with Thermal Sensor: 256-1024 Kbyte L2 4-way set associative cache

Dynamic branch

prediction unit

MMU

Instruction

dispatch unit

64 bit

pipelined FPU

64 bit

pipelined FPU

Address

generation unit

32 bit integer

pipelined CPU

32 bit integer


data64+ECC

36

16 Kbyte L1

program cache

16 Kbyte L1

data cache

to L2 cacheECC





18

Intel Pentium III

• Introduced: 1999, 0.18 mm , 6LM, 1.8 V, 28 MTOR, 370 pin

• Clock frequency: 450 - 1130 MHz Internal, 100-133 MHz External



Dynamic branch

prediction unit

MMU

Instruction

dispatch unit

64 bit

pipelined FPU

64 bit

pipelined FPU

Address

generation unit

32 bit integer

pipelined CPU

32 bit integer


data64+ECC

36

16 Kbyte L1

data cache

256 Kbyte L2 unified

cache

16 Kbyte L1

program cache





19

Intel Pentium IV

• Introduced: 2002, 0.13 mm or 90nm , 1.8 V, 55 MTOR

• Clock frequency: 1,4 to 3.8 GHz Internal, 400 to 800 MHz External


• Newer versions: Hyper threading

Dynamic branch

prediction unit

MMU

Instruction

dispatch unit

64 bit

pipelined FPU

64 bit

pipelined FPU

Address

generation unit

32 bit integer

pipelined CPU

32 bit integer


data64+ECC

36

16 Kbyte L1

data cache

256/512/1024 Kbyte L2

16 Kbyte L1

program cache





20

IA-64 (Itanium)

• Design started in 1994; first samples on the market in 2001

• 64-bit address space (4x109 Gbyte; we will never need that

much…)

• 256 64-bit integer and 128 82-bit floating point registers; 64

branch target registers; 64 1-bit predicate registers

• 41 bit instruction word length

• 10-stage pipeline

• separate L1 data and program, 96 Kbyte L2 unified on-chip,

4 Mbyte L3 unified off-chip





21



Intel 80x86






PSOC



Texas Instruments

Motorola

Philips






22

Trends for general purpose processors• Higher clock frequencies: 4.7 -> 30 GHz

• Faster memory: 120 ns -> 50 ns not proportional to clock frequency increase => use of caches and

special DRAM memories (e.g. SDRAM)

• Limited by power dissipation => decreasing power supply voltage

• Parallel processing

• Memory with processor instead of processor with memory





23

The future: general characteristics

R o a d m a p 2 0 0 1 2 0 0 2 2 0 0 4 2 0 0 7 2 0 1 0 2 0 1 3 2 0 1 6

R o a d m a p 1 9 9 8 1 9 9 7 1 9 9 9 2 0 0 2 2 0 0 5 2 0 0 8 2 0 1 1 2 0 1 4

R o a d m a p 1 9 9 5 1 9 9 5 1 9 9 8 2 0 0 1 2 0 0 4 2 0 0 7 2 0 1 0

L in e w id t h (n m ) 3 5 0 2 5 0 1 8 0 1 3 0 9 0 6 5 4 5 3 2 2 2

N u m b e r o f

m a s k s

1 8 2 2 2 2 -

2 4

2 4 2 4 -

2 6

2 6 -

2 8

2 8 2 9 -

3 0

W a fe r s iz e

(m m )

2 0 0 2 0 0 3 0 0 3 0 0 3 0 0 3 0 0

N u m b e r o f

w ir in g le v e ls

4 -5 6 6 -7 7 7 -8 8 -9 9 1 0

P o w e r s u p p ly

V : d e s k t o p

3 .3 1 .8 -

2 .5

1 .5 -

1 .8

1 .1 -

1 .5

1 .0 -

1 .2

0 .7 -

0 .9

0 .6 0 .5 0 .4

M a x . p o w e r

d is s ip a t io n /c h ip

8 0 7 0 9 0 1 3 0 1 6 0 1 7 0 1 7 5 1 8 3

Will 22 nm be the end of the scaling race for CMOS?

Some believe10 nm will be the end…

…thereafter, semiconductor drive will be scattered

(MEMS, sensors, magnetic, optic, polymer, bio, …)

Depending on application domain: besides and beyond

siliconCuuDuongThanCong.com https://fb.com/tailieudientucntt




24

Besides and beyond silicon (e.g. polymer

electronics)





25

Besides and beyond silicon: applied to future

ambient intelligent environments

© Emile Aarts, HomeLab, PhilipsCuuDuongThanCong.com https://fb.com/tailieudientucntt




26

Besides and beyond silicon: applied to future

ambient intelligent environments





27

Besides and beyond silicon: applied to ambient

intelligent HomeLab (2002)





28

R o a d m a p 2 0 0 1 2 0 0 1 2 0 0 4 2 0 0 7 2 0 1 2 2 0 1 6

R o a d m a p 1 9 9 8 1 9 9 7 1 9 9 9 2 0 0 2 2 0 0 5 2 0 0 8 2 0 1 1 2 0 1 4

R o a d m a p 1 9 9 5 1 9 9 5 1 9 9 8 2 0 0 1 2 0 0 4 2 0 0 7 2 0 1 0

N u m b e r o f T O R 6 M 1 1 M 2 1 M 7 6 M 2 0 0 M 5 2 0 M 1 .4 G 3 .6 G

O n c h ip lo c a l

c lo c k f r e q . (M H z )

7 5 0 1 2 5 0 2 1 0 0 3 5 0 0 6 0 0 0 1 0 0 0 0 1 6 9 0 3

O n c h ip g lo b a l

c lo c k f r e q . (M H z )

3 0 0 3 7 5 1 2 0 0 1 6 0 0 2 0 0 0 2 5 0 0 3 0 0 0 3 6 7 4

C h ip s iz e (m m2

) 2 5 0 3 0 0 3 4 0 4 3 0 5 2 0 6 2 0 7 5 0 9 0 1

The future: high performance (mP)

• CTO Intel says in 2001

2005

425 MTOR

100 nm

1600 mm2

30 GHz on chip

without specific measures like individual transistor power-down: 3000

W, i.e. 3000 amps...

1.8 GTOR in 2010





29

The future: high performance (mP)





30

Processor performance

1980 1985 1990 1995 2000 2005

Time

Performance

1

10

100

1K

10K

100K

1M

55%/year

Exponential growth for 3 decades!

This is called „Moore‟s law‟: number of transistors

doubles every 18 months

(Gordon Moore, founder Intel Corp.)





31

Processor performance

• Smaller line size

More transistors => parallelism

1983: 1 instruction per 4 clock cycles

2002: 8 instructions per clock cycle

Smaller capacitors => faster

1983: 4 MHz

2002: 2800 MHz

Speed-up: 25000

• Enables new applications

UMTS with large rolled-up OLED screen enabling web

downloadable services (e.g. virtual meetings)

• Do we find applications that are demanding enough for

next decade‟s processors?





32

The future: DRAM

Roadmap 2001 2003 2007 2011 2016 ? ?

Roadmap 1998 1997 1999 2002 2005 2008 2011 2014

Roadmap 1995 1995 1998 2001 2004 2007 2010

Number of bits

per chip

64M 256

M

1G 4G 16G 64G 256

G

1T

Chip size

(mm2

)

190 280 400 560 790 1120 1580 2240





33

Memory density

1980 1985 1990 1995 2000 2005

Time

Performance

1

10

100

1K

10K

100K

1M

55%/year

Processor

10%/year

Memory

Gap





34

Memory density

• Skills: center of gravity

USA: processors (Intel, Motorola, TI, …)

Japan: memory (NEC, Toshiba, …)

Future: IC = processor + memory

Where???

• Memory density grows faster than needs

1983: 512 Kbyte @ 64 Kbit/chip = 64 chips/PC

2001: 256 Mbyte @ 512 Mbit/chip = 4 chips/PC

Compensated if you sell at least 16 times more PCs…

… or if you find new applications (UMTS, car,…)

2010: 4 Gbyte @ 64 Gbit/chip = 0.5 chip/PC

No need for such a large memory chip…

… unless you find new applications (3D video…)





35

Power consumption

Power (W/cm2)

1

10

100

1K

1.5m Line

width

1m 0.7m 0.5m 0.35m 0.25m 0.18m 0.13m 0.1m

386

486

PP Pro

P II P III

P 4Hot plate

Nuclear reactor

Processor architecture design driven by memory bottleneck

& power problem!

Nevertheless, „cooling tower‟ is necessary!

© Fred Pollack, Keynote at Micro99CuuDuongThanCong.com https://fb.com/tailieudientucntt




36

Power consumption

Cooling “tower”





37

Power consumption

• Let us do a calculation: How long could a GSM using a Pentium 3 (hardly powerful

enough…) last on a single battery charge?

Capacity of a battery:600 mAh @ 4V = 2400 mWh

Power consumption Pentium 3: 45 W

One charge lasts for … 3 minutes!!!

• Let us turn the computation upside down:We want a GSM to last for 240 hours on a single charge. How much

power may be consumed by the processor?

Capacity of a battery:600 mAh @ 4V = 2400 mWh

Power consumption processor: 10 mW

Possible via specialization to the application:dedicated hardware…





38

Summary on technological trends

• Technologically speaking, we can have the same

exponential evolution for another decade

• This gives us at least 4 decades of exponential evolution,

never seen in history

• End-user price stayed the same or even decreased

Since 30 years, the price for a brand new processor is 1000 USD

• So far for the good news…





39

Design issues

1980 1985 1990 1995 2000 2005

Time

Performance

1

10

100

1K

10K

100K

1M

55%/year

Design

complexity

10%/year

Design

productivity

Gap

Unfortunately, Gordon Moore‟s law is also valid for the

design complexity, which doubles every 18 months…

… and worse, design productivity doubles only every

10 years





40

Design issues

• We can build exponentially complex circuits, but we cannot

design them

Design of Pentium 4: 8 years, during last 2 years with a team of

1000 persons

Who can afford this???





41



Intel 80x86






PSOC



Texas Instruments

Motorola

Philips






42

Giới thiệu về vi điều khiển

• Vi điều khiển = CPU + Bộ nhớ + các khối ghép nối ngoại vi

+ các khối chức năng

EEPROM

RAM

ADC/DAC

Timer

Bộ tạo xung nhịp

PWM

UART

USB

...





43

Programmable

chip selects

Interrupt logic

2 Timers

Serial asynch.

Buffered I/O

1

12

7

Motorola MC68331

• Clock frequency: > 16 MHz

• MC683xx: modular microcontroller unit: MC68000 core plus customized peripherals

FT unit: watchdog

clock&bus monitor

32 bit

integer CPU

address

data16

24





44

Motorola MC68332



FT unit: watchdog

clock&bus monitor

32 bit

integer CPU

Programmable

chip selects

Interrupt logic

Timer PU

Serial asynch.

Buffered I/O

1

12

7

Parallel I/O 48

address

data16

24

2 Kbyte RAM





45

Motorola MC68340



FT unit: watchdog

clock&bus monitor

32 bit

integer CPU

Programmable

chip selects

Interrupt logic

2 Timers

Serial asynch.

I/O

2

4

7

Parallel I/O 16

address

data16

32

2 channel

DMA controller





46

Motorola MC68F333

• 68020 processor

• 4 Kbyte SRAM, 64 Kbyte on chip flash EEPROM

• 8 channel 10-bit ADC, 16 channel 16-bit timer

• several interfaces

• Introduced in 1994CuuDuongThanCong.com https://fb.com/tailieudientucntt




47

Motorola MC68HC16

• 16-bit microprocessor

• Introduced in 1994

www.freescale.com





48



Intel 80x86






PSOC



Texas Instruments

Motorola

Philips






49

8051

• CISC 8bit processor

• Max clock 12MHz, 1 instruction cycle= 1us

• 16bit addressable memory: SROM, SRAM

• Internal RAM 128byte

• Special Function Registers (SFR)

• 2 16bit-Timers/Counters

• 5 interrupt source

• UART

• 4x8 GPIO





50

895x

• 80C51: ROMless

• 89C5x: internal ROM, Havard archtecture

• 89C52:

8K Flash ROM for programming, 3 level of memory lock

256 byte internal RAM

3 16bit-Timer/counter

4x8 GPIO

• 89C55:

20K Flash ROM

• 89S52= 89C52 + ISP

• 89S8252 = 89S52 + 2K data flash ROM

• MSC 51 family: popular, Developed by many manufacturers





51

Atmel MSC51

• ATWebSEG-32

Ethernet Interface

• C251 Architecture

8/16 bit Micro controller

• AT89C51CC03

CAN controller, Power fail detect

• AT83EB5114

Dedicated to lighting control applications

Onchip oscillator

Analog functions: 10-bit, 6 channels A/D converter and 2 PWM units.

• AT89C51SND2C : Single-Chip MP3-Player for mobile phone market.

MP3 Decoder (MPEG1&2Layer-3), 64 Kbytes Flash.

MultiMediaCard™, DataFlash®, SmartMedia™, CompactFlash™

IDE Interfaces. UART, SPI and Two-wire Interface (TWI), USB 1.1.

Audio Stereo DAC and 500mW Power Amplifier.


http://www.atmel.com/dyn/products/product_card.asp?part_id=3186






52

Philips MSC51

• 8xC592

16K ROM, 512 RAM

UART,CAN bus controller

8×10-bit A/D, PWM outputs,

• P89LPC938

8K ROM, 768B RAM, 512B EEPROM

PWM, Watchdog, ADC 8bit

UART, I2C, API

• eXtended Architecture, XAC37

16bit processor, 32 MHz

32KB ROM, 1KB RAM

UART, SPI, CAN 2.0

• eXtended Architecture, XAH4

4 UARTs, DRAM controller


http://www.semiconductors.philips.com/pip/P87C592EFA.html



http://www.semiconductors.philips.com/pip/P89LPC938FHN.html




http://www.semiconductors.philips.com/pip/XA-C3.html

http://www.semiconductors.philips.com/pip/XA-C3.html

http://www.semiconductors.philips.com/pip/XA-H4.html

http://www.semiconductors.philips.com/pip/XA-H4.html




53



Intel 80x86






PSOC



Texas Instruments

Motorola

Philips






54

AVR

• High performance RISC architecture, single cycle execution, 20 MIPS at 20Mhz.

Harvard architecture

32 general purpose registers

• Low power consumption = Long battery life time 1.8 - 5.5 volts operation

Variety of operation modes, fast wake-up from low-power modes

Software controlled operation frequency

• High code density = Ideal for High-level Languages Architecture designed for C, C-like addressing modes

16- and 32-bit arithmetic support

Linear address maps

• Outstanding memory technology Self-programming Flash

EEPROM for parameter storage

SRAMCuuDuongThanCong.com https://fb.com/tailieudientucntt




55

Atmel AVR

• Automotive AVR: ATmega168 Automotive

16KB Flash Program Memory, 512B SRAM, 256B EEPROM

8 Channel 10-bit A/D-converter

DebugWIRE On-chip Debug System

16 MIPS throughput at 16 MHz.

• CAN AVR AT90CAN128

CAN Controller. V2.0A and V2.0B standard compliant

Perfectly suited for Industrial and Automotive applications

• megaAVR ATmega128

128KB ROM, 4KB SRAM, 4KB EEPROM

8 Channel 10-bit A/D-converter

JTAG interface for on-chip-debug

Up to 16 MIPS throughput at 16 MHz

2.7 - 5.5 Volt operation.

• USB AVR AT90USB1286 CuuDuongThanCong.com https://fb.com/tailieudientucntt








56



Intel 80x86






PSOC



Texas Instruments

Motorola

Philips






57

PSoC

• Mixed-Signal Controllers 8bit MCU core + Digital blocks + Analog blocks

Low voltage, low power: 1.5V-5.5V

• MCU core CISC, Clock 3-48Mhz, Onchip oscillator

4-20KB Flash (program + storage) , 128-2K SRAM

Debugger core

• Digital blocks 8-32bit Counters/ Timers, PWM

Communication: I2C inteface, UART

Logic: Buffer , NOT gates, Multiplexer

• Analog blocks DAC 6-12 bit, ADC 6-12 bit

Amplifiers: Power Amp., Dif. Amp.,

Analog filters

DTMF generator, Analog multiplexerCuuDuongThanCong.com https://fb.com/tailieudientucntt




58



Intel 80x86






PSOC



Texas Instruments

Motorola

Philips






59

Trends for microcontrollers

• Standard CPU core surrounded by peripherals taken from

a vast library

• Single architecture line is whole family

different memory & on-chip peripherals

for embedded applications

Deterministic behavior

no caches, no virtual memory, but on-chip RAM

no out-of-order execution

delayed branch prediction





60

Trends for microcontrollers

• Word length as small as possible

4 bit: 2%

8 bit: 36%

16 bit: 25%

32 bit: 34%

64 bit: 3%

• Not pushing the limits of performance for cost reasons





61



Intel 80x86






PSOC



Texas Instruments

Motorola

Philips






62

Texas Instruments TMS320C20x

Low end consumer Fixed Point

• Series continued; typical app.: Digital camera, feature-phones, disk drives,

Point-of-Sales Terminal

• 40 MHz, 3.3-5V, 3LM

• Available as core

Selection of

peripherals:

serial comm.,

timers,...

fixed MAC

16x16+32->32

PROM

Dual access

data RAM

address

data16

18

address

data16

16

I/OLoop controller





63


Low end consumer Fixed Point

• Series continued; typical app.: electrical motor control

• 50 MHz, 5V

Selection of

peripherals:

serial comm.,

timers,...

fixed MAC

16x16+32->32

PROM

Dual access

data RAM

address

data16

16

Loop controller

8 output PWM

8 channel A/D

CAN bus

controller

watchdog





64


Floating Point

• Series discontinued; typical app.: speech, audio

• 60 MHz, 3.3-5V, 144 pin

• Super scalar

Loop controller

Selection of

peripherals:

serial comm.,

timers, DMA, ...

32 bit

floating add

32 bit

floating multiply

PRAM

XRAM

YRAMaddress

data32

24

address

data32

24

I/O

ACU

ACU





65


Floating Point Message Passing

• Series discontinued; typical app.: prototyping, radar

• 60 MHz, 5V, 325 pin

• Super scalar; message passing multiprocessor

Loop controller

Serial link,

timers

32 bit

floating add

32 bit

floating multiply

PRAM

4KByte XRAM

4KByte YRAM

20 MB/s

8

12 channel

DMA controller

address

data32

32

address

data32

32

ACU

ACU





66

Texas Instruments TMS320C54xx

High end consumer Fixed Point

• Series continued; typical app.: GSM, set-top box, audio

• 1.8-5V, max. 160 MHz, 144 pin, .15mm (1999), 0.32mW/MIPS for the core

• Specialized on-chip unit: will occur more often in future

• e.g. C5420: dual core + 2x100 MW on-chip SRAM

e.g. C5402: 5$ for 100 MIPS

Loop controller

Buffered serial

links, timers, ...

6 channel

DMA controller

Fixed ALU

32+32->40

Fixed Add

32+32->40

Fixed multiply

17x17->34

Viterbi

PROM

Dual access

XRAM

YRAMaddress

data32

17

address

data16

16ACU

ACU

I/O





67

Texas Instruments TMS320C5510

High end consumer Fixed Point

• Series continued; typical app.: UMTS handheld

• 1.6V, 200 MHz, .15mm (2000), 400 MIPS,0.05mW/MIPS (core), power

management per unit and per cycle

• Specialized on-chip unit: will occur more often in future

Power Mgment

Buffered serial

links, timers, ...

6 channel

DMA controller

Fixed ALU

32+32->40

Fixed Add

32+32->40

Fixed multiply

17x17->34

Viterbi

PROM

32 KByte

Dual access

XRAM (256 Kbyte)

YRAM

(64 Kbyte)

address

data32

24

address

data16

16ACU

ACU

I/O

Fixed multiply

17x17->34

P-cache

24 KByte





68


Fixed Point Video

• Series discontinued; typical app.: video phone, video conferencing, multimedia workstations

• Introduced: 1995, 50 MHz, 305 pin

• Multiprocessor-on-a-chip; sub-word SIMD for each DSP

DSP processor 1

DSP processor 2

DSP processor 3

DSP processor 4

General purpose

RISC processor

Transfer

controller

data

address32

64

Video controller

2 Kbyte RAM1

2 Kbyte RAM16

2 Kbyte I-cache1

2 Kbyte I-cache4

4 Kbyte D-cache

2 KByte RAM

4 KByte I-cache

X-

bar





69


High end Fixed Point

• Series continued; typical app.: modems, multimedia

• 1997, 0.25 mm, 5ML, 352 pin, 200 MHz, 2.5V, 1.9W, $85

• Super scalar (8 Instr./cycle), 1600 MIPS

• VLIW: 256 bit instruction word

fixed MUL

16x16->32

fixed MUL

16x16->32

fixed ALU

32+32->40

fixed ALU

32+32->40

fixed ALU/branch

32+32->40

fixed ALU/branch

32+32->40

integer ACU

32+32

integer ACU

32+32

16KByte D-SRAM

16KByte D-SRAM

16KByte D-SRAM

16KByte D-SRAM

64KByte

P-SRAM/cache

JTAG / clock pump

4 channel DMA

2 Serial ports

2 Timers

Ext. memory

interface

data

address17

16

Host interface

data

address23

32

External memory





70



• Series continued; typical app.: modems, multimedia

• 1999, 0.18 mm, 5ML, 352 pin, 250 MHz, 1.8V, 1.9W, $130

• Super scalar (8 Instr./cycle), 2000 MIPS, scales well till 700 MHz (6000 MIPS)

• Optimum choice when all data fits in on-chip memory

fixed MUL

16x16->32

fixed MUL

16x16->32

fixed ALU

32+32->40

fixed ALU

32+32->40

fixed ALU/branch

32+32->40

fixed ALU/branch

32+32->40

integer ACU

32+32

integer ACU

32+32

2x16KByte D-RAM

(Shadow load)

2x16KByte D-RAM

(Shadow load)

2x16KByte D-RAM

(Shadow load)

2x16KByte D-RAM

(Shadow load)

2x128KB P-RAM

(Shadow load)

JTAG / clock pump

4 channel DMA

2 Serial ports

2 Timers

Ext. memory

interface

data

address17?

32

Expansion bus

data

address23?

32

External memory





71



• Series continued; typical app.: base stations

• 2000, 0.15 mm, 5ML, 18 mm2 package size, 300 MHz, 1.5V, 1.5W

• Super scalar (8 Instr./cycle), 2400 MIPS

• Optimum choice when all data fits in on-chip memory

fixed MUL

16x16->32

fixed MUL

16x16->32

fixed ALU

32+32->40

fixed ALU

32+32->40

fixed ALU/branch

32+32->40

fixed ALU/branch

32+32->40

integer ACU

32+32

integer ACU

32+32

2x64KByte D-RAM

(Shadow load)

2x64KByte D-RAM

(Shadow load)

2x64KByte D-RAM

(Shadow load)

2x64KByte D-RAM

(Shadow load)

256KByte P-RAM

128KB P-cache/RAM

JTAG / clock pump

4 channel DMA

2 Serial ports

2 Timers

Ext. memory

interface

data

address17?

32

Expansion bus

data

address23?

32

External memory





72



• Series continued; typical app.: modems, multimedia• 1999, 0.18 mm, 5ML, 256 pin, 150 MHz, 1.8V, 1.5W, $25• VLIW, 1.2 GIPS; cheap (25$ in „99, 5$ in „01)• Optimum for random access to large memory space

• 80% of performance of C6x with infinite on-chip memory

fixed MUL

16x16->32

fixed MUL

16x16->32

fixed ALU

32+32->40

fixed ALU

32+32->40

fixed ALU/branch

32+32->40

fixed ALU/branch

32+32->40

integer ACU

32+32

integer ACU

32+32

4KByte L1 Dcache

(2 way set assoc.)

4KByte L1 Pcache

(2 way set assoc.)

4x16KByte L2

cache (direct map)

JTAG / clock pump

16 channel DMA

2 Serial ports

2 Timers

Ext. memory

interface

data

address17

16

Host port

data

address30

32

External memory





73

Texas Instruments TMS320C6416 High end

Fixed Point

• Samples June 2001, 0.12 mm, 6 LM, 532 pin, 400 MHz-600 MHz, 1.2V, starts at 95$ in volume

• Super scalar (8 Instr./cycle), 3200-4800 MIPS

• Sub-word (8bit or 16bit) parallelism

• Specialized instr.: Galois Field Mult, bit manipulation

fixed MUL

16x16->32

fixed MUL

16x16->32

fixed ALU

32+32->40

fixed ALU

32+32->40

fixed ALU/branch

32+32->40

fixed ALU/branch

32+32->40

integer ACU

32+32

integer ACU

32+32

JTAG / clock pump

64 channel DMA

3 Serial ports

3 Timers

16 Kbyte L1P

direct mapped

16 Kbyte L1D

2way dual access

1 Mbyte RAM/L2

4way

Dual EMIF & HPI &

PCI & Utopia

data

address?

32

HPI

data

address30

64

External memory

data

address30

16

Viterbi decoder

accelerator

Turbo decoder

accelerator





74


High end Floating Point

• Series continued; typical app.: video compression

• Introduced: 1998, 0.18 mm, 5ML, 352 pin, 167 MHz, 1.8V

• Super scalar (8 Instr./cycle); VLIW; 1 GFLOP

• Foreseen for „00: 50$ (cf. C6211) & 3 GFLOP (cf. C6202)

Fixed/Float MUL

32x32/64x64

Fixed/Float MUL

32x32/64x64

Fixed/Float ALU

32+32/64+64

Fixed/Float ALU

32+32/64+64

Fixed ALU/Branch

Float 1/x & x

Fixed ALU/Branch

Float 1/x & x

integer ACU

32+32

integer ACU

32+32

16KByte D-SRAM

16KByte D-SRAM

16KByte D-SRAM

16KByte D-SRAM

64KByte

P-SRAM/cache

JTAG / clock pump

4 channel DMA

Serial interface

2 Timers

Ext. memory

interface

data

address17

16

Host interface

data

address23

32

External memory





75


High end Floating Point

• Series continued; typical app.: video compression• 2000, 0.18 mm, 5ML, 256 pin, 100 MHz, 1.8V, 2W, $20• VLIW, 600 MFlops• Optimum for random access to large memory space

• 80% of performance of C6x with infinite on-chip memory

Fixed/Float MUL

32x32/64x64

Fixed/Float MUL

32x32/64x64

Fixed/Float ALU

32+32/64+64

Fixed/Float ALU

32+32/64+64

Fixed ALU/Branch

Float 1/x & x

Fixed ALU/Branch

Float 1/x & x

integer ACU

32+32

integer ACU

32+32

JTAG / clock pump

4 channel DMA

Serial interface

2 Timers

Ext. memory

interface

data

address17

16

Host interface

data

address23

32

External memory4KByte L1 Dcache

(2 way set assoc.)

4KByte L1 Pcache

(2 way set assoc.)

4x16KByte L2

cache (direct map)





76

Texas Instruments

TMS320C541 (1995)





77

Texas Instruments

TMS320C545 (1995)





78

Texas Instruments

TMS320C80 (1994)





79



Intel 80x86






PSOC



Texas Instruments

Motorola

Philips






80

Motorola MC56xxx

Audio Fixed Point

• 24 bit for audio: 16 bit data + overflow

16 or 24 bit

integer CPU

Loop controller Selection of

peripherals:

ADC, DAC, comm.,

timers, PIO, ...

ACU

PRAM

XRAM

YRAMaddress

data24

18

ACU





81

Motorola MC56002





82

Motorola MC56166





83



Intel 80x86






PSOC



Texas Instruments

Motorola

Philips






84

Philips VSP-1

Fixed Point Video

• 12 bit for video: 8 bit data + overflow

• Clock Frequency: 27 MHz

• 1 instruction per sample period for HDTV,2 instructions per sample period for TV

12 bit

integer ALU

12 bit

integer ALU

512x12 bit

Memory element

512x12 bit

Memory element

12 bit

integer ALU10x18 cross-bar

12

12

10





85

Philips VSP-1

Fixed Point Video

ALU ALU ALU ME ME

Outputs

Inputs





86

Philips VSP-1

Fixed Point Video

ALUMemory

Element

Output

FIFOs• 206K Transistors

• 1.1W dissipation

• 27 MHz clock

• 176 pin

• Introduced in 1991





87

Philips VSP-2

Fixed Point Video

• 12 bit for video: 8 bit data + overflow

• Clock Frequency: 54 MHz

• 2 instructions per sample period for HDTV,4 instructions per sample period for TV

22x50 cross-bar22

12

12

12 bit

integer ALU1

12 bit

integer ALU2

512x12 bit

Memory element1

512x12 bit

Memory element2

12 bit

integer ALU12

512x12 bit

Memory element4





88

Philips VSP-2

Fixed Point Video

• 1.15 M Transistors

• 5W dissipation

• 54 MHz clock frequency

• 208 pin

• Introduced in 1994CuuDuongThanCong.com https://fb.com/tailieudientucntt




89

Sony Graphics Engine

• Playstation 3

Status: prototype in 2001

287.5 MTOR

256 Mbit on-chip embedded DRAM

2000-bit wide internal bus

462 mm2

180 nm CMOS





90



Intel 80x86






PSOC



Texas Instruments

Motorola

Philips






91

Trends for DSP processors

• No new generations that replace old generations, but

multiple co-existing architecture lines

• Word length application dependent

Automotive: 16-bit fixed point (e.g. C2x)

Speech: 32-bit floating point (e.g. C30)

Audio: 24-bit fixed point (e.g. MC56K)

Telecommunications: 16-32 bit fixed point (e.g. C5x, C6x)

Video: 12-32 bit fixed point (e.g. C8x)

• Single architecture line is whole family

different memory & on-chip peripherals

for embedded applications (cf. microcontrollers)





92

Trends for DSP processors

• Deterministic behavior

no caches, no virtual memory, but on-chip RAM banks

no out-of-order execution

delayed branch prediction

• Increasing address space: 12 -> 32

• Multiple functions on single chip: CPU, FPU, multiple RAM

banks, ACUs, loop controller, ADC, DAC, PWM, serial

interfaces, …

• Often provisions for parallel processing





93

Kết thúc

• Kết quả ?

Khái niệm, xu hướng phát triển

Lập trình Asemblers

Thiết kế hệ vi xử lý

• Tương lai

Kỹ sư lập trình hệ thống

Kỹ sư thiết kế

• Thi




kỹ thuật số,dhbkhcm

Documents