(invited) material engineering for 7nm finfets

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Material Engineering

for 7nm FinFETs

Victor Moroz, Joanne Huang,

Munkang Choi, and Lee Smith

May 13, 2014 ECS, Orlando, Florida

Invited


Outline


Expected Design Rules

Node Gate

pitch L

Spa-

cer

Fin

width

Fin

height Fin pitch

Contact

size EOT

10 63 20 11 8 32 34 21 0.85

7 44 15 7 6 30 24 15 0.8

All sizes are in nm


Si channel SiGe channel Ge channel

NMOS

+1.5 GPa

PMOS

-1.5 GPa

7nm Stress Engineering: SRB + S/D Epi

Stress analysis in S-Process

Si Si

Si Ge

Ge

25% Ge

25% Ge

50% Ge

50% Ge

75% Ge

75% Ge

50%

Ge

50%

Ge

15%

Ge

85%

Ge

70%

Ge

30%

Ge

Ge


Ballistic Transport Evolution

• Ballistic transport is

currently ~64%

• Is expected to rise to

~84% at 7nm node

• Even higher for Ge and

InGaAs

• Therefore, ballistic

transport approximation

is reasonable for 7nm

node

Calculated in Sentaurus Monte Carlo

14nm

5nm technology node

10nm

7nm

Si NMOS FinFET with 6nm wide fin

0.85

0.77

0.70

0.64

0.53

0.32

0.11

0.90

0.84

0.77

0.71

0.61

0.41

0.16

0.0

0.2

0.4

0.6

0.8

1.0

10 100

Ball

isti

c R

ati

o

Channel Length, nm

Relaxed

2 GPa


Modeling Flow Chart

7nm NMOS FinFET

For given fin width & material composition extract Eg and mr

For given Eg & mr ad-just WF to get mini-mum IOFF at Vg=0

For given WF calculate ballistic ION

Eg, mr WF

Pros Cons

Good for fast material screening Ignores scattering (<16% effect)

Includes sub-threshold electrostatics,

BTBT, & GIDL Ignores alloy scattering (<3% effect)

Includes narrow fin band structure Simplified Rsd treatment (75 Ohm*um)

Schrodinger quantization Simplified stress handling (uniform)

S-Band S-Band S-Device


Reasons to Look Beyond Silicon

S-Band

Si

Ge

InGaAs

D1, D2 (73%) D3 (27%)

L1 (21%) L3 (21%) L2, L4 (58%)

G (68%)

Increasing Valley Occupancy

Good Transport

Mass has High

Occupancy

Good Transport

Mass has Low

Occupancy

Good Transport

Mass has High

Occupancy


Outline


Stress Free SiGe: IdVg Curves

3D analysis in S-Device

• For each Ge fraction

Gate WF is adjusted

to place min Ioff at

Vgs = 0

• Strong changes in

SS are observed

• Vdd = 0.7 V in this

project

• ~250 mV difference

between Si and Ge

Vt

• BTBT model

calibrated by IMEC

Dra

in c

urr

en

t, A

/um

Gate bias, V

Ge

Si

Higher Ge %


Off-State and On-State Currents

Ioff: 3D S-Device; Ion: S-Band

1

10

100

1000

0 0.2 0.4 0.6 0.8 1

Min

imu

m I

off

, p

A/u

m

Germanium mole fraction

0

100

200

300

400

500

600

0 0.2 0.4 0.6 0.8 1

Co

rre

sp

on

din

g I

on

, u

A/u

m


BTBT follows Eg

Current collapse!

Why ?!


Physics Behind Current Collapse

7nm NMOS FinFET

0

0.2

0.4

0.6

0.8

1

1.2

0 0.2 0.4 0.6 0.8 1

Ban

dg

ap

& e

ffe

cti

ve

ma

ss


70

80

90

100

110

10

11

12

13

14

15

16

17

0 0.2 0.4 0.6 0.8 1

Die

lec

tric

Co

ns

tan

t


Su

bth

res

ho

ld s

lop

e, m

V/d

ec

Eg

mr

BTBT leakage follows Eg and mr

On-state current at high Ge % suffers from

e that degrades sub-threshold slope

X L


0%

20%

40%

60%

80%

100%

0 0.2 0.4 0.6 0.8 1

Va

lle

y o

cc

up

an

cy %


Delta & Lambda Valley Population

S-Band

• Here, Vgs = 0.7 V and gate WF is adjusted to have min Ioff at Vgs = 0

• There are too few electrons at high Ge mole fractions for this gate overdrive

0.0E+00

5.0E+11

1.0E+12

1.5E+12

2.0E+12

0 0.2 0.4 0.6 0.8 1

Nin

v (

1/c

m2

) Germanium mole fraction

X L Relative

Absolute X

L


Ion @Minimum Ioff: SiGe


1

10

100

1000

10000

1 10 100 1000 10000

Min

imu

m I

off

, p

A/u

m

Corresponding Ion, uA/um

SiGe no stress

SiGe 2 GPa

SP

LP

Si

Ge

SiGe with

90% Ge

3D

S-D

evic

e

S-Band


Stress Free SiGe: Ion @Fixed Ioff

7nm NMOS FinFET

524 508

263

902 926

653

1,009

1,427 1,480

1,369

2,055

0

500

1000

1500

2000

2500

3000

0 0.2 0.4 0.6 0.8 1

Ion

, u

A/u

m


SiGe LP SiGe SP SiGe HP

HP: 100 nA/um

SP: 1 nA/um

LP: 50 pA/um


Stress Free SiGe

7nm NMOS FinFET

524 508

263

902 926

653

1,009

1,427 1,480

1,369

2,055

0

500

1000

1500

2000

2500

3000

0 0.2 0.4 0.6 0.8 1

Ion

, u

A/u

m



Flat

HP: 100 nA/um

SP: 1 nA/um

LP: 50 pA/um


Stress Free SiGe

7nm NMOS FinFET

524 508

263

902 926

653

1,009

1,427 1,480

1,369

2,055

0

500

1000

1500

2000

2500

3000

0 0.2 0.4 0.6 0.8 1

Ion

, u

A/u

m



Flat

Dip HP: 100 nA/um

SP: 1 nA/um

LP: 50 pA/um


Stress Free SiGe

7nm NMOS FinFET

524 508

263

902 926

653

1,009

1,427 1,480

1,369

2,055

0

500

1000

1500

2000

2500

3000

0 0.2 0.4 0.6 0.8 1

Ion

, u

A/u

m



Flat

Dip

Best

HP: 100 nA/um

SP: 1 nA/um

LP: 50 pA/um


Stress Free SiGe

7nm NMOS FinFET

524 508

263

902 926

653

1,009

1,427 1,480

1,369

2,055

0

500

1000

1500

2000

2500

3000

0 0.2 0.4 0.6 0.8 1

Ion

, u

A/u

m



Flat

Dip

Best

Gone

HP: 100 nA/um

SP: 1 nA/um

LP: 50 pA/um


Strained SiGe: 2 GPa Tensile Stress

7nm NMOS FinFET

524 508

263

902 926

653

1,009

1,427 1,480

1,369

2,055

722 638

1,233 1,310

970

1,054

1,900 2,003

1,902

2,429

0

500

1000

1500

2000

2500

3000

0 0.2 0.4 0.6 0.8 1

Ion

, u

A/u

m



SiGe (2GPa) LP SiGe (2GPa) SP SiGe (2GPa) HP

+40%

+

40%

+

40%



7nm NMOS FinFET

722 638

1,233 1,310

970

1,054

1,900 2,003

1,902

2,429

0

500

1000

1500

2000

2500

3000

0 0.2 0.4 0.6 0.8 1

Ion

, u

A/u

m



• This is only possible

for bulk FinFETs

• SOI FinFETs will be

pretty much stress

free


Strained SiGe: Ninv and Vinj

7nm NMOS FinFET

0.0E+00

2.0E+12

4.0E+12

6.0E+12

8.0E+12

1.0E+13

1.2E+13

0 0.2 0.4 0.6 0.8 1

Inve

rsio

n c

harg

e, 1

/cm

2


SiGe (2GPa) LP

SiGe (2GPa) SP

SiGe (2GPa) HP

0.E+00

1.E+07

2.E+07

3.E+07

0 0.2 0.4 0.6 0.8 1

Inje

cti

on

ve

loc

ityj, c

m/s


SiGe (2GPa) LP

SiGe (2GPa) SP

SiGe (2GPa) HP



7nm NMOS FinFET

722 638

1,233 1,310

970

1,054

1,900 2,003

1,902

2,429

0

500

1000

1500

2000

2500

3000

0 0.2 0.4 0.6 0.8 1

Ion

, u

A/u

m



Flat Dip

Best

Gone


Strained SiGe: LP, SP & HP Champions

7nm NMOS FinFET

722 638

1,233 1,310

970

1,054

1,900 2,003

1,902

2,429

0

500

1000

1500

2000

2500

3000

0 0.2 0.4 0.6 0.8 1

Ion

, u

A/u

m



LP: Si

SP: Mid-range SiGe

HP: Ge


722 638

1,233 1,310

970

1,054

1,900 2,003

1,902

2,429

0

500

1000

1500

2000

2500

3000

0 0.2 0.4 0.6 0.8 1

Ion

, u

A/u

m



Strained SiGe: Combination Champion

7nm NMOS FinFET

• Only Si and SiGe

with low Ge % can

match LP spec

• HP performance

penalty to pure Ge is

~20%

• The choice between

pure Si vs SiGe with

low Ge % can be

made based on

PMOS/NMOS stress

trade-off

Better PMOS s

Better NMOS s


Outline


IdVg After Work-Function Adjustment

3D analysis in S-Device

GaAs

InAs BTBT

• BTBT model

calibrated by

IMEC

• Vdd = 0.7 V


Leakage Patterns

Vgs = -0.3 V

InAs GaAs BTBT is spread

along junction

GIDL happens

at the fin top


Ion @Minimum Ioff: SiGe and InGaAs


1

10

100

1000

10000

100000

1000000

1 10 100 1000 10000

Min

imu

m I

off

, p

A/u

m

Corresponding Ion, uA/um

InGaAs

SiGe no stress

SiGe 2 GPaHP

SP

LP

InAs

GaAs

Si

Ge

InGaAs with 20% In

SiGe with

90% Ge

3D

S-D

evic

e

S-Band


0%

20%

40%

60%

80%

100%

0 0.2 0.4 0.6 0.8 1

Va

lle

y o

cc

up

an

cy %

Gallium mole fraction

Gamma, Delta & Lambda Valleys

7nm NMOS FinFET

• Here, Vgs = 0.7 V and gate WF is adjusted to have min Ioff at Vgs = 0

• There are too few electrons at high Ge mole fractions for this gate overdrive

• InGaAs has carriers mostly in Gamma valley in the entire InAs to GaAs range

0%

20%

40%

60%

80%

100%

0 0.2 0.4 0.6 0.8 1

Va

lle

y o

cc

up

an

cy %


G

L

SiGe InGaAs

X

L


0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

0 0.2 0.4 0.6 0.8 1

Ban

dg

ap

, e

V

Gallium mole fraction

Bulk

Narrow fin

0.6

0.7

0.8

0.9

1.0

1.1

1.2

0 0.2 0.4 0.6 0.8 1

Ban

dg

ap

, e

V


BulkStrained narrow finStress-free narrow fin

Band Gap Widening and Narrowing

7nm NMOS FinFET

• For SiGe, 6nm wide fin widens bandgap by 40 mV to 50 mV

• Tensile uniaxial 2 GPa stress pushes it down by 70 mV to 100 mV

• For GaAs, the widening is 155 mV, and for InAs it grows to 340 mV

SiGe InGaAs co

nfinem

en

t

str

ess

co

nfinem

en

t


Group IV vs III-V: Ninv and Vinj

7nm NMOS FinFET

0.0E+00

2.0E+12

4.0E+12

6.0E+12

8.0E+12

1.0E+13

1.2E+13

0 0.2 0.4 0.6 0.8 1

Inve

rsio

n c

ha

rge

, 1

/cm

2

Mole fraction (Germanium or Gallium)

InGaAs LP InGaAs SP InGaAs HP


0.E+00

1.E+07

2.E+07

3.E+07

4.E+07

5.E+07

6.E+07

0 0.2 0.4 0.6 0.8 1

Inje

cti

on

ve

loc

ityj,

cm

/s



Group IV vs III-V

7nm NMOS FinFET

601

199

1,977

754

2,449

2,612 2,589

722 638

1,233 1,310

970

1,054

1,900

2,003 1,902

2,429

0

500

1000

1500

2000

2500

3000

0 0.2 0.4 0.6 0.8 1

Ion

, u

A/u

m





Group IV vs III-V: LP, SP & HP Champions

7nm NMOS FinFET

601

199

1,977

754

2,449

2,612 2,589

722 638

1,233 1,310

970

1,054

1,900

2,003 1,902

2,429

0

500

1000

1500

2000

2500

3000

0 0.2 0.4 0.6 0.8 1

Ion

, u

A/u

m




LP: Si

SP: 30% In InGaAs

HP: Mid-range InGaAs


Group IV vs III-V: Combination Champion

7nm NMOS FinFET

601

199

1,977

754

2,449

2,612 2,589

722 638

1,233 1,310

970

1,054

1,900

2,003 1,902

2,429

0

500

1000

1500

2000

2500

3000

0 0.2 0.4 0.6 0.8 1

Ion

, u

A/u

m



SiGe (2GPa) LP SiGe (2GPa) SP SiGe (2GPa) HP• Only Si, low Ge

SiGe, and GaAs can

match LP spec

• InGaAs with 10% In

has competitive

performance, but is

too sensitive to In

content

• This would bring

severe variability

• So, silicon looks the

best…

• SiGe with low Ge %

can be used for

stress engineering


1,090

1,064

689

1,510

1,962

1,651

1,211

694

30 27

331 364

112

239

1,131

1,239

1,082

1,547

0

200

400

600

800

1000

1200

1400

1600

1800

2000

0 0.2 0.4 0.6 0.8 1

Ion

, u

A/u

m




0.5 V Vdd Instead of 0.7 V Vdd

7nm NMOS FinFET

• InGaAs with 30% In

really shines at SP

and HP specs

• Nobody can pull off

LP at 0.5 V Vdd.

Would you like your

iPhone to be ~30x

slower?

• To have 0.5 V Vdd,

variability has to go

down ~2x. That is a

stretch.

• The best InGaAs

composition has Si-

like bandgap


Summary

• It is a close race, no clear winner

• The best choice depends on particular chip spec

7nm NMOS FinFET

(invited) material engineering for 7nm finfets

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