in-situ characterization of defect dynamics in 4h-sic power diodes under high-voltage stressing

In-situ Characterization of Defect Dynamics in 4H-SiC Power Diodes under High-Voltage Stressing

Krishna Shenai,1 Balaji Raghothamachar,2 Michael Dudley,2 and Aris Christou3

1LoPel Corporation, 2259 Palmer Circle, Naperville, IL 60564, USA

1Also with: Electrical Engineering and Computer Science Department

Northwestern University, Evanston, IL 60208-3118

2Department of Materials Science and Engineering, Stony Brook University, Stony Brook, NY 11794-2275, USA

3Department of Materials Science and Engineering, University of Maryland, College

Park, MD 20742, USA

Wide bandgap (WBG) semiconductor power switching devices, especially those made on silicon carbide (SiC) and gallium nitride (GaN), promise transformative advances in electrical power switching systems because of superior electrical and thermal properties of these materials compared to the semiconductor silicon. However, the progress has been slow despite intense scientific and industrial development. Both SiC and GaN semiconductors contain a high density of crystal defects and the role of defects on the performance and reliability of electrical power switching devices under extreme operating environment is not clear. Using synchrotron white beam X-ray topography (SWBXT), it is shown that the breakdown mechanism in 4H-SiC is initiated at the threading screw dislocations present in the high field regions of a power diode. To avoid this phenomenon from occurring, commercial 4H-SiC high-voltage diodes are rated for punch-through leakage currents rather than for avalanche breakdown condition. Thus, crystal defects in 4H-SiC present a major roadblock for performance and reliability optimization of power switching devices.

I. Introduction

A comprehensive proposal by Shenai et al [1] spurred world-wide interest in electrical power switching devices made from wide bandgap (WBG) semiconductors. After a period of intense scientific and industrial development, high-voltage power switching devices made on silicon carbide (SiC) and gallium nitride (GaN) are showing significant promise for radical transformation of electric utility, transportation, and computing/telecommunication infrastructures in the impending 21st century energy economy. As of this writing, SiC is a more mature technology compared to GaN for high-voltage power device fabrication. Although several polytypes exist for the SiC crystal, the desired polytype for electrical power switching applications is 4H-SiC because of its superior electrical and thermal properties. The basic unit of a 4H-SiC crystal structure is a silicon-carbon bilayer; within each bilayer, carbon atoms are arranged in a two-dimensional hexagonal pattern, with silicon atoms directly on top of them. Three-dimensional lattices are then built by stacking the bilayers, along the normal direction,

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called the c-axis, of the hexagonal structure, and a surface polarity effect results with one face of the crystal formed of silicon atoms and the other of carbon atoms. In fact, several crystal structures or polytypes of SiC can be described in terms of stacked hexagonal layers, but with different rotational offsets between the layers.

Early attempts to synthesize single crystal bulk SiC substrates using sublimation and solution growth techniques [2, 3] were not practical on an industrial scale. The main problem is that SiC does not exist in a liquid form. Physical vapor transport (PVT) growth at very high temperatures (2000 m- 2300°C) is the primary method for growing large size SiC boules. Early vapor phase growth methods to grow SiC crystals such as the Acheson [4] and the Lely [5] methods were low in yield and non-reproducible. The Acheson method produces spontaneously nucleated small crystals while Lely method can yield bigger, low defect density crystals but not suitable for industrial scale production. However, the invention in 1978 of the “modified Lely method” [6] (or physical vapor transport, PVT) opened the way to produce semiconductor-quality large-area single-crystal SiC ingots which has remained to date as the preferred technique to grow 4H-SiC wafers. This is a seeded sublimation technique: supersaturated SiC vapor condenses on to a single crystal seed inside a graphite crucible. This method allowed reproducibility and controllability into the randomness of the Lely process. Because of extremely high growth temperatures and relative metastability of one phase over another, polytype switching during the crystal growth process occurs. This problem has been inadvertently and fortuitously ameliorated by the tendency of SiC to form c-axis threading screw dislocations (TSDs) when growth is carried out on (0001) seeds. The seed surface intersections of these dislocations provide inexhaustible sources of steps which supply stacking sequence guidance for vapor phase species that absorb onto flat terraces and diffuse to their risers (under low super saturation conditions) [7]. However, this assistance comes at a price since these TSDs have other properties that detract significantly from their usefulness towards polytype control. First, their Burgers vectors can take on values which are multiples of the c lattice parameter (nc, where n is an integer) increasing their stress fields close to the core region to the point where material evaporates during growth creating a hollow core known as the micropipe. This defect was quickly identified as a device killer [8] sparking a huge effort to eliminate them. Micropipes were finally eliminated in 2007 [9] although significant densities of 1c TSDs remain.

Another defect which existed in significant densities in the early days is the basal plane dislocation (BPD). BPDs are deformation induced dislocations, with Burgers vector of 1/3<11-20> that glide on the basal plane under the action of shear stress generated by thermal gradients inside the growth chamber. While not receiving as much attention as micropipes and TSDs in the early days, these defects rose in prominence with the observation that they become sources of Shockley stacking faults that expand in bipolar devices under forward bias, leading to an increase in forward voltage with time causing eventual device failure [10, 11]. This prompted renewed effort in the optimization of hot zone design inside the PVT growth chamber to minimize the thermal gradient induced stresses that drive the motion of BPDs in the substrate. This has culminated in reductions of BPD densities down from tens of thousands per square centimeter to just a few hundred. Simultaneously, much effort has been expended in reducing the densities of BPDs that are replicated from the substrates into the CVD grown homo-epitaxial layers required for device fabrication. This involved modification of the surface morphology at the surface intersections of the BPDs through intentional surface etching [12] or indirect etching created by growth interrupts. This has enabled a further reduction of the BPD densities in

ECS Transactions, 66 (1) 205-216 (2015)



the active regions of the devices ameliorating but not eliminating the problem of the Shockley fault expansion.

One further defect that exists at significant densities in SiC substrates is the c-axis threading edge dislocation (TED). Like the TSD, this is a growth dislocation that simply replicates at its surface intersections on the seed or growing crystal interface. Densities of TEDs can be as high as several thousand per square centimeter especially since catastrophic BPDs have been nearly eliminated by converting them to TEDs. The evolution of the densities of various dislocation types in 4H-SiC substrates and epitaxial layers suggests that TSDs and TEDs remain as prominent defects in commercial 4H-SiC bulk substrates and epitaxial wafers (see Figs. 1 and 2).

Over the past two decades, considerable resources and effort have been expended to expand the substrate size and lower the defect densities. Commercial substrates sizes were around 1 inch diameter in 1992 and have gradually expanded to 4 inch diameter in 2010 with 6 inch diameter substrates commercially available in 2013. Micropipes have been more or less eliminated and BPD densities have been greatly reduced by growth system design to reduced thermal stresses but densities of TSDs and TEDs have remained more or less the same. All commercial 4H-SiC power devices contain an abundance of these crystallographic defects in active areas; however, it is not clear what negative influence these defects have on device performance, reliability and reproducibility. Micropipes are well-known as device killers [8] while the detrimental influence of BPDs on device performance is also established [10, 11]. Earlier it was believed that TSDs and TEDs that thread into the epitaxial layers are relatively benign with respect to short-term device performance but recent evidence points to their significant impact on long-term device

Fig. 1. Dislocation density trends from 2002 to present in PVT-grown, 4H-SiC substrates. Data taken from S. Ha et al, J. Cryst. Growth 244, 257-266 (2002) and T. Ohno et al, J. Cryst. Growth 260, 209-216 (2004).




reliability. In 2002 [13], Acharya and Shenai had reported low switching dv/dt capabilities of 4H-SiC junction barrier-controlled Schottky (JBS) power diodes (54 V/ns and 7V/ns for 600V diodes at 25°C and 125°C, respectively). They had also speculated possible excess charge generation and micro plasma formation [14, 15] in the vicinity of defect sites present in reverse-biased semiconductor space-charge region during high-voltage switching. To date, commercial devices show the same dv/dt performance as measured by Acharya and Shenai in 2002 [16]. Additionally, Shenai et al (16) recently reported more than two orders of magnitude lower avalanche energy capability for 4H-SiC JBS power diodes compared to similarly rated silicon power diodes. In a parallel development, Yamamoto et al [17] showed that TEDs present in the epitaxial layer can reduce time-dependent dielectric breakdown (TDDB) of metal-oxide semiconductor (MOS) structures in 4H-SiC by an order of magnitude while TSDs reduce it by two orders.

II. Experimental Evaluation of Defect Dynamics in 4H-SiC Power Diodes during High-Voltage Stressing

The diode structure studied is a commercially available vertical 4H-SiC JBS diode where a slightly higher doped n-type buffer layer is used to constrict the spreading of the space-charge region beyond the lightly doped n- - type drift-region (see Fig. 3). The p+ region does not contribute to any electrical conduction, but is simply there to shield the metal-semiconductor interface from high-field effects when the diode is reverse-biased. The device first goes through a punch-through mechanism prior to eventual breakdown [18]. This device is rated for 600 volts and 23 amps continuous power switching operation at 25°C; however, the continuous current rating is degraded to 8 amps at 150°C. Discrete diode chips packaged in industry-standard TO-220 packages were procured and

Fig. 2. High resolution synchrotron monochromatic X-ray topographs recorded at Argonne’s Advanced Photon Source (APS) facility. (a) Back-reflection X-ray topograph (g = 0004) images of close-core threading screw dislocations (TSDs) and basal plane dislocations (BPDs) in a (0001) 4H SiC wafer; (b) Grazing incidence X-ray topograph (g = 11-28) of 4H-SiC substrate showing TSDs (right and left handed) and TEDs; (c) Transmission X-ray topograph showing the images of BPDs.




characterized in detail with case temperature varied from 25°C to 250°C in steps of 25°C; extensive forward and reverse current-voltage (I-V) and capacitance-voltage (C-V) measurements were performed; and in most cases, the measured data agreed with the data sheet values. A few devices were de-capped and the static I-V and C-V measurements were repeated in order to ensure the integrity of the diode chip and terminal connections. A slight increase in the reverse leakage current was measured that is likely caused by the loss of a gel that is typically used in the package to smooth out the surface electric field. A single event burn-out (SEB) stress test circuit with sophisticated data acquisition and signal processing circuitry was built and used to apply the high-voltage reverse bias stress on the diode (see Fig. 4). This circuit was previously used to assess the field-reliability of silicon power metal-semiconductor field-effect transistors (MOSFETs) [16]. The capacitance, C across the device under test (DUT) stores the voltage that the diode supports for the leakage current, IL determined by the current-limiting resistor, R in the circuit. The DUT is the 4H-SiC diode being studied and is reverse biased to a voltage value determined by the DC power supply, VREV. The signal processing circuitry senses any charging event in the reverse-biased space-charge region of the DUT; the sampling and data acquisition circuitry records in excess of 2,000 samples per second and is capable of detecting less than a microamp of the leakage current transient. The circuit is also equipped with a protection mechanism when the current spike exceeds a predetermined value.

Fig. 3. A schematic cross-section of half unit cell of a commercial high-voltage 4H-SiC JBS power diode where P represents the dimension of the diffusion window of p+-type implant etched in the diode fabrication mask, and S is the remaining area of the active region where the anode metal makes contact with the semiconductor.




An experiment was designed to image the 4H-SiC power diode by synchrotron white beam X-ray topography (SWBXT) [19] while it is subjected to large switching reverse voltage in an SEB stress test circuit. By monitoring the diode under the electrical stress in situ by SWBXT, micro-plasma generation and local “hot spot” formation in the vicinity of defect sites can be microscopically investigated. The SWBXT in the back reflection geometry is particularly suitable for imaging TSDs and micropipes in SiC [20] which are primarily responsible for device performance degradation and failure. In the experiment, the slit-limited synchrotron white beam X-ray radiation at 1-BM-B white beam station at the Advanced Photon Source (APS) at Argonne National Laboratory was used. This beam is incident directly on the diode material installed in the SEB test circuit and the back reflected beam from the (0001) basal planes is recorded on a high resolution X-ray film placed on the same side as the incident beam. Device performance parameters were monitored as the diode is stressed while simultaneously imaged in the synchrotron beam (see Fig. 5a). The diode was subjected to increasing reverse voltage stress starting at the rated 600V and SWBXT images were recorded at 100V intervals until the diode exhibited breakdown. Under normal diode operation, the back reflection topograph (see Fig. 5b) shows contrast from TSDs in addition to phase contrast effects from the contact leads. Immediately prior to breakdown at 900V, a TSD below the contact leads exhibited higher strains than normal (see Fig. 5b). This strongly indicates that the breakdown of the diode was induced by the TSD in a region which is favorable to current filamentation. Higher local electric field in the vicinity of the semiconductor-metal contact interface and the proximity of the TSD to the contacts makes it more vulnerable to higher strains, and thus contributing to breakdown at a lower voltage than if the defect were not present. TSDs away from this region did not exhibit any change in strain levels. The diode breakdown was also not initiated in the edge termination region suggesting good integrity of the diode edge termination design. On the other hand, when the de-capped Si power diode with the identical voltage and current ratings was subjected to the same experiment, the silicon diode also exhibited breakdown, but the crystal simply suffers inhomogeneous deformation due to stressing limits of the material being reached.

Fig. 4. A schematic of the test circuit used for single event burn-out (SEB) stress evaluation where the DUT represents the 4H-SiC JBS power diode studied. The diode leakage current, IL is monitored as the reverse bias voltage, VREV is increased using advanced signal processing and data acquisition circuitry.




Fig. 5. (a) A schematic of back reflection geometry used for recording X-ray topographs from de-capped power semiconductor diodes. (b) Back reflection topographs (g = 000 16) recorded from de-capped 4H-SiC JBS power diode at (i) 700V showing contrast from TSDs as indicated by arrows; (ii) 900V showing enhanced contrast due to strains at 1 threading screw dislocation shown in enlarged inset. The white contrast features are due to the metal leads absorbing the X-ray beam.




III. Electrical Analysis and Modeling of 4H-SiC Power Diodes

The specific on-resistance, Rsp which is the product of on-resistance, Ron and chip area, Achip has been used to optimize the manufacturing technology of controllable majority carrier power devices such as the power MOSFET’s since it’s first introduction by Adler and Westbrook in 1982 [21]. The silicon on-resistance limit discussed by Adler and Westbrook, ie., Ron ∞ VBD

2.5, corresponds to the theoretical limit which is the case of current flow between two equal area plates for silicon that is proper thickness and doping to obtain a given breakdown voltage, VBD. This figure-of-merit (FOM) relates to maximum electrical conductivity of a unipolar power switch for a given VBD design, and thus ensures the lowest chip cost and minimum conduction loss provided the device is designed for avalanche breakdown. Based on near-optimal silicon power MOSFET performance, Shenai et al [1] had proposed the use of wide bandgap (WBG) semiconductors for further improvement in the electrical conductivity of power switching devices. This proposal spurred world-wide interest in WBG power switching technology.

The specific on-resistance vs. breakdown voltage criterion, i.e., Rsp vs. VBD criterion, has remained an “industry” standard and is a true measure of the maximum electrical conductivity achievable for a given material technology. This criterion has served the silicon power industry well for over three decades. However, it must be noted that to achieve the maximum electrical conductivity and to obtain the optimal material performance, power devices must be designed and rated for avalanche breakdown of the drift-region. The problem is that the manufacturer data sheets do not provide sufficient information to evaluate if the 4H-SiC JBS power diodes are designed optimally. In order to evaluate this important criterion, a simple and accurate physics-based methodology was developed to reverse-engineer and extract the key diode design parameters from static I-V and C-V measurements. This methodology was applied to commercial 600V, 1200V and 1700V 4H-SiC JBS power diodes with current ratings from 1A to 25A procured from two manufacturers. The doping concentrations in the drift- and buffer-regions, NDR and NB, respectively, were extracted from the C-V measurements using the conventional procedure [22]; the diode area was obtained from the manufacturer data sheets. The net diode series resistance, RS, Schottky barrier junction built-in potential, Vbi, and the effective Schottky barrier height, ΦB were calculated from the measured I-V characteristics by properly including the image force and dipole barrier lowering effects [23]. The thicknesses of the drift- and buffer-regions, WDR and WB, respectively, were extracted from the measured punch-through voltage, VPT and the calculated electric field obtained by solving the Poisson’s equation for the assumed uniform doping profiles in the drift- and buffer-regions. For the JBS diode structure (see Fig. 1), the net drift-region resistance, RDR can be calculated as follows: R = R − � − R U − R

where RB, RSUB and RC are the resistances of the n-type buffer layer, n+ substrate, and cathode metal ohmic contact to the substrate, respectively. These resistances are given by: � = ��

R U = ρ U W UA




� = ��

where ρ is the resistivity of the buffer layer which can be easily calculated since the doping density is known. A substrate resistivity, ρ U = 0.012 Ω-cm and substrate thickness, W U = 377 microns were used in the calculations; both of these parameters are specified in the manufacturer data sheets. A specific contact resistance, � = 2.5 x 10-5 Ω-cm2 was also used in the calculations for the cathode ohmic contact. The specific drift region resistance, RDRS is then given by: � = � ��ℎ��

The results of these calculations are compared with 4H-SiC material limit obtained from the well-known formula, first proposed by Shenai et al [1] (see Fig. 6): � � = ��

Fig. 6. A plot of the extracted drift-region specific on resistance, RSP vs. avalanche breakdown voltage, VBD for majority carrier devices in silicon and 4H-SiC semiconductors. For silicon, the data points are obtained from scaled power MOSFETs and for 4H-SiC, the data points are obtained for the JBS power diodes.




where εs is the semiconductor permittivity, μn is the electron mobility, E is the critical electric field strength at avalanche breakdown, and V is the avalanche breakdown voltage. The silicon material limit was reached in the early 1990’s by adopting advanced lithography, trench-gate MOS structures, and reliable multi-level metallization with low contact resistances [24]. Our results clearly shows that all 4H-SiC power diodes are rated for punch-through leakage current and none of the devices are optimized for avalanche breakdown. For 600V diodes, the on-resistance is limited by substrate and contact resistances whereas for higher voltage devices significant opportunity for further on-resistance and cost reduction exists.

IV. Summary and Discussions

For nearly three decades, the exact role of crystal defects on the performance and reliability of SiC power devices has remained a mystery. Whereas 4H-SiC power diodes and MOSFETs have been commercially made available by multiple vendors around the world for some time now, it is not clear if these devices are optimized and rated for avalanche breakdown in the semiconductor bulk. The cost is high compared to silicon power devices, and the field-reliability in end-applications is unknown. The problem is complicated by the fact that the manufacturer data sheets do not provide important device design and reliability parameters, and there is little or no interaction among the key stakeholders in the power electronics supply chain that spans from the material suppliers to original equipment manufacturers (OEMs). Our work reveals that commercial high-voltage 4H-SiC JBS power diodes are rated for punch-through voltage and avoid avalanche breakdown in the semiconductor bulk. When stressed beyond the rated voltage, we have shown that the breakdown is initiated at the threading screw dislocations (TSDs) present in the semiconductor bulk where the electric field strength is high. On one hand, TSDs are essential for the crystal growth of 4H-SiC semiconductor using the PVT process [6] as they provide the seeding mechanism that is needed in the modified Lely process. In fact, in order to obtain commercially viable growth rates when growing large-area 4H-SiC ingots, a higher density of TSDs is preferred. Although basal plane dislocations (BPDs) are nearly eliminated by converting them into threading edge dislocations (TEDs), there is substantial evidence in the literature that suggests that TSDs also seed other defects, especially the TEDs that are present at even higher densities than TSDs in state-of-the-art commercial 4H-SiC wafers. Recent experimental results also suggest that the catastrophic carbon vacancy defect in 4H-SiC that is enhanced during high-temperature processing may also have its roots in the TED [25, 26]. The carbon vacancy, is an intrinsic point defect in as-grown 4H-SiC epitaxial layers, and is a dominant electrically active defect that is responsible for the so-called Z1/2 and EH7 centers which occur with a typical concentration in the range 1012 – 1013 cm-3 range. These intrinsic point defects act as traps and/or recombination centers for charge carriers, and present a formidable challenge in the development of high-voltage (> 10 kilo volts) bipolar power devices in 4H-SiC [27].

Perhaps a parallel can be drawn with the growth of the silicon industry. The foundation for single crystal silicon growth process emanates from the original Czochralski process [28, 29] where the wafer ingots are pullzed from a solution. The silicon crystal is typically grown at a much lower temperature (< 1,000°C) than the SiC crystal (> 2,000°C). On the other hand, the seeding of the SiC crystal using the PVT process begins with threading screw dislocations (TSDs). Hence, to obtain commercially viable crystal growth rates for SiC, a minimum number of TSDs are needed and the growth must be performed at a much




higher temperature than silicon. These inherent material synthesis limiations lead to a high density of crystal defects in the SiC substrate material compared to silicon substrates. Silicon defect density for the past many decades has been steady below 1 defect/cm2 and 450 mm diameter silicon wafers are contemplated by 2016 at the cost of about $2.2/cm2 [30]. In comparison, 150 mm 4H-SiC epitaxial wafers that contain an abundance of crystal defects are now commercially available at a cost of about $12/cm2 [31]. The starting material problem represents a fundamental limitation in the large-scale commercialization of WBG power devices especially for high-volume applications such as electric vehicles which by one estimate demands several million wafers per year by 2,020. Alternate material synthesis techniques that start with a different seeding mechanism and focus on crystal growth at much reduced temperatures than today’s PVT process may have the potential to reduce crystal defects. One such 4H-SiC crystal-growing process introduced by Nakamura et al [32] had limited success, at least from a commercial point of view.

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Acknowledgements

The submitted manuscript has been created by UChicago-Argonne, LLC, Operator of Argonne National Laboratory (“Argonne”). Argonne, a U.S. Department of Energy Office of Science laboratory, is operated under Contract No. DE-AC02-06CH11357. The U.S. Government retains for itself, and others acting on its behalf, a paid-up nonexclusive, irrevocable worldwide license in said article to reproduce, prepare derivative works, distribute copies to the public, and perform publicly and display publicly, by or on behalf of the Government.

The authors also acknowledge many years of fruitful collaborations with a large number of leading researchers in the field from all over the world. They wish to especially thank the contributions of R. F. Davis, M. Loboda, K. Gaskill, P. G. Neudeck, R. E. Stahlbush, T. S. Sudarshan, and B. G. Svensson. The authors also thank A. Macrander and G. Drake of Argonne National Laboratory for assisting with measurements at the Advanced Photon Source and for the construction of the SEB sensing and data acquisition circuitry, respectively.



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in-situ characterization of defect dynamics in 4h-sic power diodes under high-voltage stressing

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