Amirkabir University of Technology(Tehran Polytechnic)

Hamid Reza ZarandiAssociate Professor Department of Computer Engineering Computer Networks and Architecture

Email:h_zarandi aut.ac.ir

Phone:+98 21 6454 2702

h-index (Scopus):16Citations (Scopus):853

Educational Records

# Degree/Major University City Country Graduation Date

1 Computer Engineering (PhD) Sharif University of Technology Tehran IRAN March 2007

2 Computer Engineering (BSc) Sharif University of Technology Tehran IRAN Sept. 2000

3 Computer Engineering (MSc) Sharif University of Technology Tehran IRAN Sept. 2002

Scientific & Industrial Experience

# Responsibilities Titles Name of Organization Starting Date Termination Date

1 Visiting researcher University of California, Irvine, US

2 Visiting researcher Passau University, Germany

3 Visiting researcher INRIA research Institute, France

4 Visiting researcher University of Bristol, UK

Research Interests

# Title Start date

1 Networks-On-Chip

2 Reliable System Design

3 Computer Architecture

4 Embedded Systems

Supervised MSc Theses

# Thesis title By Date

1 Vulnerability evaluation of LPWAN IoT protocol, NB-IoT, UsingFault Injection and Proposing an improvement method

Fateme Khojaste Dana & HamidReza Zarandi

June 2022

2 Automatic Context-aware IoT Device Failure Detection in SmartHomes

Alireza Borhani & Hamid RezaZarandi

August2021

3 An Approximate Computing method for Static and temporal FaultTree Analysis

Navid Abbasnezhad Talebkhan &Hamid Reza Zarandi

February2021

4 An Approximate Computing method for Dynamic Fault TreeAnalysis

Salar Hashemi Taheri & Hamid RezaZarandi

October2019

5 To Present a Method For Tolerating Write Errors in STT-RAMMemories Considering Power Consumption

Saeed Seyedfaraji & Hamid RezaZarandi

September2018

6 A Cross-Layer Method to Tolerate Multiple Event Transients(METs) in Combinational Circuits

Amirmohammad HajisadeghiKahdooyeh & Hamid Reza Zarandi

September2018

7 Tolerating Read Disturbances in RRAM Memories Mohammadreza Nakhkash & HamidReza Zarandi

February2018

8 Soft Error Susceptibility Mitigation of RRAM-based MemoryArrays

Hossein Bardareh & Hamid RezaZarandi

February2018

9 Reducing Vulnerability of STT- based Logic-in- Memory AdderAgainst Soft Errors

Javad Talafy & Hamid Reza Zarandi February2018

10 Aging- aware task scheduling in MPSoC using knowledge fromlow abstraction- levels

Masoomeh Karami & Hamid RezaZarandi

March2017

11 a robust aging sensor design against process variation Parnian Shabani Kamran & HamidReza Zarandi

September2016

12 A Method to Reduce NBTI Effect in SRAM Cell Vahid Amini & Hamid Reza Zarandi September2016

13 Amethod to reduce Aging effect in a finfet Adder Fatemeh Hosseini & Hamid RezaZarandi

September2016

14 A Method To Tolerate NBTI In Digital Circuits Maryam Ghane & Hamid RezaZarandi

December2015

15 An improvement on Reduction of Silent Data Corruption error inCPUs

Sayed Ali Houri & Hamid RezaZarandi

August2015

16 An Improved Wear-out Faults recovery in CMPs Elham Kashefi & Hamid RezaZarandi

February2015

17 adaptive Anomaly Detection caused by sensors in embededsystems

Fatemeh Ehsani Besheli & HamidReza Zarandi

October2014

18 a technique to increase reliability in memristor-based memories Peiman Pour Momen & Hamid RezaZarandi

October2014

19 a Multiple Soft Error Tolerant Method in Networks on Chip Saeed Kohsari & Hamid RezaZarandi

April 2014

20 Accelerating fault tree analysis using stochastic logicimplemented on H.W

Elham Cheshmikhanikhanghah &Hamid Reza Zarandi

October2013

21 An Adaptive Deadlock-Avoidance Routing Algorithm For Networkon Chips

Kamran Nasiri & Hamid RezaZarandi

October2013

22 A New Method for Anomaly Correction in Embedded Systems Roghaye Mojarrad & Hamid RezaZarandi

October2013

23 A Method to improve SDC detection coverage in CPUs Fatame Eman Parast & Hamid RezaZarandi

October2013

24 presenting a fault-tolerant technique against soft errors in many-core processors

Elnaz Ghods_E_Vali & Hamid RezaZarandi

November2012

25 proposing a new nethod to tolerate multiple faults in embeddedsystems with timing constraints

Mohammad Hadi Mottaghi Khezri &Hamid Reza Zarandi

October2012

26 evalution of soft error on rollback recoverymethod in embeddedsystems

Hossein Malaee Aghdam & HamidReza Zarandi

October2012

27 presenting a fault-aware application task mapping on CMPsregarding to communication energy

Fatemeh Khalili & Hamid RezaZarandi

September2012

28 consideration of security in wired networks-on-chip Faranak Jannati & Hamid RezaZarandi

September2012

29 performance evluation of wireless network-on-chip Neda Tavakoli & Hamid RezaZarandi

September2012

30 robustness assessment of reconfigurable network-on-chipagainst side-channel attachs

Shadan Shahdi & Hamid RezaZarandi

September2012

31 Presenting a fault-tolerant mechanism for network on chip withlow performance penalty

Saleh Fakhrali & Hamid RezaZarandi

February2012

32 Presenting a method to mitigate soft error effects inreconfigurable network-on-chips

Ronak Salamat & Hamid RezaZarandi

February2012

33 Presenting and evaluating a technique for control- flow errorrecovery in multicore processors

Navid Khoshavi Najaf Abadi &Hamid Reza Zarandi

January2012

34 Fault-tolerant evaluations of buffering types and virtual buffers innetwork-on-chip routers

Farveh Saber Mahani & Hamid RezaZarandi

December2011

35 Developing a run-time soft error recovery method for multicores Hananeh Aliee & Hamid RezaZarandi

September2011

36 Implementation of stide anomaly detection method in embeddedsystems

Hoda Ghabeli & Hamid RezaZarandi

May 2011

37 An anomaly detection technique in embedded systems toincrease fault coverage

Mahroo Zandrahimi & Hamid RezaZarandi

December2010

38 Design of computer networks for digital control system of powerplants

Masoud Evazi & Hamid RezaZarandi

October2010

39 Increasing in asynchronous circuit delay fault tolerance due toprocess variation

Mohsen Rajiasadabadi & HamidReza Zarandi

September2010

40 Dependability evaluation and improvement in CAN-basedembedded systems

Saman Khoshbakht & Hamid RezaZarandi

July 2010

41 Design and evaluation of a structural method for dependability inSRAM-based FPGAs

Alireza Rohani & Hamid RezaZarandi

February2010

42 A fault-tolerant routing technique in SRAM-based FPGAs Somayeh Bahramnejad & HamidReza Zarandi

December2009

Journal Papers

Portal Records

1 Amirmohammad Hajisadeghi Kahdooyeh, Hamid Reza Zarandi, "CLEAR: A Cross-Layer Soft Error Rate ReductionMethod Based on Mitigating DETs in Nanoscale Combinational Logics", MICROPROCESSORS AND MICROSYSTEMS,September 2021 Vol. 85, Num. 104282, Page 0-0, September 2021,

2 Ali Reza Tajary, Hamid Reza Zarandi, Nader Bagherzadeh, "IRHT: An SDC Detection and Recovery ArchitectureBased on Value Locality of Instruction Binary Codes", MICROPROCESSORS AND MICROSYSTEMS, June 2020 Vol.77, Num. 0, Page 1-13, June 2020,

3 Javad Talafy, Farzaneh Zokaee, Hamid Reza Zarandi, Nader Bagherzadeh, "A High Performance, Multi-Bit OutputLogic-in-Memory Adder", IEEE Transactions on Emerging Topics in Computing, March 2020 Vol. 0, Num. 0, Page 1-11, March 2020,

4 Saeed Seyedfaraji, Amirmohammad Hajisadeghi Kahdooyeh, Javad Talafy, Hamid Reza Zarandi, "DYSCO: DYnamicStepper Current InjectOr to Improve Write Performance in STT-RAM Memories", MICROPROCESSORS ANDMICROSYSTEMS, December 2019 Vol. 73, Num. 1, Page 102963-102974, December 2019,

5 Athena Abdi, Alain Girault, Hamid Reza Zarandi, "ERPOT: A Quad-Criteria Scheduling Heuristic to Optimize ExecutionTime, Reliability, Power Consumption and Temperature in Multicores", IEEE TRANSACTIONS ON PARALLEL ANDDISTRIBUTED SYSTEMS, March 2019 Vol. 0, Num. 0, Page 1-18, March 2019,

6 Athena Abdi, Hamid Reza Zarandi, "A Meta Heuristic-based Task Scheduling and Mapping Method to Optimize MainDesign Challenges of Heterogeneous Multiprocessor Embedded Systems", MICROELECTRONICS JOURNAL, March2019 Vol. 87, Num. 1, Page 1-11, March 2019,

7 Shahab Shoar, Farnad Nasirzadeh, Hamid Reza Zarandi, "Quantitative assessment of risks on construction projectsusing fault tree analysis with hybrid uncertainties", CONSTRUCTION INNOVATION-ENGLAND, November 2018 Vol.19, Num. 1, Page 48-70, November 2018,

8 Athena Abdi, Masoomeh Karami, Hamid Reza Zarandi, "Lifetime Reliability Enhancement in Multiprocessor SystemsThrough a Fine-Grained System-level Approach", JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, October 2018Vol. 28, Num. 11, Page 195019-195039, October 2018,

9 Farzaneh Zokaee, Hamid Reza Zarandi, Lei Jiang, "AligneR: A Process-In-Memory Architecture for Short ReadAlignment in ReRAMs", IEEE Computer Architecture Letters, July 2018 Vol. 14, Num. 8, Page 1-4, July 2018,

10 Masoomeh Karami, Athena Abdi, Hamid Reza Zarandi, "A Cross-Layer Aging-aware Task Scheduling Approach onMultiprocessor Embedded Systems", MICROELECTRONICS RELIABILITY, April 2018 Vol. 85C, Num. 1, Page 190-197,April 2018,

11 Athena Abdi, Hamid Reza Zarandi, "HYSTERY: A Hybrid Scheduling and Mapping Approach to OptimizeTemperature, Energy Consumption and Lifetime Reliability of Heterogeneous Multiprocessor Systems", JOURNAL OFSUPERCOMPUTING, January 2018 Vol. 0, Num. 0, Page 0-0, January 2018,

12 Roghaye Mojarrad, Hamid Reza Zarandi, "Comparison and Analysis of Three Anomaly Correction Methods inEmbedded Systems", SCIENTIA IRANICA TRANSACTION D-COMPUTER SCIENCE & ENGINEERING AND ELECTRICALENGINEERING, February 2017 Vol. 1, Num. 1, Page 1-10, February 2017,

13 Shahab Shoar, Hamid Reza Zarandi, Elham Cheshmikhanikhanghah, Farnad Nasirzadeh, "Fast Fault Tree Analysis forHybrid Uncertainties Using Stochastic Logic Implemented on Field Programmable Gate Arrays: An Application inQuantitative Assessment and mitigation of Welding Defects Risk", QUALITY AND RELIABILITY ENGINEERINGINTERNATIONAL, November 2016 Vol. 0, Num. 12, Page 1-19, November 2016,

14 Saleh Fakhrali, Hamid Reza Zarandi, "Double Stairs: A Fault-Tolerant Routing Algorithm for Networks-on-Chip",JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, March 2016 Vol. 25, Num. 6, Page 1-15, March 2016,

15 Alireza Tajary, Hamid Reza Zarandi, "Using Instruction Result Locality and Re-Execution to Mitigate Silent DataCorruptions", MICROELECTRONICS RELIABILITY, March 2016 Vol. 0, Num. 0, Page 1-13, March 2016,

16 Mohammad Maghsoudloo, Hamid Reza Zarandi, "Design space exploration of non-uniform cache access for soft-error vulnerability mitigation", MICROELECTRONICS RELIABILITY, September 2015 Vol. 0, Num. 0, Page 0-0,September 2015,

17 Elham Cheshmikhanikhanghah, Hamid Reza Zarandi, "Probabilistic Analysis of Dynamic and Temporal Fault TreesUsing Accurate Stochastic Logic Gates", MICROELECTRONICS RELIABILITY, June 2015 Vol. 1, Num. 1, Page 1-1,June 2015,

18 Saleh Fakhrali, Hamid Reza Zarandi, "FXY: A Hierarchical Routing Algorithm to Balance Performance and FaultTolerance in Networks-On-Chip", JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, July 2014 Vol. 23, Num. 10,Page 1-23, July 2014,

19 Mohammad Hadi Mottaghi Khezri, Hamid Reza Zarandi, "DFTS: A Dynamic Fault-Tolerant Scheduling for Real-TimeTasks in Multicore Processors", MICROPROCESSORS AND MICROSYSTEMS, February 2014 Vol. 38, Num. 1, Page88-97, February 2014,

20 Mohammad Maghsoudloo, Hamid Reza Zarandi, "Cache Vulnerability Mitigation Using an Adaptive Cache CoherenceProtocol", JOURNAL OF SUPERCOMPUTING, February 2014 Vol. 1, Num. 1, Page 1-1, February 2014,

21 Mohammad Maghsoudloo, Hamid Reza Zarandi, "Reliability Improvement in Private Non-Uniform Cache Architectureusing Two Enhanced Structures for Coherence Protocols and Replacement Policies", MICROPROCESSORS ANDMICROSYSTEMS, December 2013 Vol. 38, Num. 6, Page 552-564, December 2013,

22 Hamid Sarbazi-Azad, Hamid Reza Zarandi, Mahdi Fazeli, "A parallel clustering algorithm on the star graph and itsperformance", MATHEMATICAL AND COMPUTER MODELLING, August 2013 Vol. 58, Num. 0, Page 880-891, August2013,

23 Fatemeh Khalili, Hamid Reza Zarandi, "A Fault-Tolerant Core Mapping Technique in Networks-on-Chip", IETCOMPUTERS AND DIGITAL TECHNIQUES, June 2013 Vol. 1, Num. 1, Page 1-1, June 2013,

24 Hananeh Aliee, Hamid Reza Zarandi, "A Fast and Accurate Fault Tree Analysis Based on Stochastic LogicImplemented on Field-Programmable Gate Arrays", IEEE TRANSACTIONS ON RELIABILITY, January 2013 Vol. 61,Num. 4, Page 1-1, January 2013,

25 Mohammad Maghsoudloo, Hamid Reza Zarandi, Navid Khoshavi Najaf Abadi, "An Efficient Adaptive Software-Implemented Technique to Detect Control-Flow Errors in Multi-Core Architectures", MICROELECTRONICSRELIABILITY, November 2012 Vol. 52, Num. 11, Page 2812-2828, November 2012,

26 Mohammad Maghsoudloo, Hamid Reza Zarandi, Navid Khoshavi Najaf Abadi, "On-line Control Flow Error Detectionand Correction Based on Monitoring both Data-flow and Control-flow Graphs", The CSI Journal on Computer Scienceand Engineering(JCSE), April 2012 Vol. 10, Num. 0, Page 10-19, April 2012,

27 Mahroo Zandrahimi, Hamid Reza Zarandi, Mohammad Hadi Mottaghi Khezri, "Two effective methods to detectanomalies in embedded systems", MICROELECTRONICS JOURNAL, January 2012 Vol. 43, Num. 1, Page 77-87,January 2012,

28 Somayeh Bahramnejad, Hamid Reza Zarandi, "Mitigation of soft errors in SRAM-based FPGAs using CAD tools",COMPUTERS & ELECTRICAL ENGINEERING, November 2011 Vol. 37, Num. 6, Page 1019-1031, November 2011,

29 Somayeh Bahramnejad, Hamid Reza Zarandi, "An adaptive method to tolerate soft errors in SRAM-based FPGAs",SCIENTIA IRANICA TRANSACTION D-COMPUTER SCIENCE & ENGINEERING AND ELECTRICAL ENGINEERING,September 2011 Vol. 16, Num. 1, Page 1-10, September 2011,

30 Mostafa Kishanifarahani, Hamid Reza Zarandi, Hossein Pedram, Ali Reza Tajary, Mohsen Raji Asad Abadi, BehnamGhavami, "HVD: horizontal-vertical-diagonal error detecting and correcting code to protect against with soft errors",DESIGN AUTOMATION FOR EMBEDDED SYSTEMS, May 2011 Vol. 16, Num. 1, Page 1-22, May 2011,

31 Hassan Ebrahimi, Morteza Saheb Zamani, Hamid Reza Zarandi, "Mitigating Soft Errors in SRAM-Based FPGAs byDecoding Configuration Bits in Switch Boxes", MICROELECTRONICS JOURNAL, January 2011 Vol. 42, Num. 1, Page12-20, January 2011,

32 Pooria Mohammadi Yaghini, Ashkan Eghbal, Hossein Pedram, Hamid Reza Zarandi, "Investigation of Transient FaultEffects in Synchronous and Asynchronous Network on Chip Router Reliability", Elsevier Journal of SystemArchitecture, January 2011 Vol. 57, Num. 10, Page 61-68, January 2011,

33 Pedram Rajabzadeh, Hamid Sarbaziazad, Hamid Reza Zarandi, Ebrahim Khodaie, Hashem Hashemi Najafabadi,Mohamed Ouldkhaoua, "Performance Modeling of n-Dimensional Mesh Networks", PERFORMANCE EVALUATION,December 2010 Vol. 67, Num. 12, Page 1304-1323, December 2010,

34 Ashkan Eghbal, Hossein Pedram, Pooria Mohammadi Yaghini, Hamid Reza Zarandi, "Designing a Fault-tolerant NoCRouter Architecture Respecting Fault Effects", International Journal of Electronics, October 2010 Vol. 97, Num. 10,Page 1181-1192, October 2010,

35 Alireza Rohani, Hamid Reza Zarandi, "Two Effective Methods to Mitigate Soft Error Effects in SRAM-based FPGAs",MICROELECTRONICS RELIABILITY, August 2010 Vol. 50, Num. 8, Page 1171-1180, August 2010,

36 Mohsen Rajiasadabadi, Behnam Ghavami, Hossein Pedram, Hamid Reza Zarandi, "Process Variation AwarePerformance Analysis of Asynchronous Circuits", Elsevier Journal of Microelectronics, March 2010 Vol. 41, Num. 2,Page 0-0, March 2010,

37 Hananeh Aliee, Hamid Reza Zarandi, Pooria Mohammadi Yaghini, "K2Router: A Low-Power and High-PerformanceRouter Design for Networks-On-Chip", The CSI Journal on Computer Science and Engineering(JCSE), March 2009Vol. 7, Num. 2, Page 8-23, March 2009,

38 Hamid Reza Zarandi, [en-name N/A], "A SEU-protected cache memory-based on variable associativity of sets", ,November 2007 Vol. , Num. 92, Page 0-0, November 2007,

39 Hamid Reza Zarandi, "Dependability evaluation of Altera FPGA-based embedded systems subjected to SEUs", ,March 2007 Vol. , Num. 0, Page 0-0, March 2007,

40 Hamid Reza Zarandi, "Hierchical Set -Associate Cache For High -Performance and Low -Energy Architecture", , June2006 Vol. , Num. 6, Page 0-0, June 2006,

41 Hamid Reza Zarandi, "A fault-tolerant cache architecture based on binary set partitioning", , January 2006 Vol. ,Num. 46, Page 0-0, January 2006,

42 Hamid Reza Zarandi, "Hierarchical Binary Set Partitioning in Cache Memories", , December 2005 Vol. , Num. 31, Page0-0, December 2005,

Conference Papers

Portal Records

1 Salar Hashemi, Amir Hajisadeghi, Hamid Reza Zarandi, Saadat Pourmozafari, "A Fast and Efficient Fault TreeAnalysis Using Approximate Computing ", 2019 15th European Dependable Computing Conference, September 2019

2 Saeed Seyedfaraji, Amirmohammad Hajisadeghi Kahdooyeh, Hamid Reza Zarandi, "TAMPER: Thermal AssistantMethod to Improve Write PERformance in STT-RAM Memories ", 27th Iranian Conference on Electrical Engineering(ICEE2019), March 2019

3 Amirmohammad Hajisadeghi Kahdooyeh, Hossein Bardareh, Hamid Reza Zarandi, "MOMENT: A Cross-Layer Methodto Mitigate Multiple Event Transients in Combinational Circuits ", Euromicro Conference on Digital System Design(DSD), August 2018

4 Saeed Seyedfaraji, Javad Talafy, Amirmohammad Hajisadeghi Kahdooyeh, Hamid Reza Zarandi, "DUSTER: DUalSource Write TERmination Method for STT-RAM Memories ", Euromicro Conference on Digital System Design (DSD),August 2018

5 Hossein Bardareh, Amirmohammad Hajisadeghi Kahdooyeh, Hamid Reza Zarandi, "A Low-Cost Soft Error TolerantRead Circuit for Single/Multi-Level RRAM-based Cross-Point Memory Arrays ", 24th IEEE International Symposiumon On-Line Testing and Robust System Design (IOLTS), July 2018

6 Maryam Hosseini, Hamid Reza Zarandi, Amir Rajabzadeh, "SDC Evaluation and Mitigation in Networks-on-Chip ", The23rd National CSI Computer Conference, February 2018

7 Mohammadreza Nakhkash, Hossein Bardareh, Farzaneh Zokaee, Hamid Reza Zarandi, "Designing a Differential 3R-2Bit RRAM Cell for Enhancing Read Margin in Crosspoint RRAM Arrays ", IEEE Nordic Circuits and SystemsConference, October 2017

8 Fatemeh Ehsani Besheli, Hamid Reza Zarandi, "Context-Aware Anomaly Detection in Embedded Systems ",Dependability and Complex Systems (DepCoS-RELCOMEX), July 2017

9 Javad Talafy, Hamid Reza Zarandi, "Soft Error Analysis of MTJ-based Logic-in-Memory Full Adder: Threats andSolution ", 23rd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS), July 2017

10 Elham Kashefi, Hamid Reza Zarandi, Ann Gordon-Ross, "Postponing wearout failures in chip multiprocessors usingthermal management and thread migration ", 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), June 2016

11 Kamran Nasiri, Hamid Reza Zarandi, "MWPF: A Deadlock Avoidance Fully Adaptive Routing Algorithm in Networks-On-Chip ", 24st Euromicro International Conference on Parallel, Distributed, Network-based Processing (PDP),February 2016

12 Maryam Ghane, Hamid Reza Zarandi, "Gate Merging: An NBTI Mitigation Method to Eliminate Critical Internal Nodesin Digital Circuits ", 24st Euromicro International Conference on Parallel, Distributed, Network-based Processing(PDP), February 2016

13 Alireza Tajary, Hamid Reza Zarandi, "An Efficient Soft Error Detection in Multicore Processors Running ServerApplications ", 24st Euromicro International Conference on Parallel, Distributed, Network-based Processing (PDP),February 2016

14 Elham Cheshmikhanikhanghah, Hamid Reza Zarandi, "Accelerating Dynamic Fault Tree Analysis Based on StochasticLogic Utilizing GPGPUs ", 24st Euromicro International Conference on Parallel, Distributed, Network-basedProcessing (PDP), February 2016

15 Roghaye Mojarrad, Hamid Reza Zarandi, "Two Effective Anomaly Correction Methods in Embedded Systems ", Real-Time and Embedded Systems and Technologies (RTES), October 2015

16 Peiman Pour Momen, Hamid Reza Zarandi, Mohammad Reskh Jahromi, "Series memristors: A hardened memorycell design against read faults ", 18th International Symposium on Computer Architecture and Digital Systems(CADS), October 2015

17 Behnaz Ranjbar, Hamid Reza Zarandi, "Accelerating MD5 Cracking Using FPGA Boards ", The 22nd IranianConference on Electrical Engineering (ICEE 2014), May 2014

18 Masoud Ansarian, Saeed Kohsari, Hamid Reza Zarandi, "Tolerating SET and SEU Errors in Networks on Chip ", The22nd Iranian Conference on Electrical Engineering (ICEE 2014), May 2014

19 Paria Darbani, Hamid Reza Zarandi, "A Reconfigurable NoC Architecture to Improve Overall Performance andThroughput ", The 22nd Iranian Conference on Electrical Engineering (ICEE 2014), May 2014

20 Mohammad Hazhir Bakhishi, Hamid Reza Zarandi, "Speeding Up Parallel Fault Simulation Using GPU-basedMulticore Processing ", 19th National CSI Computer Conference, March 2014

21 Elham Cheshmikhanikhanghah, Hamid Reza Zarandi, Hananeh Aliee, "Accelerating Fault Tree Analysis Using HW/SWCo-Design ", 59th IEEE Annual Reliability and Maintainability Symposium, RAMS, January 2014

22 Vahid Aalami-Al-Agha, Hamid Reza Zarandi, Mohammad Maghsoudloo, "A Method to Detect Control Flow Errors inARM-11-based Embedded Systems ", 18th National CSI Computer Conference, March 2013

23 Fatemeh Khalili, Hamid Reza Zarandi, "A Reliability-Aware Multi-Application Mapping Technique in Networks-on-Chip", 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, February 2013

24 Fatemeh Khalili, Hamid Reza Zarandi, "A Fault-Tolerant Low-Energy Multi-Application Mapping onto NoC-basedMultiprocessors ", 10th IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (EUC),December 2012

25 Hamed Abbasi Tabar, Hamid Reza Zarandi, Ronak Salamat, "Susceptibility Analysis of LEON3 Embedded Processoragainst Multiple Event Transients and Upsets ", The 15th IEEE International Conference on Computational Scienceand Engineering, December 2012

26 Fatemeh Khalili, Hamid Reza Zarandi, "A Fault-Aware Low-Energy Spare Core Allocation in Networks-on-Chip ", 30thNorchip Conference (Norchip), November 2012

27 Mohammad Maghsoudloo, Hamid Reza Zarandi, "Dirty Data Vulnerability Mitigation by means of SharingManagement in Cache Coherence Protocols ", 25th IEEE International Symposium on Defect and Fault Tolerance inVLSI (DFT), October 2012

28 Mona Nasehi Osgooi, Ali Jahanian, Hamid Reza Zarandi, "Modeling, Evaluation and Mitigation of SEU Error in Three-Dimensional FPGAs ", 16th symposium on Computer Architecture and Digital Systems CADS2012, May 2012

29 Ronak Salamat, Hamid Reza Zarandi, "Fault-Tolerant Assessment and Enhancement in the Reconfigurable Network-on-Chip ", 16th symposium on Computer Architecture and Digital Systems CADS2012, May 2012

30 Mohsen Rajiasadabadi, Behnam Ghavami, Hamid Reza Zarandi, Hossein Pedram, Mehdi B. Tahoori, "Assessment ofNano-Scale Muller C-elements Under Variability Based on a New Fault Model ", 16th symposium on ComputerArchitecture and Digital Systems CADS2012, May 2012

31 Navid Khoshavi Najaf Abadi, Hamid Reza Zarandi, Mohammad Maghsoudloo, "Two Control-flow Error RecoveryMethods for Multithreaded Programs Running on Multi-core Processors ", 28th International Conference onMicroelectronics (MIEL), May 2012

32 Mohammad Maghsoudloo, Hamid Reza Zarandi, Navid Khoshavi Najaf Abadi, "A Low-Cost Software-ImplementedError Detection Technique ", International Symposium on Electronic System Design (ISED),, December 2011

33 Hananeh Aliee, Hamid Reza Zarandi, "A Fault-Tolerant, Dynamically Scheduled Pipeline Structure for ChipMultiprocessors ", 30th International Conference on Computer Safety, Reliability and Security (SAFECOMP),September 2011

34 Mohammad Maghsoudloo, Hamid Reza Zarandi, Saadat Pourmozafari, Navid Khoshavi Najaf Abadi, "Soft ErrorDetection Technique in Multi-threaded Architectures Using Control-Flow Monitoring ", 14th Euromicro Conference onDigital System Design, Architecture, Methods and Tools (DSD), August 2011

35 Hananeh Aliee, Hamid Reza Zarandi, Ali Reza Tajary, "CPU Aware Process-Level Redundancy to Tolerate Faults inMulti-cores ", 9th IEEE International Conference on High Performance Computing & Simulation (HPCS), July 2011

36 Ronak Salamat, Hamid Reza Zarandi, "Fault-Tolerance Assessment and Enhancement in SoCWire Interface: ASystem-On-Chip Wire ", 17th IEEE International On-Line Testing Symposium (IOLTS), July 2011

37 Navid Khoshavi Najaf Abadi, Hamid Reza Zarandi, Mohammad Maghsoudloo, "Control-Flow Error Recovery UsingCommodity Multi-core Architecture Features ", 17th IEEE International On-Line Testing Symposium (IOLTS), July2011

38 Mohsen Raji Asad Abadi, Behnam Ghavami, Hamid Reza Zarandi, Hossein Pedram, "Assessment of Nano-scaleAsynchronous PCFB Circuits under Extreme Process Variation ", Asia Symposium on Quality Electronic Design(ASQED), July 2011

39 Navid Khoshavi Najaf Abadi, Hamid Reza Zarandi, Mohammad Maghsoudloo, "Control-Flow Error Detection UsingCombining Basic and Program-Level Checking in Commodity Multi-core Architectures ", Symposium on IndustrialEmbedded Systems (SIES), June 2011

40 Hananeh Aliee, Hamid Reza Zarandi, "An Efficient, Dynamically Adaptive Method to Tolerate Transient Faults inMulti-core Systems ", 13th European Workshop on Dependable Computing (EWDC), May 2011

41 Iman Faraji, Moslem Didehban, Hamid Reza Zarandi, "Analysis of transient faults on a MIPS based dual coreprocessor ", , February 2010

42 Hassan Ebrahimi, Morteza Saheb Zamani, Hamid Reza Zarandi, "A Decoder-Based Switch Box to Mitigate Soft Errorsin SRAM-Based FPGAs ", IEEE Asia and South-Pacific Design Automation Conference, January 2010

43 Hamid Reza Zarandi, "A new CLB architecture for tolerating SEU in SRAM based FPGAs ", , December 2009

44 Hamid Reza Zarandi, "New switch box architecture for SEU Detection in SRAM based FPGAs ", , December 2009

45 Mahroo Zandrahimi, Hamid Reza Zarandi, "New switch box architectue fo SEU detection in SAM based FPGAs ", ,December 2009

46 Hamid Reza Zarandi, "A SEU avoidance method in placement and routing of SRAM based FPGAs to mitigate softerror effects ", , November 2009

47 Behnam Ghavami, Hamid Reza Zarandi, Hossein Pedram, "Secure crypto chips against hardware fault attacks ", ,November 2009

48 Behnam Ghavami, Hamid Reza Zarandi, Hossein Pedram, "High level fault simulation methodology for QDI templatebased asynchronous circuits ", , November 2009

49 Behnam Ghavami, Hamid Reza Zarandi, "Diagnosis of faults in template based asynchronous circuits ", , November2009

50 Somayeh Bahramnejad, Hamid Reza Zarandi, "A fault tolerant combined method for SRAM based FPGAs ", ,November 2009

51 Behnam Ghavami, Hamid Reza Zarandi, Hossein Pedram, "Testing and diagnosis of faults in template basedasynchronous circuits ", , October 2009

52 Hosein Sadeghi, Hamid Reza Zarandi, "Power aware branch target prediction using a new BTB architecture ", ,October 2009

53 Hamid Reza Zarandi, Hossein Pedram, "Process variation aware performance analysis of asynchronous circuitsconsidering spatial correlation ", , September 2009

54 Seyyed Amir Asghari Tochae, Hamid Reza Zarandi, Hossein Pedram, "A fault injection attitude based on backgrounddebug mode in enbedded systems ", , July 2009

55 Hamid Reza Zarandi, "An investigation of fault tolerance behavior of 32 bit DLX provessor ", , June 2009

56 Hossein Pedram, Hamid Reza Zarandi, "Fault injection based evaluation of a synchronous NoC router ", , June 2009

57 Hamid Reza Zarandi, "Mitigating and tolerating SEU effects in switch modules of SRAM based FPGAs ", , April 2009

58 Alireza Rohani, Hamid Reza Zarandi, "An analysis of fault effects and propagations in AVR microontroller AT mega103 L ", , March 2009

59 Seyyed Amir Asghari Tochae, Mehdi Khademi, Abolfazle Ansarinia, Hamid Reza Zarandi, "An innovative faultinjection method in embedded systems via background debugd mode ", , January 2009

60 Ashkan Eghbal, Hamid Reza Zarandi, "Fault tolerance assessment of PIC microcontroller based on fault injection ", ,January 2009

61 Hamid Reza Zarandi, "Multiple SEU tolerance in TUTs of FPGAs using protected Schemes ", , January 2008

62 Hamid Reza Zarandi, "Matrix codes multiple bit upsets tolerant method for SRAM memberies ", , January 2007

Awards & Honors

# title Date

1 Distinguished professor, Dept. of Computer Engineering, Amirkabir Univ. of Technology 2014

Professional Memberships

# Professional memberships Explanations

1 Head of IoT Center of Excellence.

2 Member of Cyber-Physical Systems Society of Iran

3 Member of Computer Society of Iran

4 Member of IEEE

5 Chair of DADS Research Laboratory

Taught Courses

# Course title Description Headlines Date

1 ReliableSystemsDesign

This course provides knowledge on the design of reliable and fault-tolerantcomputer systems, defenitions of dependability parameters, their evaluations andpromoting methods will be provided.

Spring2022

2 ComputerArchitecture

In this course, students will be familiar with computer system architecture andorganizations, memory units and IO devices.

Spring2022

3 Testing andTestableDesign

Introduction to the concepts and techniques of VLSI (Very Large Scale Integration)design verification and testing, details of test economy, fault modeling andsimulation, defects, Automatic Test Pattern Generation (ATPG), design fortestability, Sca

Fall2021

4 OperatingSystems

Design and implementation of operating systems. Topics include processsynchronization and interprocess communication, processor scheduling, memorymanagement, virtual memory, interrupt handling, device management, I/O, and filesystems

Fall2021

5 ComputerArchitecture

In this course, students will be familiar with computer system architecture andorganizations, memory units and IO devices.

Fall2021

6 ComputerArchitecture

In this course, students will be familiar with computer system architecture andorganizations, memory units and IO devices.

Spring2021

7 ComputerArchitecture

In this course, students will be familiar with computer system architecture andorganizations, memory units and IO devices.

Spring2021