SEQUENTIAL LOGIC DESIGN

Adriana AmézquitaCesar RodríguezDavid Zamora

Sequential logic

Sequential IM logic design

A sequential system is formed by a combinational circuit and a memory element.Memory is responsible for storing the system history.

the output of the system depends not only on the input system also history

Description VHDL of sequential logic

EVENT : It is used to describe a fact or a sign.describes the Edge triggering clock.“0” and “1”, “1” and “0”.

System types

Synchronous: Dependent pulse clock

Asynchronous: Dependent on the order and time when the signal is applied

Bistables It has feedback capability connects input

outputAsynchronous: The output changes state when the input changes.Synchronous: Output changes to a clock pulse input.Flank rice “1”Flank drop “0”

Types of bistable Regardless of the time of activation

Bistables S-R Asynchronous:

Bistables S-R Asynchronous active at high level

FLIP-FLOP rising flank

Modeling VHDL initialization signal Initialization asynchronous.

Fli-flo D enable rising flank with reset

Fli-flo D enable rising flank with clear

Storage registers It has a structure similar to the flip –flop.The difference is that stores a bit vector to a single bit.

GRACIAS POR SU

ATENCION