consistent model for the hot-carrier degradation in n-channel and p-channel mosfets

2194 IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 35, NO. 12, DECEMBER 1988

Consistent Model for the Hot-Carrier Degradation in n-Channel and p-Channel MOSFET’s

PAUL HEREMANS, RUDI BELLENS, GUIDO GROESENEKEN, AND HERMAN E. MAES, MEMBER, IEEE

Abstract-A consistent model for the degradation of n-channel and p-channel transistors under hot-carrier injection conditions is presented. This model is derived using the charge-pumping technique for the evaluation of the interface characteristics, in combination with the behavior of the drain and the substrate currents after degradation. It is demonstrated that for n-channel transistors the degradation is mainly caused by the generation of interface traps. Only in the region of hole injection ( Vg = V , ) the degradation is dominated by the trapped holes, which mask the effect of the generated interface traps. It is found that the degradation of p-channel transistors, although completely different at first sight, occurs by the same mechanisms. For this case, the degradation is caused by trapped negative charge, which masks the influence of the interface traps. The latter are nevertheless generated in comparable amounts as in n-channel transistors. Based on these in- sights, improved procedures for accelerated lifetime experiments are proposed for both channel types. Finally, the peculiar degradation behavior of n-channel transistors under alternating injection conditions is discussed and fully explained based on the static stress degradation model.

I. INTRODUCTION HE influence of hot-carrier injection on the perfor- T mance of MOS transistors has been studied exten-

sively during the last decade. With the ever shrinking device geometries, this problem will hore and more become a limitation on the reliability of the devices, and therefore increased attention is being paid, not only to the modeling of the hot-carrier phenomenon, but also to the physical mechanisms that lie behind the corresponding device degradation [1]-[12].

Despite the large efforts spent during the last few years to understand the physical origins of transistor degradation, no unanimous agreement exists on this matter. In particular, the exact nature of the degradation and its correlation with the injection conditions are still the subject of discussion, and a complete and consistent model that describes the degradation of n-MOS as well as p-MOS transistors has not yet been obtained.

One of the main reasons why considerable disagreement still exists concerning the physical mechanisms of hot-carrier degradation is believed to be the lack of a reliable and sensitive technique to evaluate the damage at

Manuscript received April 13, 1988; revised July 10, 1988. P. Here- mans is a research assistant of the Belgian National Fund for Scientific Research. This work was supported by BTMC Alcatel within an IWONL project.

The authors are with the Interuniversity Micro-Electronics Center (IMEC). Kapeldreef 75, B-3030 Leuven, Belgium.

IEEE Log Number 8823785.

the interface caused by injection. Indeed, most of the studies have mainly based their conclusions about the nature of the degradation on the shifts in current characteristics of the devices. However, shifts in threshold voltage and changes in transconductance, subthreshold slope, or substrate current only indirectly reflect the physical damage at the interface. Moreover, since this damage is very localized, the interpretation of the analysis is complex and hard to verify, and the explanations given are mostly based on speculation instead of on experimental evidence.

Recently, it has been shown that the charge-pumping technique can provide more precise and additional information on the interface properties in MOS transistors [4], [8], [12]-[16]. Moreover, as is shown in [14], this technique is capable of independently providing the amount of interface traps generated during the injection and the sign and the amount of the charges that have been trapped in the gate dielectric, even for the case of localized injections.

In the present paper, the degradation mechanisms, related to hot-carrier injection, are studied for both n-chan- ne1 and p-channel transistors, using the charge-pumping technique as the primary evaluation tool. By taking into account the power and the limitations of the charge- pumping evaluation, and by making correlations between the results of charge pumping and those of the conventional evaluation techniques, a consistent picture of the degradation of n-MOS and p-MOS transistors under static and alternating stress conditions is obtained.

11. EXPERIMENTAL CONDITIONS AND DEVICES Most of the devices used in this study are n-channel and

p-channel MOS transistors, fabricated by several suppliers in a 2-pm n-well CMOS process. Some experiments were carried out on transistors from an in-house 1.25-pm n-MOS technology. The conclusions drawn in this study are thus verified to be generally valid, and independent of the quality of the technology.

The n-channel transistors of the 2-pm n-well CMOS process had a channel length ranging from 1.75 to 3.0 pm, a width ranging from 25 to 7500 pm, and an oxide thickness tox of about 28 nm. The p-channel transistors of this process had an effective channel length ranging from 1.75 to 3.0 pm, a width ranging from 25 to 200 pm, and to, = 28 nm. The n-MOS transistors of the 1.25-pm process had an effective channel length of 1.0 to 1.5 pm, W = 20 pm, and an oxide thickness of 24 nm.

0018-9383/88/1200-2194$01 .OO O 1988 IEEE

HEREMANS et al.: CONSISTENT MODEL FOR HOT-CARRIER DEGRADATION

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The devices were stressed at different voltage conditions, depending on the channel length and the technology. Drain voltages ( Vd) ranging from 6 to 11 V and gate voltages ( V, ) ranging from 0.5 to 1 1 V were used. The substrate voltage ( V s u b ) always was 0 V, except for the constant current stress experiments in Section VI-B .

111. EVALUATION TECHNIQUES It is well known that ZhVg characteristics are affected

by hot-carrier stress, and they therefore are commonly used to evaluate the damage caused by injection. How- ever, their correct interpretation is not straightforward because of the strongly spatially nonuniform nature.of the degradation. Indeed, the definition of MOSFET threshold voltage loses a great deal of its physical meaning for a channel with nonuniform oxide charge and interface trap distribution. Moreover, the magnitude of the change in an ZhV, characteristic depends on the operation mode (reverse or normal) for which it is recorded. Although com- puter simulations [6], [17] are useful to understand the influence of nonuniformly distributed Q,, or D,, on the current characteristics of MOS transistors, they cannot be used to unambiguously prove the presence and determine the amount of Q,, and Dit in real devices. Therefore, there exists a need for an evaluation tool that could provide direct information concerning nonuniform distributions of interface traps and oxide charges in MOS transistors.

The charge-pumping (CP) technique [4], [ 141 consists of applying a pulse train with constant amplitude ( A V,) and increasing base level (vba, , ) at the gate of a MOS transistor, while a reverse bias ( V,) is applied at the source and drain. For an n-MOS transistor, the substrate current,

' referred to as charge-pumping current (I,,), recorded as a function of increasing Vb,,,, typically starts from zero level, then abruptly increases at Vba, = V, - A V, to reach a saturation level, and finally drops back to zero at Vb,,,

= V,. The saturation level of Icp is a measure for the interface trap density Dit, while the transition edges of the characteristic yield V, and V,. When a local degradation is induced in the channel, the CP characteristic of the transistor simply is the sum of the characteristics of the degraded and of the nondegraded parts of the channel. An increase in the saturation level of Icp after stress therefore indicates a local or uniform increase of Dit. A distortion or a shift of the edges of the CP characteristic toward more positive Vb,,, is indicative for a localized or a uniform negative oxide charge, respectively, and analogously a distortion or a shift of the edges toward more negative Vba,, is indicative for localized or a uniform positive oxide charge, respectively. Also, in the case of a very localized degradation, the difference between the CP characteristics after and before degradation represents the characteristics of the degraded part of the channel, and independently provides its local amount of interface traps and its local Vt and V,.

In this study, three characterization techniques are used to study the degradation of the devices.

1) Threshold voltage shifts and transconductance deg-

radation are determined at a fixed current of 0.2 pA/pm width and a drain voltage of 5 V, measured in the reverse operation (Le., by interchanging the source and drain after stress).

2) Charge pumping was used, in the way described in [ 141. This allowed us to derive consistent explanations for the shifts in the ZhV, curves in terms of interface trap creation and buildup of charges.

3) Finally, changes in the substrate current (Isub) and in the multiplication factor ( M = Is&,/Id), measured in the normal and in the reverse mode, were used to get additional information on the changes of the lateral electric field at the drain.

I v . DEGRADATION OF n-CHANNEL TRANSISTORS The amount of degradation during hot-carrier aging

strongly depends on the applied stress conditions. The gate currents corresponding to these injection conditions have been studied in [ 181-[22]. In the high gate voltage region (V , = V d ) , electrons are shown to be injected into the oxide and can be measured as a gate current [ 181. In the low V, region, a small hole gate current is observed [21]-[22]. In the intermediate region (V , = Vd/2), the substrate current is maximal, and both electrons and holes can be injected into the gate oxide. In the next para- graphs, it will be shown that the damage and the degradation mechanisms are different for each of these operating regions. A. Charge-Pumping Measurement Results

In Fig. 1, the CP results are shown for several n-chan- ne1 transistors, stressed for 1800 s at vd = 6.5 V and gate voltages ranging from 0.6 to 5 V. The dashed line in the figure is the CP characteristic of the transistors before stress. The other curves are the CP characteristics, rela- tive to the virgin one (i.e., the difference between the CP curve after stress and the CP curve of the virgin device), for the different transistors after stress. From this figure, three main conclusions can be drawn:

1) In all cases, interface traps are generated. However, the highest number of interface traps is created in the region of maximum substrate current ( V, = Vd/2), and not in the region of maximum electron gate current (V, = V d ) . By disconnecting the drain during the CP measurement, it can be demonstrated that the interface traps are generated at the drain side of the channel [14].

2) Since the edges of the post-stress AI,, curves show no shift toward more positive gate pulse base lcvels under any stress condition, at first sight no negative charge ap- pears to be built up during any of the degradations. More- over, from the shift of the edges of the post-stress AIcp curves toward more negative pulse base levels, one could even conclude positive charge to be present at the interface or in the oxide after most of the stress cases. As has been shown in [ 141, however, interface traps, located very close to or inside the drain junction in an n-MOS transistor, generate CP currents at more negative Vb,,, than the interface traps located in the true channel because the local threshold and flat-band voltages in the proximity of

2196 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 35. NO. 12. DECEMBER 1988

50

30

10

-8 -6 - 4 -2 0

Base level [ V I signals (AIc , , is given by the solid lines) as

compared to the original I<,, curve (dashed line), for different channel hot-carrier stress conditions. Transistor parameters: Le, = 1.5 pm, W = 20 pm, r,,, = 24 nm.

Fig. 1. Increase of the

the drain are lower than in the channel. Therefore, at least part of the shift of the edges of the post-stress AZ,, curves toward more negative base level voltages is merely to be attributed to the proximity of the drain, and not to the buildup of positive charges. This is typically the case for stresses at medium and high gate voltages (i.e., Vg 2 Vd/2). As a result, the eventual presence of a relatively small negative oxide charge ( Q < 10" cm-2) cannot be ruled out after the stresses at V, 2 Vd/2. Indeed, the shift toward more positive V,,,,, which is expected for such a charge, would be compensated for by the shift of the post- stress AZcp curve to more negative Vb,,, due to the proximity of the drain 1141.

3) For stresses at V, < Vd/2 (and especially at V, = V,), where holes are injected into the oxide, the rising edge and falling edge of the post-stress A&,, curves ex- hibit a clear shift toward more negative V,,,,, as compared to the edges of the CP curve of the virgin device. This marked shift cannot solely be explained by the proximity of the drain [14]; therefore, we conclude a net positive charge to be present after stress. The curve for V, = 0.6 V even becomes slightly negative for V,,,, = - 1 V, and has a corresponding hump near Vb,,, = -6 V. This indicates that part of the interface traps of the virgin device contribute to the CP curve at a reduced flat-band and threshold voltage after stress. This proves the presence of positive charge, further evidence of which is given below. As discussed in [4], the net positive charge can be caused by trapped holes or by donor-type interface traps. How- ever, it was found that there is no relationship between the amount of interface traps and the amount of positive charge.

In order to get more information concerning the exact nature of the observed distortion of the CP edges for the latter case, an Tdditional experiment was carried out 141, which is illustrated on Fig. 2. The dotted line is the CP measurement of a virgin 1-pm n-MOS transistor. The curve labeled "h'inj - virgin" is the difference between the CP curve after hot-hole injection ( V, = 1 V, Vd = 6 V, t = 1800 s ) and the virgin curve. The characteristic "h'inj + e-inj - virgin" is the difference between the

0 -8 -6 -4 -2 0

Base level [VI Fig. 2. Increase of the I , signals after channel hot-hole injection (h'inj - virgin) and after subsequent channel hot-electron injection (h'inj + e-inj - virgin), as compared to the charge-pumping signal for the virgin device. LeW = 1.0 pm, r,, = 24 nm. The channel hot-hole stress is done at Vd = 6.0 V, Vg = 1.0 V during 1800 s; the electron injection at Vd = Vg = 6.0 V during 30 s.

CP current after a brief electron injection ( V, = 6 V, V, = 6 V, t = 30 s ) subsequent to the hole injection, and the characteristic of the virgin device. As can be seen on the figure, the AZcp curve after hole injection has its transition edges located at substantially more negative base level values than the original CP curve. After electron injection, the transition edges of the AZ,, curve shift back toward the ones of the virgin device. However, no significant change in interface trap density is detected after this injection. From this experiment, three conclusions can be drawn.

1) Since the negative shift of the curve ''h'inj - virgin" with respect to the virgin curve can be greatly removed by an electron injection, this shift must be due to positive charge and not to the fact that the generated interface traps are located very near or inside the drain. For the same reason, the positive charge is mainly due to holes trapped in the oxide, and not to the eventual donor-like nature of the created interface traps.

2) Since the oxide field near the drain during short electron injection is very small ( V , = V d ) , detrapping of these holes during this injection is very unlikely. This proves that the compensation of the positive charge (about 2 x 10" cm-2 over a supposed degraded channel portion of 0.1-pm length by 20-pm width) is due to trapping of the injected electrons on the trapped holes.

3) Despite the trapping of electrons on the previously trapped holes, no significant increase in the number of interface traps is observed (only 1 x 10" cm-2/eV over 0.1 pm by 20 pm). It was found, from numerous other similar experiments, that only 5 to 10 percent of the compensated holes are converted into interface traps by the subsequent electron injection. More experiments, using alternating injection conditions, will be discussed in Sec- tion VII.

The experiments of Figs. 1 and 2 directly evidence the interface trap generation at the drain and hole trapping for certain hot-carrier stress conditions. The maximum increase of the CP current ( A Zcp ) is a measure for the gen-

HEREMANS et a[.: CONSISTENT MODEL FOR HOT-CARRIER DEGRADATION 2197

erated interface traps, while the portion of the negative shift of the CP transition edge that can be compensated by a subsequent short electron injection ( A Vcp in Fig. 2 ) is a measure for the hole trapping. Negative charge generation (acceptor-type interface traps or electron trapping) could not be evidenced from these CP measurements, although its presence in small densities ( < 10" cm-*) cannot completely be excluded.

B. Experimental Degradation Characteristics In Fig. 3, the results of the CP measurements ( A Icp and

A Vcp as defined above) are compared to the degradation of the current characteristics ( A V, ) for several stress conditions. A current decrease is plotted as a positive degradation, a current increase is plotted as negative. The curves are normalized to their maxima, indicated in the figure caption. The following conclusions can be drawn from this figure.

1) For the case of hole injection ( V, = K), the shift of the threshold voltage is negative. This is consistent with the results of the CP measurement, where a net positive charge is observed ( A Vc! < 0 V ). This positive charge leads to a channel shortening, and consequently a (usually small) increase of the transistor current. So for the case of V, = V,, the changes of the I d - l / , curves are mainly caused by hole trapping at the drain.

2 ) When going from V, 5: V, to the region where the substrate current is maximal, the positive charge gradually disappears and the threshold voltage shift changes sign. Since no significant electron trapping could be observed from the CP measurements, it is concluded that the positive AV, is caused by the generated interface traps. These interface traps can affect the transistor current measured in reverse mode in two ways. Firstly, an increase of Di, can degrade the channel carrier mobility and thus increase the channel resistance. Secondly, if the interface traps generated in the upper half of the bandgap are of acceptor-type (Le., negatively charged or neutral depending on their occupancy), their negative charge can decrease the number of channel carriers, which also increases the channel resistance [6] .

3) The peak of the interface trap generation does not coincide with the peak of the threshold voltage shift. This can be understood by the fact that the threshold voltage shift is determined by both the generated interface traps and the presence of fixed charge. At the peak of the interface trap generation, a significant amount of positive charge is present at the drain. The increase of channel resistance, caused by the interface traps, is then partly compensated by the positive charge due to trapped holes. Therefore, the peak of ADi, is always shifted to lower gate voltages as compared to the peak of A V,. The latter is known to be more or less coinciding with the peak of the substrate current [2], [3], while the former is located in the gate voltage regian where both electrons and holes are injected into the oxide [4]. It is also important to notice that the threshold voltage shift can be zero, although a large number of interface traps is generated, while some '

0.0

-0.5

-7 .0L' ' i ' ' I " ' I ' ' ' ' ' ' " 0 1 2 3 4 5 6 7 8

vi2 [VI Fig. 3 . Plot of A V,/AV,, , , , , A V, /A Vcp,,max and AI, /AI , max versus

gate bias applied during stress. The translstors and stress conditions are the same as for Fig. 1 . The maximum changes are: A V,.,, = 15 mV; A V,.,, = 1.24 V; AIcp,mx/Icp, virgin = 250 percent.

positive charge is trapped. These effects illustrate that re- lying only on current characteristics can lead to erro- neous conclusions about the degradation mechanism.

4) For the region of high electron injection ( V, = V d ) , the threshold voltage shift decreases drastically with increasing V,, but remains positive. The interface trap generation also decreases. For this region, the degradation may be caused by a combination of interface trap generation and electron trapping. Indeed, although no electron trapping could be detected from the CP measurements for the used stress times, some electron trapping above the drain cannot be excluded. This will be treated further on in Section IV-D.

In conclusion, by combining the CP measurement results and the results from the conventional evaluation techniques, it can be proven unambiguously that interface trap generation is the main cause for the shifts in the current characteristics in the region of maximum degradation. For low gate voltage stress conditions ( V, < v d / 2 ) , hole trapping also occurs. It induces a lowering of the channel resistance, which partly compensates the increase of the channel resistancq due to the generation of fast interface traps. In the region of very low V,( V, = V t ) , the effect of the hole trapping clearly dominates, and a net current increase is observed. As will further be demonstrated in Section VII, it is important to bear in mind that a large amount of interface traps is still generated during channel hot-carrier stresses at V, < VdId/2. However, its influence on the Zd-Vg curves is "masked" because the channel region in which the interface traps are generated has become an extension of the drain due to the presence of a large amount of holes locally trapped in the gate oxide. If the interface traps are of acceptor-type, the density of the positive trapped charge has to exceed the density of the generated interface traps to achieve the masking. On the other hand, the effect of donor-type interface traps, which can only affect the channel carrier mobility, could be masked by a relatively small number of positive oxide charges.

C. Mechanism of Integace Trap Generation Since the main degradation mechanism due to hot-car-

rier injection is interface trap generation, eventually com-

.

2198 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 35, NO. 12, DECEMBER 1988

pensated by hole trapping, the question arises as to which mechanisms cause the interface trap generation. Again a lot of controversy is found in the literature. Several studies attribute the interface trap generation to electron injection [2]; others conclude that hot holes are the responsible carriers [12]. Lai [23] suggested that interface traps are generated by a two-step process, in which an electron recombines with a previously trapped hole, leading to the creation of an interface trap. This model is also adopted by Hofmann et al. [3]. In order to clarify this point, experiments aiming at separating the role of hot electrons and hot holes were performed [8].

For the case of channel hot-carrier injection in n-MOS transistors, it is difficult to separate the role of electrons and holes in the generation of interface traps because both types of carriers are injected into the gate oxide during stresses where a large amount of interface traps are generated ( Vg < Vd/2). To separate the role of electrons and holes in the creation of interface traps, we made use of drain-avalanche stresses instead of channel hot-carrier stresses. In this type of experiments, the drain of a MOS transistor is reverse biased without generating avalanche multiplication, while the source is left floating, and the substrate is grounded. When a small accumulation voltage is then applied at the gate, the drain diode is avalanched locally near the interface underneath the gate [24], [25]. As a result, some majority carriers at the drain can acquire sufficient energy to overcome the Si-Si02 barrier and are injected into the gate oxide. In this way, a local hole (electron) injection into the gate oxide can be achieved in an n-MOS (p-MOS) transistor.

The CP characteristics of several batches of n-MOS and p-MOS transistors submitted to this type of drain avalanche stresa were analyzed. The stresses were kept stort (tstress = 100 s ) in order to assure that the injection condition did not change too much during the experiment by the buildup of the oxide charge. A typical result of these experin its is ~ 'ven in Fig. 4, where the CP characteristics af: r di ,in avalanche injection are shown. From the distortion of the edges of the CP curves ( A V c p ) , the amount of charge trapped in the gate oxide was derived, taking into account the proximity effect of the drain mentioned in Section IV-A, and assuming that the carriers are trapped very near the injecting interface. The ratio of the number of carriers trapped in the oxide during stress to the number of carriers injected during that period gives the trapping efficiency R,. Therefore, R, can be written as

'

where Cox is the oxide capacitance per unit area, Zg is the measured gate current, and Ainj is the injection area.

Using Ainj = W X 0.1 pm [15], it is obtained that 0.03 < R, < 0.10 for holes and R, = 3 x for electrons. The R, value of the hole injection cannot be evaluated ac- curately because of the inaccuracy in the measurement of the extremely small hole gate currents in n-MOS transis-

30 1000s

- 1 2 - 8 - 4 0

Base level [VI (a)

15 1000s

10 a E $ 5

n - - 1 0 - 5 0

Base level [VI (b)

Fig. 4. IC, characteristics before (virgin) and after (100 and 1000 s) drain- avalanche stresses on n-MOS (a) and p-MOS (b) transistors with Le,, =

2.4 pm, W = 200 pm and r,, = 28 nm. The stress conditions are Vd = 10.5 V, V, = -2.0 V, Vsub = 0 V, and source floating for the n-MOS, and V, = -10.5 V, V, = 1 V, Vsub = 0 V, and source floating for the p-MOS.

tors. Nevertheless, the values obtained here are very comparable to those found in the literature [25] , [26]. From the increase of the amplitude of the CP signals after stress, and assuming again a degraded channel length of 0.1 pm, the ratio

has been determined both for electrons and holes. Ri is a measure for the efficiency of a certain type of carrier to generate interface traps. From our experiments, Ri,holes = 4 X lop3 eV-' and Ri,elect,,,ns = 2 X eV-'. There- fore, it can be concluded hot-hole injection is about 2000 times more efficient than electron injection for generating interface traps. This value of course is a rough approxi- mation for the efficiency of electron injection versus hole injection for the interface trap generation process because the gate currents were assumed to remain constant during the 100 s of the stress. Repeating the experiment on other samples originating from different technologies, however, systematically yielded values for Ri, holes /Ri,electrons between lo3 and lo4, depending on the gate oxide quality.

In conclusion, these gated diode experiments give a strong indication of the importance of hot-hole injection in the mechanism of interface-trap generation. Further evidence for the role of hot holes in channel hot-carrier aging of n-MOS devices will be given in Section VI-A.

HEREMANS et al. : CONSISTENT MODEL FOR HOT-CARRIER DEGRADATION 2199

D. Additional Experimental Evidence for the Degradation Model

In order to get additional information about the degradation mechanisms in the different regions of operation, the time dependences of the multiplication factor, A Vt and A Icp were monitored during stress. The multiplication factor M is a measure for the electric field in the channel at the drain, and it does not depend on the amount of carrier supply. Fig. 5 shows the variation of M, measured in normal operation (drain and source in their normal role) during stress, for stresses at V, = 8.5 V, and several V,. Fig. 6 shows the shift of Vt (measured in the inverse operation) together with the increase in the CP current as a function of the stress time under similar conditions. From this experiment, the conclusions from the previous para- graphs are confirmed.

1) During the stress at V, = 3 V, i.e., around the maximum of the substrate current, the substrate current decreases. The channel current, however, decreases at the same rate. Therefore, the multiplication factor almost remains constant. This means that, during the stress, the lateral electric field does not change, which confirms that no significant charge trapping (electrons or holes) occurs for this stress condition. Indeed, the degradation was already concluded to be due to an increase of interface traps. The influence of this interface trap generation on the multiplication factor is, however, not very clear and might be caused by mobility degradation effects or by the charges in the interface traps. In order to clarify this, one has to examine the complete characteristics of the multiplication factor and the substrate current as a function of gate and drain voltage after stress. This will be further discussed in Section IV-E. In Fig. 6, it can be seen that the threshold voltage shift is logarithmic in time and can be ex- pressed as

AV, = A - t" (3)

where n has a value of about 0.7, in agreement with previous reports [l], [2], [ll]. This value of 0.7 seems to be typical for the mechanism of interface trap generation, and is also found from other degradation experiments [27]. Hu et al. demonstrated that the slope for interface trap generation is expected to be between 0.5 (diffusion limited) and 1 (reaction limited) [2]. Moreover, the increase of the CP current as a function of time is also logarithmic, again with a slope n of typically 0.5 to 0.7, as becomes clear from Fig. 6.

2) During the stress at V, = 0.8 V, Le., around the maximum of the hole injection current, the multiplication factor decreases with stress time. Such a decrease corresponds to an effective increase of the gate voltage and thus a net positive oxide charge at the drain. This is still in agreement with the results of Sections IV-A and IV-B, where it was concluded that holes are trapped under these conditions. For this case the CP current increases with a slope of about 0.5. The threshold voltage on the contrary decreases with time with a slope of about 0.2, and a sat-

1.1 I

6 4 1.0

vg = 3v E B 0.9

d Vg = 0.8V

.. 3

0 250 500 750 1000 1250 1500

Time [s] Fig. 5 . &,,/Id, normalized to the initial value, during stress at v d = 8.5

V and three values of V,, for n-channel transistors W = 25 pm, Le, = 2.1 pm, to, = 28 nm.

1000 & m e /AVt/*lOO[mV]

Time [s] Fig. 6. Behavior of A V, and of AIcp as a function of stress time. Transistor

parameters: LCff = 2.4 pm, W = 100 pm, z,, = 28 nm. The stresses are performed at V, = 7.5 V, and various V,: 0 and are for V, = 0.7 V; A and A are for V, = 3.0 V; 0 and 4 are for V, = 5.0 V.

uration effect is observed for longer times. From these different time dependences one can conclude that the interface trap generation is not responsible for the threshold voltage shifts in this region, for the stress times used in this study. The slope of 0.2 and the saturation of AV, seem to be typical for the trapping mechanism and will also be found in Section V for the case of p-channel transistors.

3) During the stress at V, = 8.5 V, Le., around the maximum of the electron gate current, M increases with time. This corresponds to an effective decrease of the gate voltage, which might be indicative for electron trapping or acceptor-type interface trap generation. Also mobility degradation cannot be excluded because it causes an increase in the local channel resistance, and consequently of the lateral electric field. However, the slope of the threshold voltage shift is again about 0.2, whereas the CP current increases with a slope of about 0.5 to 0.6. There- fore, the interface trap generation obviously is not corre- lated to A V,. The behavior of A Vt is most probably caused by electron trapping, which is confirmed by the saturation observed after lo00 s. How soon this saturation occurs, or whether it occurs at all, probably depends on the quality of the gate oxide. It has indeed been reported in the literature [28] that, instead of saturating, the rate of the V, shift can gradually increase, becoming comparable to the rate of the interface trap generation. This was ex-

2200 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 35, NO. 12, DECEMBER 1988

plained by the fact that trapped electrons have the same effect as a decrease of the gate bias during stress. There- fore, after a very long time, the transistor operation region can shift from Vg = Vd to a lower effective Vg, where the increase of the interface traps is the dominant effect on A V,.

E. Mobility Degradation or Acceptor Type Interface Traps

In Section IV-B, it was shown that, in the region of maximum degradation, the increase of the channel resistance is related to the generation of interface traps. This can be explained by two mechanisms. Firstly, the strongly nonuniform interface trap profile after degradation could severely reduce the channel carrier mobility. Secondly, negative charges in acceptor-type Dir, generated at the drain side of the channel, can reduce the number of channel carriers. Which of these mechanisms is dominant is a point of disagreement in the literature 131, 141, [6], and it is worthwhile to give a critical evaluation of the different arguments.

The presence of acceptor-type interface traps is mainly concluded from the fact that a certain amount of negative charge at the drain is needed in order to explain the resistance increase after stress. The presence of negative charge is only derived indirectly from the consideration that the channel current after stress has decreased, or that the substrate current after stress has increased [6]. The negative charge after stress has however never been directly evidenced. In contrast, in this work, charge pumping is used as an additional evaluation technique, which yields a direct measurement of the interface characteristics. As already mentioned in Section IV-A, although a small amount of negative charge in the proximity of the drain cannot be ruled out completely, under no circum- stances the presence of a significant amount of negative charge could be evidenced from the CP measurements.

The increase of channel resistance, however, can also be explained by a local mobility degradation [4]. Again, no direct proof for this mechanism could be given until now. The conclusion that mobility degradation could be at the origin of the channel resistance increase after stress was drawn in [4], based on the absence of any indication of negative charge from the charge-pumping results. It was even concluded there that positive charge or donor- type interface traps could be generated. The arguments against mobility degradation are twofold [6]: firstly, by using MINIMOS and introducing a model for mobility

a degradation, the observed shifts in channel currents could not be explained, unless unphysically large scattering due to the surface charges was introduced; secondly, simulation of the behavior of the substrate current after stress, which shows a gate-voltage-dependent increase in normal operation, requires a gate-voltage-dependent negative charge, which can be provided by acceptor-type interface traps.

However, this is not the only possible explanation for the behavior of the substrate current. Since mobility deg-

radation causes a local resistance increase, it also causes a local increase of the lateral electric field, leading to a higher substrate current. At low gate voltages, however, the current does not flow at the interface in the vicinity of the drain, but deeper into the substrate. Therefore, for these conditions the interface traps are not able to influence the currents by a change in mobility. The mobility degradation thus becomes only effective at higher gate voltages, when the channel current flows closer to the interface. So, again a gate-voltage-dependent influence on the substrate current is expected, which could explain the observed experimental characteristics. In order to further clarify this problem, we measured the substrate current before and after degradation. It was already mentioned in the previous section that, for the region of maximum degradation ( Vg = V d / 2 ) , where only interface traps are generated, the multiplication factor does not change sig- nificantly during stress. In Fig. 7, the substrate currents, measured in normal operation at different drain voltages after stresses at Vg = 3.5 V and v d = 8.5 V during 6000 s are plotted as a function of the gate voltage. It is important to notice that, for the case of [6, Fig 41, the substrate current is only measured for V, = 5 V, and plotted on a logarithmic scale. In Fig. 7 of the present study, Zsub is plotted for different drain voltages on a linear scale. Although our measurement yields the same result as in [6] at v d = 5 V on a logarithmic scale, it becomes clear from this figure that, for higher V,, the substrate current after stress. The multiplication factor shows the same qualita- gate voltages than the respective substrate currents before stress. The multiplication fator shows the same qualitative behavior. This behavior could be explained, e.g., by donor-type interface traps, which are positively charged at low gate voltages and therefore lead to a decrease of the lateral electric field and consequently of the substrate current. At higher gate voltages, however, the current flows at the interface. The donor-type interface traps become neutral, while the mobility degradation now directly influences the current characteristics, leading to an increase of the substrate current for higher gate voltages.

Of course, the above explanation is not proof for the discussed model of donor-type interface traps and mobility degradation. It just indicates again that characteristics such as those of [6, Fig. 41 and Fig. 7 should be interpreted with care, since different models can explain their behavior. Since we did not dispose of a MINIMOS sim- ulator that can account for spatially nonuniform distributions of interface traps, we were not able to check the above mentioned model. In any case, also simulation results should be treated with care, since they are only as good as the models that are used. To our knowledge, no verified model for the influence of strongly nonuniform interface trap distributions on the local carrier mobility was achieved until now. Simply extrapolating the results of uniform distributions may give qualitative results, but may certainly not be used as an unambiguous and quan- titative proof.

In conclusion, one has to acknowledge that the question

HEREMANS el al. : CONSISTENT MODEL FOR HOT-CARRIER DEGRADATION

Forward mode evaluation 720 1

0 2 4 6 8

vs Ivl Fig. 7. Substrate current in normal mode measured at different drain volt-

ages before (-) and after (---) a hot-carrier stress at Vd = 8.0 V, Vg = 3.5 V during 6000 s on an n-MOS with Leff = 2.4 pm, W = 25 pm, io, = 28 nm.

of whether mobility degradation or acceptor-type interface traps are responsible for the observed increase of the channel resistance cannot be solved at this moment. One only can state the following: 1) several models (acceptor- type interface traps or donor-type interface traps + mobility degradation) can qualitatively explain the observed current characteristics; 2) large amounts of negative charges, which could be expected for the case of acceptor- type interface traps, were never observed from charge- pumping results until now; 3) mobility degradation models able to treat strongly nonuniform interface trap distributions are required.

F. Degradation Mechanism in n-Channel Devices: Conclusions

As the conclusion of this section, the degradation characteristics for n-channel devices can be summarized as follows:

1) For very low gate voltages ( V, = V,), hot-hole injection occurs and results in hole trapping as being the major effect on A V,. A lot of interface traps are also generated under this condition, but their influence is masked by channel shortening due to the trapped holes.

2) For intermediate gate voltages ( V, = V d / 2 ) , the hole trapping gradually disappears and A V, becomes positive, due to the effect of the interface traps. The hot-hole- induced generation of interface traps, typical for the region V, = VI, is gradually taken over by a much less efficient hot-electron-induced generation. Further proof of this will be given in Section VI-A. The peak of this generation is located in the gate voltage region where both hot-electron injection and hot-hole injection occur. It is always shifted toward more negative gate voltages than that of the threshold voltage shifts since the latter are caused by the combined effect of hole trapping and interface trap generation.

3) For higher gate voltages ( V, 5: V d ) , the degradation is most probably caused by electron trapping at the drain, although some interface traps are still generated and are also influencing the current characteristics.

2201

V. DEGRADATION OF CHANNEL TRANSISTORS

The behavior of the substrate and gate currents of p- channel transistors is reasonably well understood. For equal substrate current levels, p-channel devices require substantially higher drain voltages than n-channel transistors because holes are much cooler than electrons in the same electric field. On the other hand, the p-MOS electron gate current in the low gate bias region is orders of magnitude larger than the n-MOS hole gate current because the oxide barrier for electron injection into the oxide is much smaller than the one for hole injection. In analogy to the n-channel case, one would also expect a hole injection peak for higher gate voltages ( Vg = Vd). However, since the energy of the holes in this region is not high enough for injection, no hole injection peak could ever be detected in p-channel devices until now.

A. Charge-Pumping Measurement Results

In Fig. 8, AZcp characteristics are shown for a p-channel transistor before and after a hot-carrier stress for different stressing regions. The drain voltage for each case was - 10 V. The injection time was 1000 s. From this figure, three main conclusions can be drawn:

1) As for the case of n-channel transistors, interface traps are generated for each condition. The highest number of interface traps is created in the region of maximum gate current ( V, C V d / 2 ) , which for this case is also the region of maximum substrate current. It was also verified by disconnecting the drain that the interface traps are generated at the drain side of the channel.

2 ) In addition to the interface.trap generation, a large net negative charge is present, which is observed in the shift of the CP transition edge toward positive base level voltages. This is explained by strong electron trapping at the drain side of the channel, similar to the hole trapping for n-channel transistors. It is also clear that the shift of the transition edge of the AZcp curve is mainly caused by negative trapped charge, and not only by the fact that the interface traps are generated very close to the drain, since the AIcp curves reach a net saturation level for base level voltages higher than V, (cf. the characteristics of a channel hot-hole-stressed n-MOS transistors). The presence of negative charge is also evidenced from the negative values of AZcp at Vba,, = -6.5 V and the humps at vba,, = -0.5 V. However, a charge-compensating experiment, which was possible in the case of n-channel transistors, could not be carried out in this case because no holes can be locally injected near the drain of a p-MOS transistor.

3) For the condition V, > V d / 2 no negative charge is observed. Furthermore, a rather small amount of interface traps is generated.

B. Experimental Degradation Characteristics

. In this paragraph, the results of the previous paragraph are compared with the degradation behavior of the current

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 35. NO. 12. DECEMBER 1988 2202

a h ,o Q.

8

6

4 7 E

2 s P

0

-2 .‘8 ’ - ‘ 6 . - ‘ 4 . -‘2 . 0 ’ i2 Base level [VI

Fig. 8. Increase of the Izp signals ( A I , represented by the solid lines) as compared to the I , , curve at a virgin device (dashed line) for different channel hot-carrier stress conditions. The stresses are done at V, = - 10 V for 1000 s on p-MOS transistors ( L e f f = 2.4 pm, W = 200 p m , r,,, = 28 nm).

I I C 2 1.0 d

p” 0.0

s -1.0 2“

2 0.5 0 )

’D

4 -0.5

0 2 4 6 8 1 0 1 2

-vs [VI Fig. 9. Behavior of A Vt /A V<.-%, A V,/AV,,,, and A I ~ p / A I c , ~ m ~ x as a

function of the gate bias applied during stress. The transistors and stress conditions are the same as for Fig. 8. The maximum degradation values are: A V?,,,, = 5.8 m V , A V,,,, = 1 . 1 V , Al,,,,/l,,,,,,, = 56 percent.

characteristics. In Fig. 9, the maximum of the CP current ( A Icp ), which is a measure for the interface trap generation, and the shift of the CP transition edge ( A V,), which is a measure for the electron trapping, are plotted as a function of the gate voltage during stress, together with the shift of the threshold voltage ( A V , ) . The curves are normalized to their maxima, indicated in the figure caption. It must be noticed that, in order to use the same conventions as for n-channel transistors, a positive A V, and a positive A Vcp are plotted on the negative side of the degradation axis on Fig. 9 because they correspond to an increase of I I d I . An increase of Icp on the other hand is plotted on the positive side of this axis because it causes a decrease of I I d I. From this figure, three conclusions can be made:

1) For the region of low and intermediate gate voltages, where large electron injection occurs, the shift of the threshold voltage is positive (i.e., a negative shift of the absolute value of VI). This shift correlates to the shift of the CP transition edge, but is opposite to the shift to the CP current. The degradation is therefore explained by the large amount of electron trapping, which causes a channel shortening, similar to the hole trapping in the n- channel case for very small gate voltages ( V, 5: V,).

2 ) Also, ADjf is maximum in the low Vg region. The

influence of these traps on the ZhVg curve can be twofold. Firstly, the mere presence of the traps can reduce the mobility of the channel carriers, resulting in a decrease of I I d I . Secondly, donor-type interface traps filled with holes (i.e., only those located above the Fermi level) will reduce I I d \, while acceptor-type traps filled with electrons (Le., only those located below the Fermi level) will increase it. Since the interface traps are created in the region of the channel that has a lowered V,, their influence on the channel current is masked, similar to the case in the very low V, stress region in n-channel transistors. Since electrons only need 3.2 eV to be injected into the gate oxide while holes need about 4.5 eV, the electron gate current of p-channel transistors is much larger than the hole gate current in n-channel transistors, and the range of the gate voltage for which trapping of carriers in the gate oxide masks the influence of the created interface traps is also broader in p-channel transistors than in n-channel transistors. If the trapped electrons could be compensated, e.g., by photo detrapping or by hole injection, the influence of the interface traps would become visible on A 1 V, I. In analogy to the n-MOS case, one can predict that A I V, I would then reverse sign in Fig. 9. This becomes clear from the behavior of A 1 V, I at larger 1 V, I , where no electron trapping occurs (see below).

3) For the region of high gate voltages, A I V, I is positive. This is again in agreement with the CP results, since for this condition there is no longer any electron trapping ( A V,, 5: 0 V ), and consequently the (small) amount of interface traps plays an increasingly important role. This role could consist of a degradation of the mobility of the free channel carriers. Another possibility is that the interface traps are donor-like, i.e., positively charged during the threshold voltage measurement, thus increasing the channel resistance by a reduction of the amount of free carriers. Note that these possibilities are compatible with the model using donor-type interface trap generation and mobility degradation, offered in Section IV-E explain the behavior of the substrate current after stress in n-MOS transistors. If, however, the interface traps are considered to be of acceptor-type, the decrease of I Id1 at high I V, I in Fig. 9 has to be explained either by supposing that the traps degrade the channel carrier mobility, or that hole injection occurs for this condition. However, hole injection at V, = Vd in p-channel transistors has never been confirmed experimentally. Nevertheless, one can state that the condition V, = V d is the least degrading of all possible conditions (for n-channel as well as for p-channel).

C. Additional Experimental Evidence for the Degradation Model

The stress time dependence of the multiplication factor, the threshold voltage, and the CP current were monitored to obtain confirmation of the model presented above. The results of these experiments are shown on Figs. 10 and 11. They confirm the conclusions of the previous paragraph.

1) For the stresses around the maximum degradation

2203 HEREMANS et ai.: CONSISTENT MODEL FOR HOT-CARRIER DEGRADATION

1.1 q 1 0 V g = - l V

vg=-3v 0 Vg=-SV

0.9 3

0 . 3 ' " " " ' I " ' 0 200 400 600 800 1000

Time [s] Fig. IO. I,,,/Id, normalized to the initial value, during stress at Vd = - 10

V and three values of V,, for p-channel transistors. Leff = 2.4 pm, W = 25 pm, to, = 21 nm.

loo0 I

70 10 100 1000 10000

Time Is] Fig. 11. V, shifts and increase of I, as a function of stress time for p-

channel transistors. Stress parameters: Vd = -9 V , v, = -2.5 V. Le,, = 2.4 pm, fox = 28 nm. W = 7500 prn for AIcp and W = 25 pm for A V,.

conditions (all curves on Fig. lo), the multiplication factor strongly decreases. This corresponds to an increase of 1 Vg 1 and consequently a net negative trapped charge, in agreement with our previous conclusions. It is the dual case of the curve for Vg = 0 .8 V on Fig. 5. As shown on Fig. 11, for this case the threshold voltage increases with time with a slope of only about 0.2, and a saturation effect is observed for longer times. The CP current, however, increases with a slope of about 0.5, as shown also in Fig. 11. This confirms our conclusions that the increase of the Di, is not responsible for the threshold voltage shifts in this regime. As already mentioned in Section IV, a slope of 0.2 and the saturation effect are typical for the trapping mechanism, while a slope of 0.5 is typical for Di, generation.

2) The behavior of M , A V,, and A IC,, in the region of high Vg (e.g., Vg = - 10 V) is not easy to determine: the changes are too small to allow reliable recording. One can, however, predict that the multiplication factor M will slowly increase with stress time. Indeed, if any hole trapping occurs at all, this will increase the lateral electric field in the channel and therefore increase M. If on the other hand no hole trapping occurs, only the influence of generated interface traps will be noticed. These will also increase the multiplication factor, either by mobility degradation, or by positive charges in donor-type interface traps, in analogy with the case of n-channel degradation.

D. Degradation Mechanism in p-Channel Devices: Conclusions

In summary, two modes of degradation can be observed in p-channel transistors.

1) For very low and intermediate gate voltages ( VR = V, and Vg = Vd/2), electron trapping is the dominant degradation mechanism. Interface traps are also generated, but their influence remains masked by the channel shortening, caused by the trapped electrons.

2) For high gate voltages ( Vg = V, ) , the positive A I V, I is most likely due to the generated interface traps.

One can question why such a large amount of electron trapping is observed from CP measurements in p-channel transistors for Vg = V d / 2 , while no electron trapping could be evidenced in n-channel transistors after stresses in the region Vg > Vd, even though the electron gate current of the latter stress can be made to exceed the electron gate current in the former case. Although this question is difficult to answer, it is suggested that this difference is due to the completely different field distributions that exist in both cases. Indeed, in n-channel transistors the drain voltage is positive, and the injected electrons are directed toward the drain region. Therefore, they are probably trapped mainly above the drain, where they cannot be detected by charge pumping, and hardly influence the channel current. For p-channel transistors however, the drain voltage is negative, and the electrons are injected away from the drain. Therefore, they are trapped further away from the drain, above the channel, where they can easily be detected by charge pumping, and fully influence the channel current characteristics. It was found from experiments on split-gate transistors that a large amount of electron trapping can be evidenced in n-channel transistors after hot-carrier degradation as well. In this experiment, the transfer gate near the drain is biased to a high positive voltage (extending the drain into the channel), while the other gate is biased for providing hot-electron injection conditions ( Vg = V d ) . It was found by charge pumping on both gates separately that trapped electrons are only present underneath the transfer gate.

VI. ACCELERATED LIFETIME EXPERIMENTS (ALE)

In order to predict the lifetime of MOS transistors under the influence of hot-carrier degradation and to intercompare the hot-carrier sensitivity of different MOS technologies, the linear relationship between log ( Zsub/Zd) and log (7 Isub) for n-channel and p-channel transistors, respectively, is commonly used [2], [29]-[34]. In these experiments, the lifetime T is related to an arbitrarily chosen shift of a parameter (e.g., V, [2] or g, [29] ) that is believed to be a good monitor for the real damage caused by the hot-carrier injection. It is obvious that this ALE procedure becomes questionable or invalid if this chosen parameter no longer embodies the real damage unambiguously, or if the stress conditions vary during the stress time. In this section, it will be shown that, for the case of n-channel transistors, the use of the threshold volt-

I d ) or log ( T

2204

: 0 Vg=lVVd=7.5V . A Vg=ZVVd=7.5V

age shift, as a monitor for the damage, can lead to severe experimental complications for stressing at low gate voltages. Also, for the case of p-channel transistors, the conventional procedure cannot be applied as such due to the influence of the trapped charge on Isub and Z,.

A. n-Channel Transistors The accelerated lifetime procedure, proposed by Hu et

al. [2], is based on the fact that all hot-canier phenomena follow the same Z, * exp ( - / q X E, ) relationship. Based on this, the expression for the device lifetime 7 can be obtained, using the measured substrate and drain currents

7 . I d / w = c * [ I ~ u b / l d ] - ~ (4) where C is a constant, W is the channel width, and rn = +,,/+,, with the critical energy a channel electron must have in order to create an interface trap and +i is the impact ionization energy.

It is important to notice that, according to this model, T is the stress time necessary to generate a certain amount of interface traps. When carrying out the ALE-procedure of 121, it is implicitly assumed that AV, (or Ag,) is a good monitor for this interface trap generation. Defining the device lifetime at A V, = 10 mV, 7 can be plotted according to (4). This is shown on Fig. 12, where the curves for transistors from different technologies are compared with data from the literature [ 11. The slope rn of the curves is about 2.7. Assuming +i = 1.3 eV, this leads to +lf = 3.5 eV. This value was interpreted [2] as being the sum of the energy needed for electron injection into the oxide (i.e., 3.2 eV), and the energy required to create an interface trap by breaking a Si-H bond (i.e., 0.3 eV). However, the described ALE method can give rise to experimental problems when the transistor is operating at conditions of low gate voltage ( V, < Vd/2). As shown in Section IV, the threshold voltage shifts under these conditions are very small and become even negative. Moreover, the slope of the log ( A V, ) versus the log-of- time curve is only 0.2. A distinct relationship between 7 - Id and Isub/Id can no longer be found, and consequently lifetime predictions based on Vi measurements become unreliable.

In order to extend Hu's model to all gate voltages, AIcp is plotted as a function of stress time on a double log scale, in the same way as is done for A VI in the conventional procedure. This is done on Fig. 13(a) for a stress at V, = 7.5 V and at different gate voltages. The slope n of the curves is found to be 0.55, almost independent of the used stress condition. On Fig. 13(b) the slopes of both A VI and AIcp are plotted as a function of the applied gate voltage. The slope of the threshold voltage is plotted positive for increasing threshold voltage and negative for decreasing threshold voltage. In the region of maximum Isub, where the influence of generated Dit on the V, shift is dominant, the slopes of A VI and AI,, are identical and equal to 0.55. This value seems to be typical for the creation of interface traps, as already suggested in Section IV-D. However, for stresses at low gate voltages, the slope of the (negative)

IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 35. NO. 12. DECEMBER 1988

loo 7

Supplier B 4 Supplier C - - - Literature \

.01 .01 .1 1

lsub /Id Fig. 12. Intercomparison of hot-carrier sensitivity of different technolo-

gies for n-channel transistors using constant voltage stress experiments, based on A V, shifts ( T: A V, = 10 mV). W = 25 pm.

X VgdV Vd=7.5V t VgSV Vdz7.5V

NMOS lO0*2um

10 100 1000

Time [SI (a)

0.8 I I

Fig. 13. (a) "1, as a function of stress time for different stress conditions. W = 100 pm, Le, = 2.4 pm, to, = 28 nm. (b) Slope of the time-dependence of A V, and of AIcp for stresses at Vd = 7.5 V, as a function of the gate voltage applied during stress. W = 100 pm, Leff = 2.4 pm, tOx = 28 nm.

V, shift drops to a value of about 0.3 due to the influence of hole trapping on the V, shift. Also at high gate voltages, the slope of the V, shift drops to a value of about 0.2. Based on Fig. 13(a), a new lifetime can be defined as the stress time necessary to obtain an arbitrarily chosen A IC,, which was taken as 1 pA/pm channel width measured at a frequency of 100 kHz in our experiments [9]. Using this concept, again a marked relationship between 7 - Id and I , , , / / , according to (4), can be found. The result of this new procedure, based on CP measurements, is shown in Fig. 14 for two different suppliers. The new lifetime curves can be divided into two linear parts with different slopes. A slope rn, of about 2.5 is observed for the I s u b / I d

HEREMANS e, al.: CONSISTENT MODEL FOR HOT-CARRIER DEGRADATION

10000 1

1000

100

10

. I 9 LI

9. . . .... J .001 .Of . I 1

/sub / I d Fig. 14. Intercomparison of hot-camer sensitivity of different technolo-

gies for n-channel transistors, using constant voltage stress experiments, based on AI , , shifts (7: AI., = 1 .O pA per pm channel width atf = 100 kHz, AVA = 5 V , and V, = 0.1 V ) . W = 100 pm.

region where the influence of the interface traps on V, is dominant. This is in agreement with the value, obtained from the conventional procedure. It indicates that, in the low I sub / ld region, the interface traps are mainly caused by the hot-electron injection. At high Isub/Id values, where hole injection and trapping occur, a much larger slope m2 of about 5.5 is observed. From Section IV, it is known that for these conditions a lot of interface traps are created, but that they can not be extracted from the V, measurement due to the masking effect by the trapped holes. The slope of 5.5 is a strong indication that the holes are responsible for the interface trap generation in this region. The slope m2 can be written as

m2 = 1 + [ ( 4 h t * h ) / ( d ) i * ( 5 ) where &, is the energy necessary to create an interface trap and h h and A, are the mean free paths for holes and electrons, respectively. Assuming 4l = 1.3 eV and x h / x ,

= 0.724 [29], the critical hole energy for the creation of interface traps is found to be 4.2 eV. This suggests that the interface traps are created by holes that are first generated by impact ionization and subsequently injected into the oxide. It was suggested in Section IV-C that holes are about three to four orders of magnitude more effective than electrons in creating interface traps. The analysis performed in the present section gives a second and independent argument for the importance of hole injection in the interface trap generation mechanism. The existence of more than one slope for lifetime curves was also reported in [31]. A different explanation was given for this fact, but it should be noted that the experimental conditions used in [31] were quite different from those in this study.

B. p-Channel Transistors As mentioned iQ Section IV, in p-channel transistors,

the Vt shift during worst case degradation (i.e., Vg = V d / 2 ) proceeds as a power 0.2 of time, and it clearly tends to saturate. As a result of this saturation, linear ex- trapolation of the curves and extraction of the lifetime is hazardous and unreliable. A meaningful T - Isub versus Zsub/Zd relationship can no longer be obtained and an intercomparison of the hot-carrier sensitivity of different

Id = 747pA /sub = 17pA

___

2205

vg = -4.5v Vd = -12.W

1 ' . ' . ' " " . ' .....'I . . . . ' . 10 100 1000 10000

Time [s] Fig. 15. Comparison between constant current stress (curve A ) , constant

voltage stress (curve B ) and gradually adjusted voltage stress (curve C ) on pchannel transistors. W = 100 pm, Le, = 2.4 pm, to, = 28 nrn.

technologies becomes impossible. It is furthermore obvious that the saturation of A 1 V, 1 is caused by electron trapping during a constant voltage stress. Indeed, trapped electrons reduce the lateral electric field in the channel and induce a transversal electric field in the oxide that repels further injection. It therefore is proposed to stress p-channel transistors by imposing constant drain and substrate currents, while keeping the source and gate voltages constant. The drain and substrate voltages thus vary con- tinuously during the stress period. This ensures a constant electric field near the drain, which should guarantee a constant electron injection current, greatly eliminating the saturation effect. This procedure is similar to the one suggested in [31] for n-channel transistors.

Comparing the results of constant current (Fig. 15, curve A ) and constant voltage stress (Fig. 15, curve B ) , one can observe two main features. First, the slope of A V, versus time is about 0.2 in both cases; second, the saturation effect observed for curve B has disappeared, as expected, for the case of constant current stress. Notice that curve B lies below curve A . This is due to the larger electron trapping during the constant current stress, as the result of the continuous increase of the applied voltage ( V d and v S u b ) . In order to check the validity of this conclusion, a third experiment was performed. Constant voltage stresses were applied but the stress voltages ( V d and VsUb) were adjusted at each measurement time to the values measured during the constant current stress at the corresponding time. The results of this experiment are represented by curve C on Fig. 15. As can be seen, A V, is at first identical to the value of the constant voltage case, while the curve gradually approaches the one for constant current stress.

p-channel transistors from different technologies were evaluated using this new stressing procedure. The results are shown in Fig. 16 for different suppliers. Now, the threshold voltage shifts result in the expected T Isub versus I,,b/Id relationship with a slope of about 2.3. In this way, it becomes possible to reliably intercompare the hot- carrier sensitivity of p-channel devices from different technologies. But, of course, the procedure does not yield a useful lifetime prediction for constant voltage conditions.

2206 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 35, NO. 12. DECEMBER 1988

.ooo 1 .001 .01 .1 lsub / Id

Fig. 16. Intercomparison of hot-carrier sensitivity of different technologies for p-channel transistors using constant current stress experiments, basedonAV,shi f ts (~: ( A V , ( = 10rnV) . W = 2 5 p m .

VII. ALTERNATING INJECTION CONDITIONS The degradation mechanisms for n-channel and p-chan-

ne1 devices were discussed for different dc stress conditions. The degradation, however, shows a peculiar behavior when alternating stressing conditions are applied. In this section, it is demonstrated that this behavior can be explained by the presented model and that it provides additional evidence for the validity of the model.

A first experiment on an n-channel transistor is shown on Fig. 17(a) and (b). First, a degradation at conditions of maximal (i.e., at V, = 3.5 V, V, = 8 V, period 1 ) was performed during 1000 s . This was followed by a 1000-s stress at low gate voltage ( Vg = 0.8 V, V, = 8 V, period 2 ) during which holes were injected. Next, a 500-s stress at high gate voltage was applied ( Vg = 8 V, V, = 8 V, period 3) , during which electrons were injected. Finally, a second 500-s stress at low gate voltage ( V , = 0.8 V, V, = 8 V, period 4 ) was done. In Fig. 17(a) A V, and AZ(,, are plotted as a function of the total stress time. On Fig. 17(b), the CP characteristics are plotted at the end of the different stressing conditions, together with the characteristics of the virgin device.

During the first period, the normal threshold voltage increase is obtained. It results from the local increase of interface traps near the drain. The increase of Di, is indicated by the increase of the CP current on Fig. 17(a) and (b), while its location very near the drain is shown by the CP tail at low base level voltages on Fig. 17(b). During the second period (hole injection), A V, abruptly drops and even becomes negative. Yet, in Fig. 17(b), it is shown that the CP current has further increased. However, this increase is accompanied by the buildup of positive trapped charge, illustrated by the large shift of the CP transition edges toward more negative base level voltages. The behavior of A V, is therefore readily explained by the fact that the interface traps that are created during the first and the second period, are completely masked by the holes trapped in period 2.

Fig. 17(b) shows that, after the third period (electron injection), the edges of the CP curve shift back to their position after period 1. As already mentioned in Section IV, this can only be due to trapping of injected electrons

2n Alcp*2 [nA]

period 1 Period 2 Period 3 Period 4

0 1000 2000 3000 -1

? E Q ,o

Fig. 17. (a) A

0.8

0.6

0.4

0.2

0.0

Time [s] (a)

.9 -7 -5 -3 - 1 Base Level [VI

(b)

I

; and AIcp as a function of stress time for n-channc transistor W = 100 pm, Le, = 2.4 pm, r,, = 28 nm, Vd = 8.0 V; period 1: V, = 3.5 V, 1000 s; period 2: V, = 0.8 V, 1000 s; period 3: V, = 8.0 V, 500 s; period 4: VR = 0.8 V, 500 s. (b) Charge-pumping characteristics before stress and at the end of each of the stress periods of (a).

on the previously trapped holes. In Fig. 17(a), the threshold voltage almost immediately shifts back to a positive value that is larger than the one obtained after period 1. Indeed, the interface traps that now influence AV, are those generated during both periods 1 and 2. As clearly shown on Fig. 17(a) and (b), there is only a modest increase in the number of interface traps after the trapping of electrons on previously trapped holes, in agreement with the results presented in Section IV-A.

The experiment can be continued. Each time holes are injected, the interface traps are masked by trapped holes, and A V, becomes negative (as during period 4). Electron injection again neutralizes the trapped holes, and A V, becomes positive again.

In a second but similar experiment, illustrated on Fig. 18(a) and (b), holes were injected during the first period (Vd = 8 V, V, = 0.8 V) for 1000 s . This was followed by an electron injection ( Vd = 8 V, V, = 8 V, period 2 ) for 1000 s and another hole injection (period 3) for 1000 S .

After the first period, Fig. 18(b) shows that positive charge is trapped at the drain, and is accompanied by an increase of Dit. A V, is negative, due to the dominant influence of the channel shortening.

During the second period, a strong increase in the threshold voltage is observed, which is not found if the electron injection was performed without a previous hole

HEREMANS et al.: CONSISTENT MODEL FOR HOT-CARRIER DEGRADATION

3 -

2 -

s 1 - E . 5 0 .

-1

-2'

2207

0 before slnjectlon

A alter e-Injection

- . ' ' ' * ' . ' . ' . ' .

2.0

1.5

1.0

0.5

0.0

-0.5

-1.0

-1.5' ' ' ' ' ' ' ' ' 0 1000 2000 3000 4000

0.6

3 0.4

3 0.2

E

0.0 -8 - 6 -4 -2 0

Base level [v] (b)

Fig. 18. (a) A VI and AIcp as a function of stress time for n-channel transistor W = 1 0 0 pm, Leff = 2.4 pm, zo, = 28 nm, Vd = 8.0 V; period 1: V, = 0 .8 V, 1000 s; period 2: V, = 8.0 V, 1000 s ; period 3: V, = 0.8 V, 1000 s. (b) Charge-pumping characteristics before stress and at the end of each of the stress periods of (a).

injection. This experiment is often incorrectly interpreted as evidence for the model of Lai [23], concerning the generation of interface traps by trapping of electrons on previously trapped holes [3], or as evidence for electron trapping during period 2 on neutral electron traps, created by hot holes during period 1 [ 5 ] . In Fig. 18(a) as well as Fig. 18(b), it is unambiguously demonstrated that the trapping of electrons on the trapped holes only leads to a small increase in interface traps. Also, no significant electron trapping could be observed during our experiments, which should be visible on the CP characteristics. The strong increase of the threshold voltage during period 2 is simply explained by the compensation of the positive trapped charge during electron injection. By this compensation, the interface traps generated during the hole injection, which were masked by the channel shortening, now fully influence the threshold voltage. This is confirmed by the fact that the threshold voltage shift after this electron injection corresponds to the one that is observed during the first period of the first experiment (Fig. 17(a)) at an identical Icp shift, as is indicated by the arrows in Figs. 17(a) and 18(a).

The hole injection during the third period again masks the interface traps, leading to a quick turn-around of the threshold voltage shift.

In another type of experiment, different devices were stressed during 1000 s at a fixed drain voltage V, = 8 V

0.6

0.5

3 0.4 E Q 0.3 P

0.2

0.1

0.0

A after e-Injection

d

0 1 2 3 4 5 6 7

V g M (a)

and at gate voltages ranging from 0.8 to 6 V. These stresses were all followed by one additional electron injection performed at V, = V, = 8 V during 100 s. The results of these degradations are summarized on Fig. 19(a) and (b). The squares represent AIcp (Fig. 19(a)) and A Vl (Fig. 19(b)) after 1OOO-s stress as a function of the gate voltage applied during this stress. The triangles show both parameters measured after the additional 100-s electron injection. It becomes clear from Fig. 19(a) that during the additional stress at V, = V, only a small increase of Dit is obtained, while the V, behavior as a function of the applied gate voltage changes strongly as shown on Fig. 19(b). This again confirms the model of masking of the interface traps in the low V, region after the first 1000-s stress. There obviously is no correlation between the created interface traps, and the threshold voltage shifts after this first stress. This correlation does exist after the additional 100-s electron injection because the masking effect is removed by neutralization of the positive charge. It is again important to notice that the A V, shift after the additional 100-s electron injection is mainly caused by interface traps that were generated during the first stress of 1000 s, and not during the electron injection itself.

VIII. CONCLUSIONS Using changes in Id- V, characteristics, charge-pump-

ing characteristics, and substrate current curves, a con-

2208 IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 35. NO. 12. DECEMBER 1988

sistent model is derived that explains all channel hot-carrier degradation phenomena in both n-channel and p- channel transistors under static stress. It is shown that hot- carrier injection always results in the generation of interface traps. These traps are the main cause for the degradation of n-channel transistors, except for the region of the hole injection in which their influence is masked by the trapped holes. In p-channel transistors their effect is masked by trapped electrons.

Gated diode experiments are used to compare the effi- ciencies for interface trap generation by hot-hole injection and hot-electron injection. Holes are shown to be by far (three or four orders of magnitude) more efficient in this generation process. The influence of hot holes in the degradation of n-channel transistors was further demonstrated by studying the critical energies necessary for interface trap generation.

The slope of 0.2 for the V, shift as a function of time is experimentally shown to correspond to a carrier trapping mechanism. A slope of 0.5 to 0.7, on the other hand, is typical for interface trap generation. When carrier trapping is dominant, it is responsible for a saturation of device degradation during constant voltage stresses, which greatly complicates accelerated lifetime experiments. In these cases constant current stresses are proposed in order to be able to intercompare the hot-carrier resistance of different technologies. This technique is successfully applied to p-channel transistors. For n-channel transistors, an alternative lifetime prediction procedure is proposed, that is applicable over a wider range of stress conditions, and which uses charge-pumping current as the degradation monitor.

The model of interface trap generation and hole trapping is shown to completely explain the behavior of n- channel transistors during alternating injections. No en- hanced generation of interface traps is observed during this type of degradations.

ACKNOWLEDGMENT

The authors wish to thank BTMC Alcatel for providing the devices.

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HEREMANS er a/.: CONSISTENT MODEL FOR HOT-CARRIER DEGRADATION 2209

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*

Paul Heremans was born in Leuven, Belgium, on October 29, 1961 Hc received the Ekctricdl and Mechanical Engineering degree in 1984 from the Katholieke Universiteit Leuven, Belgium He is currently working toward the Ph.D degree in the Analysis and Reliability Group of the Mdterial dnd Packaging Divi\ion at the Interuniversity Micro- Electronics Center (IMEC)

In 1984, he joined the ESAT Laboratory of the Katholieke Universiteit Leuven as a Research As- bi\tdnt of the Belgidn National Fund for Scientific

Rewarch In 1986. he pined lMEC His current interests are hot-carrier effect\ in MOSFET'\. device physics. and chardcteriZdtion techniques

*

Rudi Bellen5 was born in Herentals, Belgium. on April 24, 1963 He received the Electrical and Mechanical Engineering degree in 1986 trom the Kdtholieke Universiteit Leuven, Belgium He I\

currently working toward the Ph D degree in the Analysis and Reliability Group of the Material and Packdging Divi\ion of the Interuniversity Micro- Electronic\ Center (IMEC)

In 1986, he joined IMEC as a Research Assis- tant His current interests are hot-carrier-related problem< in MOS devices and device physics

Guido Groeseneken m a \ born in Tienen Bel glum. on March 27, 1958 He rccei\ed the Elec- tricdl and Mechdnlcdl Engineering degree in 1980 dnd the Ph D dcgree in 1986, both trom the k i t h olicke Univcrsiteit LeuLen. Belgium

In 1980. he pined the ESAT Labordtor) ol t h e Kntholieke UniLersiteit Leuben \\here he v.orhed a \ 'i Rc\e,irch A\\i\tant (1980-198-1) dnd Senioi Re\e.irch A\\istant (1985- 1987) ot the Hel:i,in National Fund tor Scientihc Re%nrch In 1087. he joined the RKrD Ldboratory ot the In-

teruniversity Micro-Electronic\ Center (IMEC). uhere he I\ working in the Analysis dnd Relldbilitj Group ol the Material and Packaging Division where he i s respon\ible for reliability re\earch HI\ current re\earch inter ests are nonvoldtile semiconductor memorlc,, reliability phy\ic\. hot-carrier effect\ i n MOSFET's, device phy\ic\. electrical chuacterizdtion tech nique\ tor semiconductors, and DLTS analysi\

*

Herman E. hlaes (S'73-M'80) was born in Leu- ven, Belgium. on August 15. 1947. He received the M.Sc. degree in electrical and mechanical cn- gineering in 1971 and the Ph.D. degree in applied sciences in 1974, both from the Katholieke Uni- versiteit Leuven (KIJL), Belgium.

From 1971 until 1974. he was a Research As- sistant (Fellow of the National Fund for Scientific Research of Belgium. NFWO) in the Laboratory for Physics and Electronics of the University of Leuven. In 1974, he was granted a CRB Fellow-

ship by the Belgian American Educational Foundation. From 1975 until 1985, he was with the ESAT Laboratory at the University of Leuven as a Senior Research Associate of the Belgian National Fund for Scientific Re- search and ab a Lecturer at the University. Since 1985. he has been a Pro- fessor at the University of Leuven. In 1985. he joined the newly established R&D Laboratory of the Interuniversity Micro-Electronics Center (IMEC) in Leuven, Belgium. as Head of Analysis and Reliability. His research interests and activities cover nonvolatile memory devices. physics of seini- conductor devices. reliability aspects of integrated circuits. silicon-on-in- sulator techniques and devices. and the use of physical and electrical characterization techniques in semiconductor-related problems.

consistent model for the hot-carrier degradation in n-channel and p-channel mosfets

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