INTERNATIONAL JOURNAL OF CIRCUlT THEORY AND APPLICATIONS, VOL. 23,269-283 (1995)

AN ANALOGUE MODULE GENERATOR FOR MIXED ANALOGUE/DIGITAL ASIC DESIGN

G. GIELEN,: G. DEBYSER, K. LAMPAERT, F. LEYN. K. SWINGS. G. VAN DER PLAS AND W. SANSEN

Katholieke Universiteit Leuven, Leuven, Belgium

AND

D. LEENAERTS. P. VESELlNOVlC AND W. VAN BOKHOVEN

Technical University Eindhoven, Eindhoven. Netherlands

SUMMARY

This paper discusses the realization of an analogue module generator that forms part of a mixed analogue/digital design environment. It is able to design analogue functional modules such as like amplifiers, filters, etc., either in an automatic or in an interactive session, starting from performance specifications over topology selection, parameter optimization and simulation/verification down to lay-out. The analogue module generator is integrated in a commercial EDA framework. Practical design results show the capabilities and efficiency of the system.

1. INTRODUCTION

There is a clear tendency in the electronics market and particularly for application-specific integrated circuits (ASICs) to integrate complete systems on a single chip or a multichip module. The motivations for this are cost reduction (fabrication, test), improved performance and reliability, less weight, volume and power consumption, fewer off-chip connections, etc. Although such integrated systems mainly consist of digital circuitry, analogue circuits are needed at the interface between the electronic system and the outer world. The signals in this world are analogue in nature and in applications such as space and telecommunications are often very weak (low signal, high noise contents, distortion), with demanding application constraints (high dynamic range, high transmission rates, etc.). This places very demanding requirements on these analogue interfaces.

The evolution to completely integrated systems and the inability to fully dispose of analogue circuitry explain the booming market share of mixed signal ASICs nowadays. Although the analogue circuits occupy only a small part of the area in these mixed signal ASICs, they require an inversely large part of the design time and cost and are often responsible for design errors and expensive design iterations. This is due to the knowledge-intensive nature and the larger number of degrees of freedom in analogue design compared with digital design. Therefore it is necessary to develop tools or an integrated environment for the automated or computer-assisted design of analogue and mixed signal integrated circuits.

The objectives of developing a CAD environment for the mixed signal ASIC design process are then

(i) to reduce the overall design time and cost and to improve the turnaround time of the ASIC (ii) to realize high-performance area/speed/power-optimized mixed signal applications

(iii) to guarantee the correctness of the design such that overall system goals can be met (iv) to capture, formalize and generalize existing mixed analogue/digital design knowledge such that it

can be applied automatically to a wide variety of designs

t Research associate of the Belgian National Fund of Scientific Research.

CCC 0098-98861951040269- 15 0 1995 by John Wiley & Sons, Ltd.

Received 20 September 1994 Revised I6 January 1995

G. GIELEN ET AL.

inexperienced designers to become familiar with the process of designing ASICs through an interaction with the system expert designers to concentrate on creative tasks while the routine tasks are taken over by the system.

An essential part of such a mixed signal design environment at the lowest levels in the hierarchy is an analogue module generator, which is the subject of this paper. In Section 2 the functionality of the realized analogue module generator will be discussed. The design flow will be described and the corresponding software architecture presented. The major software components of the analogue module generator will then be discussed in detail in Section 3. Their operation will be illustrated with practical design examples. An evaluation of practical experiences with the realized analogue module generator will be given in Section 4 and conclusions will be drawn in Section 5 .

2. THE ANALOGUE MODULE GENERATOR

2.1. Context within a mixed signal design environment

The complexity of the design of a mixed analogue/digital ASIC demands a hierarchical design strategy with several levels of design abstraction.' At the chip level a behavioural input description is used to compose an appropriate architecture, i.e. the system is divided into several modules or circuits needed to realize the specified behaviour (including the partitioning between analogue, digital and DSP circuitry). At the same time the ASIC specifications have to be translated into specifications for the individual modules in the selected architecture. These modules then have to be synthesized by the appropriate module generators according to the previously determined specifications. As the modules can be either analogue, digital or DSP, both analogue, digital and DSP generators are required in the mixed signal design environment. These tools then return the sized module lay-outs back to the chip level. The ASIC lay-out is then composed by assembling the module lay-outs and the design is verified by means of mixed-mode simulation.

For the DSP and digital circuitry, commercial DSP and logic synthesis tools can be used. The development of an analogue module generator, on the other hand, is the subject of this paper.

2.2. Functionality of the analogue module generator

An analogue module generator (AMG) has been developed that facilitates the automated or computer- assisted design of analogue integrated modules or circuits of the complexity level of amplifiers, comparators, filters, etc. As shown in Figure 1, the AMG has to translate module or circuit specifications including the selected technology process into mask lay-outs such that the resulting designs are guaranteed

Module Specifications Technology

Ccll&T&b~

Module Generator

Layout Sized netlist D m Shcct

Figure 1. Black box view of the analogue module generator

MIXED ANALOGUE/DIGITAL ASIC DESIGN 27 1

to function correctly from the first time. The AMG could be run automatically, but it will most often be used interactively by human designers who want to control and guide the overall design process. In order to carry out its task, the AMG needs two libraries: a cell library which contains all information about the different cells (standard, parametrized and custom) available in the system, and a technology library which contains all process-specific information about the different technology processes available in the system.

2.2.1. Input and output of the analogue module generator. The input for the AMG consists of a complete specification of the module or circuit to be designed, including:

(i) the type of module or circuit (ii) the preferred design style (standard cell, parametrized cell or custom design)

(iii) performance specifications for the module (iv) optimization targets for the module optimization (v) selection of the technology class (CMOS, bipolar or BiCMOS) and process

(vi) additional options that allow the user to control the operation of the AMG, such as (a) selection of the running mode (interactive or batch) (b) selection of the optimization algorithm (c) selection of the level of detail with which the trace of the design is displayed to the user.

The designer has to enter these specifications into a specification sheet at the start-up of the AMG. See Figure 2 for an example specification sheet for an analogue-to-digital converter. The AMG output will consist of the following data:

(i) schematic of the designed module (ii) net list of the designed module

(iii) data sheet (with an overview of the obtained performances as extracted from simulations) (iv) lay-out of the module (v) design history data (providing all kinds of information about the design session).

All this information is continuously updated and available for designer inspection in different data windows while running the AMG.

2.2.2. Main features of the analogue module generator. The most essential features of the developed analogue module generator are the following.

Availability of different design styles

The AMG offers three different design styles to the designer, all handled in the same way by the system: analogue standard cells, parametrized cells and full-custom design. The user can indicate which type of design style he or she wants. This allows the designer to optimally trade off design flexibility for design speed. The use of fully predefined standard cells has the advantage that the cells have a proven quality and that the design time is very short. Parametrized cells, which have a limited set of changeable parameters, have the additional advantage that the performances can still be tuned over some range, which gives a larger flexibility. Often, however, the required specifications are different from those of the library cells and optimal fully customized tuning of the circuit is needed. In addition, standard and parametrized cells are also dependent on the technology process, which further reduces their design flexibility. Therefore, for optimal performance and flexibility, full-custom design is necessary and is also offered in the AMG. The full-custom cells tool can also be used to automatically generate the standard cells in the library and thus to easily keep track of technology changes.

Hierarchical design methodology

The design process is organized hierarchically: a module (e.g. an analogue-todigital converter) is composed of different circuits (e.g. a comparator) which in turn consists of devices. The design at the different hierarchical levels all consists of the same steps (see Section 2.3). This allows for the largest

272

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Ierformnnce specifications resolution conversion time input m g e INL DNL offset error gain error input impedance output impedance

G. GIELEN ETAL.

W-ADC in-ADC, out-ADC

>= 8 bit <= 2P S

P 2 v <= 0.5 S B <= 0.5 S B <= 1 ISB C= 1 S B >= 50k R C= R

technology class technology process

test vectors/signals test coverage test SrnCtLlreS test nodes

test constraints

CMOS MIETEC-1.5pm

Figure 2. Example specification sheet filled out by the designer as input to the analogue module generator

degree of interactivity level of information stored optimization algorithm simulator layout format

design flexibility, since a small set of lower-level circuit topologies can be combined to result in a large variety of high-level module architectures that can cover a broad range of specification values. It is also possible to mix design styles at the different levels, e.g. to select a custom design style at the module level and a standard cell for the composing circuits.

automatic 2 simulated-annealing PLANET GDSII

Technology tolerance

The AMG covers the CMOS, BiCMOS and bipolar technology classes. The custom design tools are then independent of the actual process used within these classes. Indeed, all process-specific information is stored in the technology library files and the tools read in the actual values at run time after the designer has specified the desired process in the AMG input specification (see Figure 2).

Openness of the libraries

The AMG cell library is easily extendable with new topologies by the designers themselves. The effort required to include a new cell has been reduced to the strict minimum: drawing of the schematic (including

MIXED ANALOGUE/DIGITAL ASIC DESIGN 273

properties that guide the lay-out tool, e.g. matching and symmetry axes) and derivation of design equations (by means of the symbolic simulator) that are used for topology selection and sizing. The combination of symbolic analysis with the automatic computational path generation (see Section 3) simplifies the latter process and distinguishes this AMG from other analogue synthesis systems such as IDAC/PlanFrame,' OASYS' and MIDAS."

2.2.3. Graphical user interface. The designer operates the AMG through the graphical user interface. The main window in this user interface is shown in Figure 3. The top panel gives a graphical representation of the hierarchical structure of the module under design in terms of its subcells. This hierarchical view panel shows all subcells (and their subcells and so on) and indicates which (sub)cell is currently being designed by the AMG tools. Below the hierarchical view panel we find the data view panel which allows the designer to view all kinds of information (net list, schematic, data sheet, lay-out, design history) about the (sub)cell under design. Below we then find the design flow panel which shows the default design flow to be followed when designing a (sub)cell (see Section 2.3 for more details). It also indicates through colours the past steps that have successfully been completed and the present step that has to be or is being executed. Finally, at the bottom we find the message area where all kinds of messages about the tool

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i Hietanhlcal View Panel

Oesipn Flow Panel

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....... ".'.,

Figure 3. Main window of the analogue module generator's graphical user interface

274 G. GIELEN ET AL.

execution are displayed to the user. Possible error or warning messages are displayed in separate windows that pop up at run time.

2.3. Design flow in the analogue module generator

The design strategy implemented in the AMG is hierarchical and performance-driven. Since the performance specifications entered by the designer are the ultimate requirements which have to be satisfied by the synthesized module, these specifications are used to drive the different synthesis and lay-out tools. In this way the number of design iterations needed should be reduced or iterations should even be avoided.

The performance-driven design strategy is shown schematically in Figure 4 (see also the design flow panel in Figure 3). In between any two levels i and i + 1 in the design hierarchy the following steps are performed:

(i) top-down (a) topology selection (b) sizing and optimization (c) verification after sizing

(a) lay-out generation and extraction (b) verification after lay-out.

(ii) bottom-up

Conceptually these steps are the same at any level. The input to the top-down synthesis path comprises the specifications for the block under design at level i. Topology selection is then the selection of an appropriate topology (i.e. an interconnection of subblocks from the lower level i + 1) that can meet the specifications at the lowest implementation cost. Sizing is the mapping of the specifications for the block at level i into specifications for the subblocks at level i + 1 in the selected topology, so that the complete topology meets its specifications at level i. The latter is verified by means of (circuit-level or behavioural) simulation. If the verification fails, redesign has to be carried out and certain steps have to be redone. This

speclfications at level i layout at level i I 4 b I + I I c level i 3

t

- _ _ _ _ _ --- sizing &

optimization

I - _ _ _ _ _ I

sizing &

I c T

level i+ 1 1 I A t

I layout at level i+l t I

specificatiom at level i+l

Figure 4. The performance-driven analogue design stntegy

MIXED ANALOGUE/DIGITAL ASIC DESIGN 275

redesign has to be controlled by the designer. An automatic intelligent backtracking system has not yet been implemented, but at this moment backtracking hints are given to the user at any failure point to help him or her decide on the corrective action to be taken. If on the other hand the verification passes, the same steps have to be repeated for each of the subblocks at level i + 1 starting from the derived specifications. The performance specifications therefore drive the analogue synthesis.

This top-down synthesis process continues until a level is reached which allows a physical implementation. This is either the device level when selecting a custom design style or a higher level when using standard cells. The hierarchy is then traversed bottom-up, at each level generating the lay-out for the block at level i by assembling the already completed lay-outs of the subblocks from level i + 1. After extraction and detailed verification (by simulation) the lay-out is passed to the next level up. If the verification fails, redesign has to be carried out again under control of the designer. Note that also for the lay-out generation a performance-driven methodology is used in which the lay-out tools are driven in such a way that the block laid out meets its specifications by construction (if possible).

2.4. Software architecture of the analogue module generator

According to the above design strategy, the following tools had to be developed for the AMG: a topology selection tool, a sizing and optimization tool, a verification tool with links to one or more simulators and a lay-out generation tool. Existing commercial extraction and other back-end verification tools were used.

All this has resulted in the software architecture of the developed AMG shown in Figure 5 . The central part is the design controller which supervises the status of the design and controls the whole

t -iLrrA selection

sizing & € optimization

verification

analog layout generation

extraction I 4 DRCERC I

Figure 5. Software architecture of the analogue module generator

276 G. GIELEN ETAL..

execution of the AMG. The design controller interacts with the different tools on one hand and with the user through the graphical user interface on the other. This guarantees software modularity of the whole system. Any user actions in the user interface are passed to the design controller which takes the corresponding actions. It is therefore the design controller that calls the different tools and returns the result back to the designer when the tool is finished. The design controller also supervises the design flow and takes care of the management of the design data, which are stored in the design database. The data about the different cells and technology processes available in the system are stored in the cell library and technology library respectively. In order to change or extend the data in the cell and technology libraries, a separate database interface is provided. Access through this database interface, however, is restricted to authorized designers only, since the data in these libraries directly affect the quality of the resulting designs.

The AMG has been implemented on a workstation environment under the UNIX operating system and uses X11 and OSF Motif windowing software. Almost all the individual tools are developed in the C or C+ + language. The AMG has been linked to the EDDM database and the Falcon framework of Mentor Graphics through a clearly defined data representation interface (DRI) using as much as possible ASCII text files as exchange formats. The use of a clearly defined DRI allows an easy migration to other vendor frameworks, since only the DRI functions will have to be reimplemented without changing the tools. Each of these tools can also be run stand-alone if desired.

3. DESCRIPTION OF THE TOOLS IN THE ANALOGUE MODULE GENERATOR

The different tools used in the AMG are now described in more detail and their operation is illustrated with practical design examples.

3.1. Topology selection

The first step is the selection of the most appropriate circuit topology that can realize the given specifications in the specified technology process out of all alternative topologies stored in the cell library. The task of the topology selector is therefore twofold: (i) eliminate all topologies that are not capable of meeting the input specifications and (ii) rank all remaining topologies in order of preference based on criteria such as circuit complexity, area and power consumption.

A topology selection tool has been developed that consists of the subsequent application of three topology filters to achieve this.5 The flow diagram of the topology selector is depicted in Figure 6. The filtering sequence is a combination of procedural and knowledge-based approaches and consists of the following filters: (i) a boundary-checking filter that checks whether the specifications are within the feasible intervals for each individual performance characteristic, (ii) an interval analysis filter that uses interval analysis to include the relations between the different performances, and (iii) a rule-based filter for possible heuristic modifications to the final ranking. This filtering sequence was chosen to allow an optimal trade-off between selection accuracy and selection speed. The final ranked list is then displayed to the user, who can accept the proposed topology or alternatively select one of the others on the list if he or she prefers to.

3.2. Circuit characterization

The second task is then the sizing of the selected topology towards the given specifications. For this an optimization-based method using analytic models to characterize the circuit performance has been implemented. The use of optimization guarantees design flexibility and also reduces the effort required to add new topologies to the system. At the same time the evaluation of equations is faster than a full simulation at each iteration of the optimization loop.

Each module or circuit topology in the cell library is therefore characterized by a declarative equation- based model (DEBM) consisting of analytic and heuristic knowledge about the module or circuit written in

MIXED ANALOGUE/DIGITAL ASIC DESIGN 277

3oundary Checking\

I

Soecifi cat ions

Spec sheet

' Design history Net list Design style

........................ .................... ................... ,~ ...........................

Figure 6. Flow diagram of the topology selection tool with the sequence of three filters

the form of general (both linear and non-linear) symbolic equations. A key feature for the openness and flexibility of the AMG is that these models are declarative, i.e. they only declare the relations between the different circuit variables without specifying how to use or evaluate these equations to perform the sizing. Other programmes such as IDAC/PlanFrame,* OASYS3 and MIDAS4 suffer from severe flexibility and extendability limitations owing to the hard-coded mix of design equations and dedicated design solution methods that has to be built in the formal design procedures or design plans used in the programme. This

278 G. GIELEN ET AL.

drastically increases the effort required to include new topologies in the system compared with the derivation of purely declarative models.

Furthermore, the analytical design equations in the declarative model of a circuit can to a large extent be extracted automatically by means of symbolic analysis techniques. The symbolic simulator ISAAC6 is used to generate symbolic expressions for all AC characteristics of both continuous-time and switched analogue circuits, including symbolic distortion expressions for weakly non-linear circuits. In this way the time to create the model is greatly reduced and the designer can easily extend the cell library himself or herself. To illustrate this with a simplified example, Figure 7 shows part of the DEBM of the CMOS two-stage Miller- compensated op amp.

3.3. Sizing and optimization

Starting from the declarative model of the selected topology, the sizing tool then has to determine the optimal parameters of the topology subcells such that all specifications are satisfied and some design objectives (e.g. minimal power consumption) are optimized. These objectives have to be selected and weighted by the designer in the input specification sheet depending on the application.

Before being able to evaluate the equations during the optimization iterations, the unordered declarative model first has to be converted into an ordered computational path. This is the task of the DONALD tool,' which first determines the number of degrees of freedom in the model, then selects a set of independent design variables equal to the degrees of freedom and finally derives the symbolic computational path which expresses how all dependent variables have to be calculated numerically once values for the independent variables are given. The ordering is obtained using a graph representation of the DEBM (see e.g. Figure 8) and constraint satisfaction techniques.

The optimization itself is then performed in the OPTIMAN tool, which iteratively selects numerical values for the independent variables according to the selected optimization algorithm, each time evaluating the computational path to calculate all circuit performances and the value of the objective function and the constraints. See Figure 9 for the main flow of this tool. The present OPTIMAN version is a highly improved and extended version compared with the tool presented in Reference 8 and is modular with respect to the optimization algorithm used. In the present version the user can select between a local optimization algorithm (Hooke-Jeeves, hj) and a global one (very fast simulated reannealing, vfsr), which again allows the designer to make a trade-off between optimality of the design solution and CPU time. Results of both algorithms for the same fully differential op amp with

gm6 p2 =

2+( 1 + F) +cgs6)

GBW GBW PM = 90" - arctan- -arctan y- P2

Figure 7. Example of part of the declarative equation-based model of a CMOS two-stage Miller-compensated op amp

MIXED ANALOGUE/DIGITAL ASIC DESIGN 279

Figurc8. Graph

' -b

\

e> PM

representation of the declarative model of Figure 7 used to order the equations in the

I initial values for I input set

-obtained specifications

computational path

Figure 9. Principle flow of the sizing and optimization tool

the same set of specifications are shown in Figure. 10. The vfsr run of course took more CPU time than the hj run.

3.4. Verification

The resulting design after sizing and optimization, and later on also after lay-out generation and extraction, has to be verified more accurately, because during topology selection and sizing, simplified formulae, models or heuristics may have been used or introduced by the designer. This verification requires a whole set of detailed numerical simulations (both nominal behaviour and with variations in process and environmental parameters, e.g. power supply, temperature, etc.) as well as other tests to guarantee the correct operation of the circuit.

280

hj vfsr igbw 14.9 MHz 15.5 MHz

G. GIELEN ET AL.

.- __ 1 1 pFi 1 1 5 0 kOhm 9 9 0 0 h m

.-

__-_

Figure 10. Optimization results obtained with the local (hj) and global (vfsr) optimization algorithms for the same circuit and specifications

For the numerical simulations a link has been established to existing numerical simulators such as the well-known SPICE through the integration within the EDA framework. For the efficient simulation of mixed analogue/digital circuits (e.g. a data converter) also the piecewise linear simulator PLANET9 has further been developed and integrated in the AMG as well. A piecewise linear simulator has the advantages that it permits a unified representation for both analogue and digital circuits at all levels (and therefore is inherently mixed mode, multilevel) and that it allows one to find all solutions of non-linear circuits in rather small CPU times (at the expense of some loss in accuracy because of the piecewise linear approximation of non-linear functions).

If the design passes the verification of the specification constraints, the lay-out phase will be started. Otherwise, redesign has to be performed under control of the designer. Depending on the failure information, the designer must decide what corrective action has to be taken, such as a modification of some internal specifications or the selection of another topology. In order to automatically carry out redesign throughout the design hierarchy, an intelligent backtracking expert system would be required, which at present the authors believe is difficult to implement in a general, non-topology-specific and efficient way. Instead, at the moment backtracking hints are given to the user at any failure point to help him or her decide on the corrective action to be taken.

3.5. Lay-out generation

The final step is the generation of the lay-out of the module. This lay-out introduces parasitic effects that can degrade the module performance or even make the circuit fall outside the specifications. In the case of high-performance analogue modules, preserving the correct operation within the given specifications is therefore more important than generating the most compact lay-out. The analogue and mixed signal lay-out generation tool thus has to take into account all specific analogue lay-out requirements, such as matching, clustering, symmetry, net balancing, reduction of parasitic wire capacitances and resistances, avoidance of cross-talk, temperature balancing, etc., in order to guarantee the correct operation of the circuit after the lay-out phase. To this end a performance-driven lay-out methodology is used, where for the given specifications the margins on the circuit performances remaining after the sizing step are used to constrain and drive the lay-out tools.

The analogue lay-out generation programme in the AMG consists of (i) procedural generators for individual devices as well as for groupings of matched devices, (ii) a placement tool based on simulated annealing that considers symmetry and the performance degradation due to wire parasitics and device mismatches," and (iii) a router that is an extension of a powerful digital channel router. An example of a completed lay-out is shown in Figure 1 1.

The module net list including all actual parasitics is then extracted from the lay-out. A new verification is performed to check the module performance with these parasitics. If the test is successful, the module lay-out

MIXED ANALOGUE/DIGITAL ASIC DESIGN 28 1

,-__-___-___--- ----

Figure I I . Example of a complete lay-out

is passed to the designer or to the higher level in the design hierarchy. If the test fails, redesign has to be carried out as described above.

4. PRACTICAL EXPERIENCES WITH THE ANALOGUE MODULE GENERATOR

The developed analogue module generator has been and still is being tested for a large number of industrial circuit designs. To give a typical example, the CMOS high-speed op amp of Figure 12 is taken. Starting from scratch, the inclusion of this op amp as a custom cell into the AMG cell library (definition of the cell schematic in the EDDM database, derivation of the analytic design equations, derivation and compilation of the corresponding computational path) took about 7 h in total. After this large initial effort the complete

282 G. GIELEN ETAL.

I

I I m7 I

vss Figure 12. High-speed op amp used to evaluate the analogue module generator

synthesis of the op amp (including topology selection, sizing, verification and generation of the lay-out) for a given set of specifications was performed in less than 15 min in total on an HP735.

The synthesis results from this and other circuit designs have indicated the good and efficient functioning of the sizing and optimization and the lay-out generation programmes. Also the topology selection programme works appropriately, but its overall efficiency can only be tested when a really large number of cells is included in the cell library. The largest effort is still the derivation of the design equations, although the time for this has already been reduced quite drastically to one or a few days instead of weeks to months as in previous approaches.’ Moreover, this initial modelling effort has to be carried out only once and the same cell can then be used many times for different sets of specifications and optimization targets. Once the cell is in the AMG library, a complete optimized lay-out can be generated in a time frame of 15 min for the example of Figure 12 using the approach presented in this paper. Other approaches using numerical simulation in the sizing and optimization loop perhaps require less set-up time for a new circuit schematic but take longer CPU times for each optimization, which prohibits the designer from exploring different design alternatives.

5. CONCLUSIONS

An analogue module generator as part of a mixed signal design environment has been presented that covers the complete design path of analogue modules for telecommunications and other applications starting from specification down to lay-out. Several tasks participate in this action: topology selection, sizing and optimization, verification and lay-out generation. The system supports three different design styles, follows a hierarchical performance-driven design strategy, is technology-process-tolerant, easily extendable with new topologies and integrated in a commercial EDA framework.

ACKNOWLEDGEMENTS

This research was developed in part under projects with Philips Research (Netherlands), ESPRIT ADMIRE, ESA-ESTEC and the Belgian IUAP-20.

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1106-116 (1987).