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AN12286Hardware design guidelines for PF81/82 PMIC familyRev. 2.0 — 14 January 2019 Application note

Document informationInformation Content

Keywords PMIC, PF8100, PF8200, PF8101, PF8201, PF8121, i.MX8

Abstract This application note provides a comprehensive list of design guidelines usedfor the hardware development of PF81/82 PMIC family architecture.

NXP Semiconductors AN12286Hardware design guidelines for PF81/82 PMIC family

AN12286 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2019. All rights reserved.

Application note Rev. 2.0 — 14 January 20192 / 21

Revision historyRev Date Description

2.0 20190114 • Document title, keywords and abstract: updated to include PF81/82 PMIC family of devices(PF8101, PF8201, PF8121)

• Global: PF8x00 replaced by PF81/82 PMIC family• Section 1: added description for PF8121, PF8201, PF8101• Section 2: added Figure 2• Section 3.2: added target applications for PF8121• Section 4.1: added note "The unused pins corresponding to the LDO regulator not available in

the PF8101 or PF8201 should be grounded or left unconnected."• Section 5.4: added description• Section 6: added product summary page links for PF8101_PF8201 and PF8121

1.0 20181203 • Initial version




1 Overview

The PF81/82 PMIC family of devices feature power management integrated circuit(PMIC) designed for high performance i.MX 8 and S32V based applications. It featuresvarious devices with multiple high efficiency buck converters with the ability to operatein single or multiphase configuration as well as various linear regulators with selectableswitch mode configuration.

Built-in one-time programmable memory stores key startup configurations, drasticallyreducing external components typically used to set output voltage and sequence ofexternal regulators. Regulator parameters are adjustable through high-speed I2C afterstartup offering flexibility for different system states.

The PF81/82 PMIC family comprises five devices, to address different market needs:

• PF8200 is the flagship version of this family providing a full feature PMIC with sevenswitching regulators and four LDOs, integrating functional safety mechanism to complywith the ISO 26262 standard and providing a powerful and flexible solution for ASILB(D) automotive modules.

• PF8100 is the non-safety version of the higher end device, it features seven switchingregulators and four LDOs, providing all the power management and digital controlincluded in PF8200, without the functional safety overhead to provide an economicplatform for systems not required to meet the ASIL B qualification.

• PF8121 is the consumer version of the higher end device, it features seven switchingregulators and four LDOs, providing same power management and digital control withstandard consumer qualification rating to address a more cost effective platform forconsumer applications.

• PF8201 is a reduced version of this PMIC, featuring five switching regulators and threeLDOs, integrating functional safety mechanism to comply with the ISO 26262 standardand providing a powerful and flexible solution for lower end ASIL B(D) automotivemodules.

• PF8101 is the non-safety version of the PF8201 device, it features five switchingregulators and three LDOs, providing power management and digital control for lowerend application, without the functional safety overhead to provide an economic platformfor systems not required to meet the ASIL B qualification.

All devices provide pin-to-pin compatibility, delivering high power capability with tightload regulation from a small profile 8 x 8 mm, 56-pin QFN package with up to 2.5 Wpower dissipation capability. For this reason, proper component selection and PCBlayout design is necessary to achieve top performance out of the PF81/82 PMIC familyarchitecture.

All design rules provided in this application note apply to all devices in the PF81/82 familyof PMICs.




2 Package pinout

aaa-028049

SDA

56

SCL

55

VDD

IO54

VDD

OTP

53

AMU

X52

AGN

D51

VIN

50

SYN

CO

UT

49

SYN

CIN

48

VSN

VS47

LIC

ELL

46

DG

ND

45

XFAI

LB44

LDO

2EN

43

PGOOD42

V1P5A41

V1P5D40

XINTB39

SW7FB38

SW7IN37

SW7LX36

SW6IN35

SW6LX34

SW5LX33

SW5IN32

SW5FB31

SW6FB30

FSOB29

LDO

1OU

T15

VSEL

ECT

16

LDO

12IN

17

LDO

2OU

T18

WD

I19

EWAR

N20

RES

ETBM

CU

21

PWR

ON

22

STAN

DBY

23

INTB

24

LDO

3OU

T25

LDO

3IN

26

LDO

4IN

27

LDO

4OU

T28

DNC1 1

SW2FB 2

SW1FB 3

SW1IN 4

SW1LX 5

SW2LX 6

SW2INEPAD

7

SW3IN 8

SW3LX 9

SW4LX 10

SW4IN 11

SW4FB 12

SW3FB 13

TBBEN 14

Figure 1. Pin configuration PF8100, PF8200 and PF8121




56 55 54 53 52 51 50 49 48 47 46 45 44 43

PGOOD42

V1P5A41

V1P5D40

XINTB39

SW7FB38

SW7IN37

SW7LX36

SW6IN35

SW6LX34

SW5LX33

SW5IN32

SW5FB31

SW6FB30

FSOB29

15 16 17 18 19 20 21 22 23 24 25 26 27 28

DNC1 1

SW2FB 2

SW1FB 3

SW1IN 4

SW1LX 5

SW2LX 6

SW2INEPAD

7

RSVD1 8

RSVD2 9

RSVD3 10

RSVD4 11

RSVD5 12

RSVD6 13

TBBEN 14

RSV

D7

RSV

D8

LDO

1OU

T

VSEL

ECT

LDO

12IN

LDO

2OU

T

WD

I

EWAR

N

RES

ETBM

CU

PWR

ON

STAN

DBY

INTB

LDO

3OU

T

LDO

3IN

SDA

SCL

VDD

IO

VDD

OTP

AMU

X

AGN

D

VIN

SYN

CO

UT

SYN

CIN

VSN

VS

LIC

ELL

DG

ND

XFAI

LB

LDO

2EN

Figure 2. Pin configuration for PF8101 and PF8201




3 PMIC control schematic design

3.1 I/O interfacing diagram

aaa-028062

GP

IO(o

ptio

nal)

GP

IO(o

ptio

nal)

SD

1_VS

ELE

CT

SD

1_PW

R_E

N_B

VSE

LEC

T

LDO

2EN

PM

IC_O

N_R

EQ

PWR

ON

EAR

LY_W

ARN

ING

EW

AR

N

PGO

OD

FSO

B

VIN/VDDIO VDDIO VDDIO

PM

IC_S

TBY

_RE

QS

TAN

DB

Y

RES

ETB

MC

U

WD

OG

_B

i.MX8 MCU

PMIC1 PMIC2

WD

I

PO

R_B

VDDIO

VDDIO

INTB

INT_

B

TBBE

N

GP

IO(o

ptio

nal)

GP

IO(o

ptio

nal)

SD

2_VS

ELE

CT

SD

2_PW

R_E

N_B

VSE

LEC

T

LDO

2EN

PWR

ON

GP

IO(o

ptio

nal)

GP

IO(o

ptio

nal)

EW

AR

N

PGO

OD

FSO

B

VIN/VDDIO VDDIO VDDIO

STA

ND

BY

RES

ETB

MC

U

WD

I

INTB

TBBE

N

XINTBXINTB

XFAILB

V1P5A

XFAILB

Figure 3. I/O interfacing diagram

Pin # Symbol Pin description Type i.MX8 application connection

MCU interface I/Os

22 PWRON PWRON input I Autostart mode: 100 kΩ pull up to VIN or VSNVSSCU control mode: connected to MCU PMIC_ON_REQ

23 STANDBY STANDBY input I Connected to MCU PMIC_STBY_REQ

19 WDI Watchdog Input from MCU I Connected to MCU WDOG_B

21 RESETBMCU RESETBMCU open drain output O Connected to MCU I/O (POR_B) with 100 kΩ pull up toVDDIO

24 INTB INTB open drain output O Connected to MCU INT_B with a 100 kΩ pull up toVDDIO

20 EWARN Early warning to MCU O Connected to MCU EARLY_WARNING with a 100 kΩpull down to ground

General function I/Os

43 LDO2EN LDO2 Enable pin I Connect to MCU I/O

16 VSELECT LDO2 voltage select input I Connected to MCU SDx_VSELECT

42 PGOOD PGOOD open drain output O Connect to MCU I/O with 100 kΩ pull up to VDDIO

48 SYNCIN External clock input pin forsynchronization

I Connect to external clock signal

49 SYNCOUT Clock out pin for external partsynchronization

O Pin for master clock generation

52 AMUX Analog multiplexer output O Connect to MCU analog to digital converter




Pin # Symbol Pin description Type i.MX8 application connection

29 FSOB Safety output pin O Connected to safety output monitoring I/O on MCU witha 100 kΩ pull up to VDDIOOptional system interface pin with a 470 kΩ pull up toVIN

55 SCL I2C synchronous clock I 2.2 kΩ pull up to VDDIO

56 SDA I2C data line I/O 2.2 kΩ pull up to VDDIO

PMIC interface I/Os

39 XINTB External Interrupt Input I Connected to companion PMIC INTB pin with a 100 kΩpull up to VDDIO

44 XFAILB External fail detection and PMICsynchronization pin

I/O Connect to companion PMIC XFAILB with a 100 kΩ pullup to its own V1P5A

14 TBBEN Try before buy enable pin I GND

PMIC core supplies

46 LICELL Coin cell input I/O Connected to coin cell battery with 22 nF capacitor

54 VDDIO System I/O supply I Bypass with a 0.1 µF capacitor

47 VSNVS VSNVS regulator output O Connected to SNVS_4.2_IN domain in MCU with a2.2 µF capacitor

41 V1P5A Internal 1.5 V analog supplydecoupling pin

O Bypass with 1.0 µF capacitor

40 V1P5D Internal 1.5 V digital supplydecoupling pin

O Bypass with 1.0 µF capacitor

3.2 PMIC control signalsThe PF8100, PF8200, PF8101, and PF8201 are targeted for a range of automotiveapplications, including high end Infotainment, gateways and interface cluster. For thisreason, it has been defined to comply with the AEC-Q100 automotive standard. In orderto fulfill the automotive standards at system level, it is encouraged to use automotivegrade components.

The PF8121 is targeted for consumer applications, including IoT and hand-held devices.For this type of applications, standard components may be used in order to achieve costeffective bill of materials.




Figure 4. PMIC control signals

3.3 Special use case configurationsOne of the main features of the PF81/82 PMIC family is the flexibility to configure thedefault configuration of the system as well as provide full control of the PMIC during thesystem-on state via the I2C communication bus.

The default configuration (OTP) can be defined and programmed in several ways:

• For high volume opportunities, NXP may offer full device customization, includingdefault OTP programing and custom part marking.

• For lower volume opportunities, NXP will work with distributors to enable them toprovide in-house programming of the PF81/82 PMIC family for their customers.

• On-board device programming is available for customers that require in-houseprogramming out of their production line.

For customers opting for on-board OTP configuration, a special configuration is requiredto allow proper access to the PMIC configuration signals without interfering or damagingany components from the main system. Figure 5 shows the recommended configurationcompatible with NXP programming tools.




Figure 5. Programming interface

Note: Programming interface connector pinout shown in Figure 5 is compatible with theKITPF8200FRDMPGM programming tool.

Note: Configuration signal may require isolation from the main system in order to allowproper communication with the PMIC during OTP programming procedure. Such isolationmay be achieved via two row pin headers, 0 Ω resistor arrays or a dip switch array.

Note: PMIC_ON_REQ pull up may be moved to the SNVS_SCU_V1P8 domain on i.MX8processor or not connected when the PMIC_ON_REQ is a push pull driver.

3.4 Unused pin terminationWhen a specific feature is not required on the system, certain rules should be followedto properly terminate the unused pins on the system. Likewise, some software/OTPconfiguration may be required to ensure proper operation of the PMIC. Table 1 providesall considerations for unused pin termination.




Table 1. Unused functional pin terminationPin # Symbol Termination if not used Software/OTP considerations

1 NC1 1. NC2. GND

14 TBBEN GND

16 VSELECT GND OTP_VSELECTEN = 0

19 WDI GND OTP_WDI_INV = 0

20 EWARN 100 kΩ pulled down to GND

21 RESETBMCU 100 kΩ pulled up to VDDIO

22 PWRON N/A

23 STANDBY GND OTP_STBY_INV = 0

24 INTB 100 kΩ pulled up to VDDIO All interrupt mask = 1

29 FSOB 100 kΩ pulled up to VDDIO/VIN OTP_ASS_FSOB = 0OTP_FSOB configuration bits= 0

39 XINTB 1. NC2. 100 kΩ pulled up to VDDIO

42 PGOOD 1. NC2. 100 kΩ pulled up to VDDIO

1. All OTP_SWx_PG_EN bits =0 and OTP_LDOx_PG_EN bits= 0

43 LDO2EN GND OTP_LDO2EN = 0

44 XFAILB 1. GND2. 100 kΩ pulled up to V1P5A

OTP_XFAIL_EN = 0

46 LICELL 22 nF cap COINCHG_EN = 0COINCHG_OFF = 0

47 VSNVS 2.2 µF OTP_VSNVS = 00

48 SYNCIN GND OTP_SYNCIN_EN = 0

49 SYNCOUT 1. NC2. 100 kΩ pulled down to GND

OTP_SYNCOUT_EN = 0

52 AMUX 1. NC2. 100 kΩ pulled down to GND

AMUX_EN = 0

4 Power supplies schematic design

LDO regulators schematic requirements are straight forward, requiring only the inputcapacitance and output capacitance as shown in Figure 6.




Figure 6. PMIC LDO regulators

Input/output capacitors must be rated at least twice the value of the input in the pin. Forinput capacitors, it is recommended to use at least a 10 V or 16 V rating and for outputcapacitors at least 6.3 V to 10 V rating to minimize capacitance variation overvoltage.

Switching regulators require the following components:

• 4.7 µF input capacitor rated at least 10 V or 16 V.• 1.0 µH inductor with saturation current higher than the current limit selected for the

application. DCR < 40 mΩ is recommended to improve efficiency performance of theregulator.

• 2 x 22 µF output capacitor rated at least 6.3 V. Multiple capacitors are required toimprove total ESR of the output capacitor.

• Both input and output may add a small 0.1 µF capacitor for decoupling high frequencynoise on the pins, however the noise reduction impact with these capacitors is minimaland they may be excluded if desired.




Figure 7. PMIC switching regulators

4.1 Terminating unused regulator pinsFor unused LDO regulators, the pins must be terminated as indicated below:

1. LDO1 and LDO2 not used• LDO1OUT = GND• LDO12IN = GND• LDO2OUT = GND

2. LDO1 or LDO2 not used• Unused LDOxOUT = GND• LDO12IN = Connect to LDO input (to supply input for the LDO in use)

3. LDO2 or LDO4 not used• LDOxIN = GND• LDOxOUT = GND

Note: The unused pins corresponding to the LDO regulator not available in the PF8101or PF8201 should be grounded or left unconnected.

For unused switching regulators, the pins can be terminated as shown in Table 2.

Table 2. Switching regulator terminationNo connects allowed (preferred) [1] Physical termination required

SWxIN = VIN SWxIN = GND

SWxLX = not connected SWxLX = GND

SWxFB = GND SWxFB = GND




[1] The unused pins corresponding to the SW regulator not available in the PF8101 or PF8201 should be grounded or leftunconnected.

5 PCB layout recommendations

5.1 General layout recommendations1. The PF81/82 PMIC family pinout is defined in such a way that it can be laid-out in as

little as four layers, however, at least six layers are recommended to provide propershielding and grounding to minimize ground loops and ensure proper operation.• High current signals• GND• Signal• Signal• GND• High current signal

2. Allocate TOP layer for main component placement and output power routing of theswitching regulators and LDOs; place a dynamic copper plane to ground on theunused area.

3. Allocate bottom layer for input power routing; place a dynamic copper plane to groundon the unused area.

4. Use internal layers sandwiched between two GND planes for the SIGNAL routing.5. It is desirable to keep all components related to the power stage as close to the PMIC

as possible, specially decoupling input and output capacitors.

5.2 General routing requirements1. Some recommended rules to keep in mind for manufacturability:

• Via in pads require a 4.5 mil minimum annular ring. Pad must be 9.0 mils larger thanthe hole

• Maximum copper thickness for lines less than 5.0 mils wide is 0.6 oz copper• Minimum allowed spacing between line and hole pad is 3.5 mils• Minimum allowed spacing between line and line is 3.0 mils

2. Care must be taken with SWxFB pins traces. These signals are susceptible to noiseand must be routed far away from power, clock, or high-power signals, like the oneson the SWxIN, SWx, SWxLX pins.

3. Run feedback traces of the regulators in the inner layers to keep them shielded fromthe power and noise nodes.

4. Avoid coupling V1P5D, V1P5A traces with any high current, high-speed switchingnodes (i.e. SWxLX nodes).

5. Make sure all components related to a specific block are referenced to thecorresponding ground. Use through vias to connect signals to the closest groundplane to minimize the ground loop.

5.3 Switching regulators layout recommendations1. Per design, the switching regulators in PF81/82 PMIC family, are designed to operate

with only one input bulk capacitor. Depending on the strategy and the specific PCBlayout design rules, the input capacitor can be placed on the top layer as close aspossible to the input pin, or placed on the bottom layer underneath the PMIC, usingenough vias to connect to the Input pin and to the expose path.




2. A high frequency filter input capacitor (CIN_hf), can be added to help filter out highfrequency noise at the regulator input. This capacitor should be in the range of 100 nFand should be placed right next to or under the IC, closest to the IC pins.

3. Make the LX nodes as wide and short as possible to minimize the trace inductanceand improve the output efficiency.

4. Make high-current traces as symmetrical as possible for dual or quad phaseregulators.

Figure 8. Switching regulators placement and routing examples

5.4 Six layers PCB layout exampleThe following figure shows a layout exampled based on the higher end devices featuringseven switching regulators and four LDOs.




Figure 9. Top layer - Power

Figure 10. Inner 2 - GND




Figure 11. Inner 3 - Signal

Figure 12. Inner 4 - Signal




Figure 13. Inner 5 - GND

Figure 14. Bottom layer - Power




6 References

Support page Description URL

PF8100_PF8200 product summary page http://www.nxp.com/PF8100-PF8200

PF8101_PF8201 product summary page http://www.nxp.com/PF8101-PF8201

PF8121 product summary page http://www.nxp.com/PF8121

http://www.nxp.com/PF8100-PF8200

http://www.nxp.com/PF8101-PF8201

http://www.nxp.com/PF8121




7 Legal information

7.1 DefinitionsDraft — The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result inmodifications or additions. NXP Semiconductors does not give anyrepresentations or warranties as to the accuracy or completeness ofinformation included herein and shall have no liability for the consequencesof use of such information.

7.2 DisclaimersLimited warranty and liability — Information in this document is believedto be accurate and reliable. However, NXP Semiconductors does notgive any representations or warranties, expressed or implied, as to theaccuracy or completeness of such information and shall have no liabilityfor the consequences of use of such information. NXP Semiconductorstakes no responsibility for the content in this document if provided by aninformation source outside of NXP Semiconductors. In no event shall NXPSemiconductors be liable for any indirect, incidental, punitive, special orconsequential damages (including - without limitation - lost profits, lostsavings, business interruption, costs related to the removal or replacementof any products or rework charges) whether or not such damages are basedon tort (including negligence), warranty, breach of contract or any otherlegal theory. Notwithstanding any damages that customer might incur forany reason whatsoever, NXP Semiconductors’ aggregate and cumulativeliability towards customer for the products described herein shall be limitedin accordance with the Terms and conditions of commercial sale of NXPSemiconductors.

Right to make changes — NXP Semiconductors reserves the right tomake changes to information published in this document, including withoutlimitation specifications and product descriptions, at any time and withoutnotice. This document supersedes and replaces all information supplied priorto the publication hereof.

Applications — Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makesno representation or warranty that such applications will be suitablefor the specified use without further testing or modification. Customersare responsible for the design and operation of their applications andproducts using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer productdesign. It is customer’s sole responsibility to determine whether the NXPSemiconductors product is suitable and fit for the customer’s applicationsand products planned, as well as for the planned application and use ofcustomer’s third party customer(s). Customers should provide appropriatedesign and operating safeguards to minimize the risks associated withtheir applications and products. NXP Semiconductors does not accept anyliability related to any default, damage, costs or problem which is basedon any weakness or default in the customer’s applications or products, orthe application or use by customer’s third party customer(s). Customer isresponsible for doing all necessary testing for the customer’s applicationsand products using NXP Semiconductors products in order to avoid adefault of the applications and the products or of the application or use bycustomer’s third party customer(s). NXP does not accept any liability in thisrespect.

Suitability for use in automotive applications — This NXPSemiconductors product has been qualified for use in automotiveapplications. Unless otherwise agreed in writing, the product is not designed,authorized or warranted to be suitable for use in life support, life-critical orsafety-critical systems or equipment, nor in applications where failure ormalfunction of an NXP Semiconductors product can reasonably be expectedto result in personal injury, death or severe property or environmentaldamage. NXP Semiconductors and its suppliers accept no liability forinclusion and/or use of NXP Semiconductors products in such equipment orapplications and therefore such inclusion and/or use is at the customer's ownrisk.

Export control — This document as well as the item(s) described hereinmay be subject to export control regulations. Export might require a priorauthorization from competent authorities.

Translations — A non-English (translated) version of a document is forreference only. The English version shall prevail in case of any discrepancybetween the translated and English versions.

7.3 TrademarksNotice: All referenced brands, product names, service names andtrademarks are the property of their respective owners.

I2C-bus — logo is a trademark of NXP B.V.NXP — is a trademark of NXP B.V.




TablesTab. 1. Unused functional pin termination ................... 10 Tab. 2. Switching regulator termination ....................... 12

FiguresFig. 1. Pin configuration PF8100, PF8200 and

PF8121 ..............................................................4Fig. 2. Pin configuration for PF8101 and PF8201 ........ 5Fig. 3. I/O interfacing diagram ......................................6Fig. 4. PMIC control signals ......................................... 8Fig. 5. Programming interface ...................................... 9Fig. 6. PMIC LDO regulators ......................................11Fig. 7. PMIC switching regulators .............................. 12

Fig. 8. Switching regulators placement and routingexamples ......................................................... 14

Fig. 9. Top layer - Power ........................................... 15Fig. 10. Inner 2 - GND ................................................. 15Fig. 11. Inner 3 - Signal ............................................... 16Fig. 12. Inner 4 - Signal ............................................... 16Fig. 13. Inner 5 - GND ................................................. 17Fig. 14. Bottom layer - Power ...................................... 17


Please be aware that important notices concerning this document and the product(s)described herein, have been included in section 'Legal information'.

© NXP B.V. 2019. All rights reserved.For more information, please visit: http://www.nxp.comFor sales office addresses, please send an email to: [email protected]

Date of release: 14 January 2019Document identifier: AN12286

Contents1 Overview .............................................................. 32 Package pinout ................................................... 43 PMIC control schematic design .........................63.1 I/O interfacing diagram ...................................... 63.2 PMIC control signals ......................................... 73.3 Special use case configurations ........................ 83.4 Unused pin termination ......................................94 Power supplies schematic design ...................104.1 Terminating unused regulator pins .................. 125 PCB layout recommendations ......................... 135.1 General layout recommendations ....................135.2 General routing requirements .......................... 135.3 Switching regulators layout

recommendations ............................................ 135.4 Six layers PCB layout example ....................... 146 References ......................................................... 187 Legal information ..............................................19

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