dma

496 CHAPTER 12 INTERRUPTS

11. Explain how a type 0 interrupt occurs.12. Where is the interrupt descriptor table located for protected mode operation?13. Each protected mode interrupt descriptor contains what information?14. Describe the differences between a protected and real mode interrupt.15. Describe the operation of the BOUND instruction.16. Describe the operation of the INTO instruction.17. What memory locations contain the vector for an INT 44H instruction?18. Explain the operation of the IRET instruction.19. What is the purpose of interrupt vector type number 7?20. List the events that occur when an interrupt becomes active.21. Explain the purpose of the interrupt flag (IF).22. Explain the purpose of the trap flag (TF).23. How is IF cleared and set?24. How is TF cleared and set?25. The NMI interrupt input automatically vectors through which vector type number?26. Does the INTA signal activate for the NMI pin?27. The INTR input is _______ -sensitive.28. The NMI input is _______ -sensitive.29. When the INTA signal becomes a logic 0, it indicates that the microprocessor is waiting for

an interrupt __________ number to be placed on the data bus (DO-D7).30. What is a FIFO?31. Develop a circuit that places interrupt type number 86H on the data bus in response to the

INTR input.32. Develop a circuit that places interrupt type number CCH on the data bus in response to the

INTR input.33. Explain why pull-up resistors on DO-D7 cause the microprocessor to respond with interrupt

vector type number FFH for the INTA pulse.34. What is a daisy-chain?35. Why must interrupting devices be polled in a daisy-chained interrupt system?36. Whatisthe8259A?37. How many 8259As are required to have 64 interrupt inputs?38. What is the purpose of the IRO-IR7 pins on the 8259A?39. When are the CAS2-CASO pins used on the 8259A?40. Where is a slave INT pin connected on the master 8259A in a cascaded system?41. WhatisanlCW?42. What is an OCW?43. How many ICWs are needed to program the 8259A when operated as a single master in a

system?44. Where is the vector type number stored in the 8259A?45. Where is the sensitivity of the IR pins programmed in the 8259A?46. What is the purpose of ICW1?47. What is a non-specific EOI?48. Explain priority rotation in the 8259A.49. What is the purpose of IRR in the 8259A?50. At which I/O ports is the master 8259A PIC found in the personal computer?51. At which I/O ports is the slave 8259A found in the personal computer?

CHAPTER 13

Direct Memory Accessand DMA-Controlled I/O

INTRODUCTION

In previous chapters, we discussed basic and interrupt-processed I/O. Now we turn to the finalform of I/O called direct memory access (DMA). The DMA I/O technique provides direct ac-cess to the memory while the microprocessor is temporarily disabled. This allows data to betransferred between memory and the I/O device at a rate that is limited only by the speed of thememory components in the system or the DMA controller. The DMA transfer speed can ap-proach 32-40 M-byte transfer rates with today's high-speed RAM memory components.

DMA transfers are used for many purposes, but more common are DRAM refresh, videodisplays for refreshing the screen, and disk memory system reads and writes. The DMAtransfer is also used to do high-speed memory-to-memory transfers.

This chapter also explains the operation of disk memory systems and video systems thatare often DMA-processed. Disk memory includes floppy, fixed, and optical disk storage. Videosystems include digital and analog monitors.

CHAPTER OBJECTIVES

Upon completion of this chapter, you will be able to:

1. Describe a DMA transfer.2. Explain the operation of the HOED and HEDA direct memory access control signals.3. Explain the function of the 8237 DMA controller when used for DMA transfers.4. Program the 8237 to accomplish DMA transfers.5. Describe the disk standards found in personal computer systems.6. Describe the various video interface standards that are found in the personal computer.

13-1 BASIC DMA OPERATION

Two control signals are used to request and acknowledge a direct memory access (DMA)transfer in the microprocessor-based system. The HOED pin is an input that is used to request aDMA action and the HEDA pin is an output that acknowledges the DMA action. Figure 13-1shows the timing that is typically found on these two DMA control pins.

497

498

FIGURE 13-1 HOLD andHLDA timing for the micro-processor.

CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O

orT.

CLK

HOLD

HLDA

Whenever the HOLD input is placed at a logic 1 level, a DMA action (hold) is re-quested. The microprocessor responds, within a few clocks, by suspending the execution ofthe program and by placing its address, data, and control bus at their high-impedance states.The high-impedance state causes the microprocessor to appear as if it has been removed fromits socket. This state allows external I/O devices or other microprocessors to gain access tothe system buses so that memory can be accessed directly.

As the timing diagram indicates, HOLD is sampled in the middle of any clocking cycle.Thus, the hold can take effect any time during the operation of any instruction in the micro-processor's instruction set. As soon as the microprocessor recognizes the hold, it stops executingsoftware and enters hold cycles. Note that the HOLD input has a higher priority than the INTRor NMI interrupt inputs. Interrupts take effect at the end of an instruction, while a HOLD takeseffect in the middle of an instruction. The only microprocessor pin that has a higher priority thana HOLD is the RESET pin. Note that the HOLD input may not be active during a RESET or thereset is not guaranteed.

The HLDA signal becomes active to indicate that the microprocessor has indeed placed itsbuses at their high-impedance state, as can be seen in the timing diagram. Note that there are afew clock cycles between the time that HOLD changes and until HLDA changes. The HLDAoutput is a signal to the external requesting device that the microprocessor has relinquished con-trol of its memory and I/O space. You could call the HOLD input a DMA request input and theHLDA output a DMA grant signal.

Basic DMA DefinitionsDirect memory accesses normally occur between an I/O device and memory without the use ofthe microprocessor. A DMA read transfers data from the memory to the I/O device. A DMAwrite transfers data from an I/O device to memory. In both operations, the memory and I/O arecontrolled simultaneously, which is why the system contains separate memory and I/O controlsignals. This special control bus structure of the microprocessor allows DMA transfers. A DMAread causes both the MRDC and IOWC signals to simultaneously activate, transferring data fromthe memory to the I/O device. A DMA write causes the MWTC and IORC signals to both acti-vate. These control bus signals are available to all microprocessors in the Intel family except the8086/8088 system. The 8086/8088 require their generation with either a system controller or acircuit such as the one illustrated in Figure 13-2. The DM A controller provides the memory withits address and a signal from the controller (DACK) selects the I/O device during the DMAtransfer.

The data transfer speed is determined by the speed of the memory device or a DMA con-troller that often controls DMA transfers. If the memory speed is 100 ns, DMA transfers occur atrates of up to 1/100 ns or 10 M-bytes per second. If the DMA controller in a system functions ata maximum rate of 5 MHz and we still use 100 ns memory, the maximum transfer rate is 5 MHzbecause the DMA controller is slower than the memory. In many cases, the DMA controllerslows the speed of the system when DMA transfers occur.

13-2 THE 8237 DMA CONTROLLER 499

FIGURE 13-2 A circuit thatgenerates system control sig-nals in a DMA environment.

W/R

M/iO

Vcc

10K

HL

l[\02

V^74F04

DA

2, 3

56

, 11101413

15,,1~

1A1B2A2B3A3B4A4B

GA/B

1Y

2Y

3Y

4Y

4 IPlRP

7 IOWC9 MRpr1-

1~ MWTC

74F257

13-2 THE 8237 DMA CONTROLLER

The 8237 DMA controller supplies the memory and I/O with control signals and memory ad-dress information during the DMA transfer. The 8237 is actually a special-purpose micro-processor whose job is high-speed data transfer between memory and the I/O. Figure 13-3shows the pin-out and block diagram of the 8237 programmable DMA controller. Although thisdevice may not appear as a discrete component in modern microprocessor-based systems, it doesappear within system controller chip-sets found in most systems. Although not described be-cause of its complexity, the chip set (82357 ISP or integrated system peripheral controller) andits integral set of two DMA controllers are programmed exactly as the 8237. The ISP also pro-vides a pair of 8259A programmable interrupt controllers for the system.

The 8237 is a four-channel device that is compatible with the 8086/8088 microprocessors.The 8237 can be expanded to include any number of DMA channel inputs, although four chan-nels seem to be adequate for many small systems. The 8237 is capable of DMA transfers at ratesof up to 1.6M bytes per second. Each channel is capable of addressing a full 64K-byte section ofmemory and can transfer up to 64K bytes with a single programming.

Pin Definitions

CLK

cs

RESET

READY

The clock input is connected to the system clock signal as long as thatsignal is 5 MHz or less. In the 8086/8088 system, the clock must beinverted for the proper operation of the 8237.Chip select enables the 8237 for programming. The CS pin is normallyconnected to the output of a decoder. The decoder does not use the8086/8088 control signal IO/M (M/IO) because it contains the newmemory and I/O control signals (MEMR, MEMW, IOR, and IOW).The reset pin clears the command, status, request, and temporaryregisters. It also clears the first/last flip-flop and sets the mask register.This input primes the 8237 so it is disabled until programmedotherwise.A logic 0 on the ready input causes the 8237 to enter wait states forslower memory and/or I/O components.

500 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-2 THE 8237 DMA CONTROLLER 501

FIGURE 13-3 The 8237A-5 programmable DMA controller, (a) Block diagram, and (b) pin-out.(Courtesy of Intel Corporation.)

HLDA A hold acknowledge signals the 8237 that the microprocessor hasrelinquished control of the address, data, and control buses.

DREQ3-DREQO The DMA request inputs are used to request a DMA transfer for eachof the four DMA channels. Because the polarity of these inputs isprogrammable, they are either active-high or active-low inputs.

DB7-DBO The data bus pins are connected to the microprocessor data busconnections and are used during the programming of the DMAcontroller.

IOR I/O read is a bi-directional pin used during programming and during aDMA write cycle.

IOW I/O write is a bi-directional pin used during programming and during aDMA read cycle.

EOF End-of-process is a bi-directional signal that is used as an input toterminate a DMA process or as an output to signal the end of the DMAtransfer. This input is often used to interrupt a DMA transfer at the endof a DMA cycle.

A3-AO These address pins select an internal register during programming andalso provide part of the DMA transfer address during a DMA action.

A7-A4 These address pins are outputs that provide part of the DMA transferaddress during a DMA action.

HRQ Hold request is an output that connects to the HOLD input of themicroprocessor in order to request a DMA transfer.

DACK3-DACKO DMA channel acknowledge outputs acknowledge a channel DMArequest. These outputs are programmable as either active-high or active-low signals. The DACK outputs are often used to select the DMAcontrolled I/O device during the DMA transfer.

AEN The address enable signal enables the DMA address latch connected tothe DB7-DBO pins on the 8237. It is also used to disable any buffers inthe system connected to the microprocessor.

ADSTB Address strobe functions as ALE, except that it is used by the DMAcontroller to latch address bits A15-A8 during the DMA transfer.

MEMR Memory read is an output that causes memory to read data during aDMA read cycle.

MEMW Memory write is an output that causes memory to write data during aDMA write cycle.

Internal Registers

CAR The current address register is used to hold the 16-bit memoryaddress used for the DMA transfer. Each channel has its own currentaddress register for this purpose. When a byte of data is transferredduring a DMA operation, the CAR is either incremented ordecremented, depending on how it is programmed.

CWCR The current word count register programs a channel for the numberof bytes (up to 64K) transferred during a DMA action. The numberloaded into this register is one less than the number of bytes transferred.For example, if a 10 is loaded into the CWCR, then 11 bytes aretransferred during the DMA action.

BA and BWC The base address (BA) and base word count (BWC) registers are usedwhen auto-initialization is selected for a channel. In the auto-initialization mode, these registers are used to reload both the CAR andCWCR after the DMA action is completed. This allows the same countand address to be used to transfer data from the same memory area.

CR The command register programs the operation of the 8237 DMAcontroller. Figure 13-4 depicts the function of the command register.

The command register uses bit position 0 to select the memory-to-memory DMA transfer mode. Memory-to-memory DMA transfers useDMA channel 0 to hold the source address and DMA channel 1 to hold thedestination address. (This is similar to the operation of a MOVSB instruc-tion.) A byte is read from the address accessed by channel 0 and saved

FIGURE 13-4 8237 A-5command register. (Courtesyof Intel Corporation.)

7 6 5 4 3 2 1 (Hi.i.u.i.iTTi -Bit Number

k o Memory-to memory disable1 Memory-to-memory enable

' 0 Channel 0 address hold disable

.X Ifbit0 = 0___ T 0 Controller enable

L 1 Controller disable' 0 Normal timing

.X If bit 0 = 1F 0 Fixed priorityL 1 Rotating priorityI" 0 Late write selection

LX If bit 3 = 1T 0 DREQ sense active hiahL 1 DREQ sense active lowf 0 DACK sense active lowL 1 DACK sense active high

502 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O

MR

within the 8237 in a temporary holding register. Next, the 8237 initiatesa memory write cycle, in which the contents of the temporary holdingregister are written into the address selected by DMA channel 1. Thenumber of bytes transferred is determined by the channel 1 count register.

The channel 0 address hold enable bit (bit position 1) programschannel 0 for memory-to-memory transfers. For example, if you mustfill an area of memory with data, channel 0 can be held at the sameaddress while channel 1 changes for memory-to-memory transfer. Thiscopies the contents of the address accessed by channel 0 into a block ofmemory accessed by channel 1.

The controller enable/disable bit (bit position 2) turns the entirecontroller on and off. The normal and compressed bit (bit position 3)determine whether a DMA cycle contains 2 (compressed) or 4 (normal)clocking periods. Bit position 5 is used in normal timing to extend thewrite pulse so it appears one clock earlier in the timing for I/O devicesthat require a wider write pulse.

Bit position 4 selects priority for the four DMA channel DREQinputs. In the fixed priority scheme, channel 0 has the highest priorityand channel 3 has the lowest. In the rotating priority scheme, the mostrecently serviced channel assumes the lowest priority. For example, ifchannel 2 just had access to a DMA transfer, it assumes the lowestpriority and channel 3 assumes the highest priority position. Rotatingpriority is an attempt to give all channels equal priority.

The remaining two bits (bit positions 6 and 7) program the polaritiesof the DREQ inputs and the DACK outputs.The mode register programs the mode of operation for a channel.Note that each channel has its own mode register (see Figure 13-5),as selected by bit positions 1 and 0. The remaining bits of the moderegister select the operation, auto-initialization, increment/decrement,and mode for the channel. Verification operations generate the DMAaddresses without generating the DMA memory and I/O control signals.

The modes of operation include demand mode, single mode, blockmode, and cascade mode. Demand mode transfers data until an external

FIGURE 13-5 8237A-5mode register (Courtesy ofIntel Corporation).

7 6 5 4 3 2 1 CHen———— -Bit Number

00 Channel 0 select01 Channel 1 select10 Channel 2 select11 Channel 3 select

[" 00 Verify transfer01 Write transfer10 Read transfer11 Illegal

LXX If bits 6 and 7 = 110 Autoinitialization disable1 Autoinitialization enable0 Address increment select1 Address decrement select

00 Demand mode select01 Single mode select10 Block mode select11 Cascade mode select

13-2 THE 8237 DMA CONTROLLER

FIGURE 13-6 8237A-5 re-quest register. (Courtesy ofIntel Corporation.)

503

5 4 3 2 1 0 ^

RR

MRSR

MSR

SR

-Bit Number

00 Select channel 001 Select channel 110 Select channel 211 Select channel 30 Reset request bit1 Set request bit

EOF is input or until the DREQ input becomes inactive. Single modereleases the HOLD after each byte of data is transferred. If the DREQpin is held active, the 8237 again requests a DMA transfer through theDRQ line to the microprocessor's HOED input. Block mode automati-cally transfers the number of bytes indicated by the count register forthe channel. DREQ need not be held active through the block modetransfer. Cascade mode is used when more than one 8237 is presentin a system.The request register is used to request a DMA transfer via software(see Figure 13-6). This is very useful in memory-to-memory transfers,where an external signal is not available to begin the DMA transfer.The mask register set/reset sets or clears the channel mask, asillustrated in Figure 13-7. If the mask is set, the channel is disabled.Recall that the RESET signal sets all channel masks to disable them.The mask register (see Figure 13-8) clears or sets all of the masks withone command instead of individual channels, as with the MRSR.The status register shows the status of each DMA channel (seeFigure 13-9). The TC bits indicate whether the channel has reached itsterminal count (transferred all its bytes). Whenever the terminal countis reached, the DMA transfer is terminated for most modes of operation.The request bits indicate whether the DREQ input for a given channelis active.

FIGURE 13-7 8237A-5mask register set/resetmode. (Courtesy of IntelCorporation.)

FIGURE 13-8 8237A-5mask register. (Courtesy ofIntel Corporation.)

7 6 5 4 3 2 1 0-*I I I I I I I I I

-Bit Number

Don't Care

7 6 5 4 3 2 1 0 * -I I I I I I I I I

Don't Care k4-t

r

[ 00 Select channel 0 mask bit01 Select channel 1 mask bit10 Select channel 2 mask bit11 Select channel 3 mask bit

" 0 Clear mask bit. 1 Set mask bit

-Bit Number

0 Clear channel 0 mask bit1 Set channel 0 mask bit0 Clear channel 1 mask bit1 Set channel 1 mask bit0 Clear channel 2 mask bit1 Set channel 2 mask bit

0 Clear channel 3 mask bit1 Set channel 3 mask bit


FIGURE 13-9 8237A-5status register. (Courtesy ofIntel Corporation.)

7 6 5 4 3 2 1 -Bit Number1 1 1 1 1 1 1 1

' — 1 Channel 0 has reached TC' ——— 1 Channel 1 has reached TC

1 ———— 1 Channel 2 has reached TC

' ————————————— 1 Channel 3 reauest

Software CommandThree software commands are used to control the operation of the 8237. These commands do nothave a binary bit pattern, as do the various control registers within the 8237. A simple output tothe correct port number enables the software command. Figure 13-10 shows the I/O port assign-ments that access all registers and the software commands.

The function of the software commands are explained in the following list:

1. Clear the first/last flip-flop—Clears the first/last (F/L) flip-flop within the 8237. The F/Lflip-flop selects which byte (low or high order) is read/written in the current address and cur-rent count registers. If F/L = 0, the low order byte is selected; if F/L = 1, the high order byteis selected. Any read or write to the address or count register automatically toggles the F/Lflip-flop.

2. Master clear—Acts exactly the same as the RESET signal to the 8237. As with the RESETsignal, this command disables all channels.

3. Clear mask register—Enables all four DMA channels.

Programming the Address and Count RegistersFigure 13-11 illustrates the I/O port locations for programming the count and address registersfor each channel. Notice that the state of the F/L flip-flop determines whether the LSB or MSBis programmed. If the state of the F/L flip-flop is unknown, the count and address could be pro-grammed incorrectly. It is also important that the DMA channel be disabled before its addressand count are programmed.

FIGURE 13-10 8237 A-5command and control port as-signments. (Courtesy of IntelCorporation.)

SignalsA31111111111111111

A20n0oo0n011111111

A10000111100001111

AO0011001100110011

IOR0101010101010101

IOW1010101010101010

Operation

Read Status RegisterWrite Command RegisterIllegalWrite Request RegisterIllegalWrite Single Mask Register BitIllegalWrite Mode RegisterIllegalClear Byte Pointer Flip/FlopRead Temporary RegisterMaster ClearIllegalClear Mask RegisterIllegalWrite All Mask Register Bits


0

1

2

3

Base and Current Address

Current Address

Base and Current Word Count

Current Word Count


Current Address


Current Word Count


Current Address


Current Word Count


Current Address


Current Word Count

Write

Read

Write

Read

Write

Read

Write

Read

Write

Read

Write

Read

Write

Read

Write

Read

Signals

CS IOR IOW A3 A2 A1 AO0 1 0 0 0 0 00 1 0 0 0 0 00 0 1 0 0 0 00 0 1 0 0 0 00 1 0 0 0 0 10 1 0 0 0 0 10 0 1 0 0 0 10 0 1 0 0 0 10 1 0 0 0 1 00 1 0 0 0 1 0

0 0 1 0 0 1 00 0 1 0 0 1 00 1 0 0 0 1 10 1 0 0 0 1 10 0 1 0 0 1 10 0 1 0 0 1 10 1 0 0 1 0 00 1 0 0 1 0 00 0 1 0 1 0 00 0 1 0 1 0 00 1 0 0 1 0 10 1 0 0 1 0 10 0 1 0 1 0 10 0 1 0 1 0 10 1 0 0 1 1 00 1 0 0 1 1 00 0 1 0 1 1 00 0 1 0 1 1 00 1 0 0 1 1 10 1 0 0 1 1 10 0 1 0 1 1 10 0 1 0 1 1 1

Internal Flip-Flop

01

010101010101010101010101010101

L/atcl DllS UDU-UD/

AO-A7A8-A15AO-A7A8-A15WO-W7W8-W15WO-W7W8-W15AO-A7A8-A15AO-A7A8-A15WO-W7W8-W15WO-W7W8-W15AO-A7A8-A15AO-A7A8-A15WO-W7W8-W15WO-W7W8-W15AO-A7A8-A15AO-A7A8-A15WO-W7W8-W15WO-W7W8-W15

FIGURE 13-11 8237A-5 DMA channel I/O port addresses. (Courtesy of Intel Corporation.)

There are four steps required to program the 8237: (1) the F/L flip-flop is cleared using aclear F/L command, (2) the channel is disabled, (3) the LSB and then MSB of the address areprogrammed, and (4) the LSB and MSB of the count are programmed. Once these four opera-tions are performed, the channel is programmed and ready to use. Additional programming is re-quired to select the mode of operation before the channel is enabled and started.

The 8237 Connected to the 80X86 MicroprocessorFigure 13-12 shows an 80X86-based system that contains the 8237 DMA controller.

The address enable (AEN) output of the 8237 controls the output pins of the latches andthe outputs of the 74LS257 (E). During normal 80X86 operation (AEN = 0), latches A and C andthe multiplexer (E) provide address bus bits A19-A16 and A7-AO. The multiplexer provides thesystem control signals as long as the 80X86 is in control of the system. During a DMA action(AEN = 1), latches A and C are disabled along with the multiplexer (E). Latches D and B nowprovide address bits A19-A16 and A15-A8. Address bus bits A7-AO are provided directly bythe 8237 and contain a part of the DMA transfer address. The control signals MEMR, MEMW,IOR, and IOW are provided by the DMA controller.

The address strobe output (ADSTB) of the 8237 clocks the address (A15-A8) into latch Dduring the DMA action so that the entire DMA transfer address becomes available on the address

o FIGURE 13-12 Complete 8088 minimum mode DMA system.


TABLE 13-1 DMA pageregister ports.


Channel

01234567

Port number (A16-A23)

87H83H81H82H8FH8BH89H8AH

Port number (A24-A31)

487 H483H481 H482H48FH48BH489H48AH

bus. Address bus bits A19-A16 are provided by latch B, which must be programmed with these fouraddress bits before the controller is enabled for the DMA transfer. The DMA operation of the 8237is limited to a transfer of not more than 64K bytes within the same 64K-byte section of the memory.

The decoder (F) selects the 8237 for programming and the 4-bit latch (B) for the upper-most four address bits. The latch in a PC is called the DMA page register (8-bits) that holds ad-dress bits A16-A23 for a DMA transfer. A high page register also exists, but its address ischip-dependent. The port numbers for the DMA page registers are listed in Table 13-1 (these arefor the Intel ISP). The decoder in this system enables the 8237 for I/O port addressesXX60H-XX7FH, and the I/O latch (B) for ports XXOOH-XX1FH. Notice that the decoderoutput is combined with the IOW signal to generate an active-high clock for the latch (B).

During normal 80X86 operation, the DMA controller and integrated circuits B and D aredisabled. During a DMA action, integrated circuits A, C, and E are disabled so that the 8237 cantake control of the system through the address, data, and control buses.

In the personal computer, the two DMA controllers are programmed at I/O portsOOOOH-OOOFH for DMA channels 0-3, and at ports OOCOH-OODFH for DMA channels 4-7.Note that the second controller is programmed at even addresses only, so the channel 4 base andcurrent address is programmed at I/O port OOCOH and the channel 4 base and current count isprogrammed at port OOC2H. The page register, which holds address bits A23-A16 of the DMAaddress, are located at I/O ports 0087H (CH-0), 0083H (CH-1), 0081H (CH-2), 0082H (CH-3),(no channel 4), 008BH (CH-5), 0089H (CH-6) and 008AH (CH-7). The page register functionsas the address latch described with the examples in this text.

Memory-to-Memory Transfer with the 8237The memory-to-memory transfer is much more powerful than even the automatically repeatedMOVSB instruction. While the repeated MOVSB instruction tables the 8088 4.2 [as per byte, the8237 requires only 2.0 |is per byte, which is over twice as fast as a software data transfer. This isnot true if an 80386, 80846, or Pentium/Pentium Pro is in use in the system.

Sample Memory-to-Memory DMA Transfer, Suppose that the contents of memory locations 10000H-13FFFH are to be transferred into memory locations 14000H-17FFFH. This is accomplished witha repeated string move instruction, or, at a much faster rate, with the DMA controller.

Example 13-1 illustrates the software required to initialize the 8237 and program latch B inFigure 13-12 for this DMA transfer. This software is written for an embedded application. For it tofunction in the PC, you must use the port addresses listed in Table 13-1 for the page registers.

EXAMPLE 13-1

;A procedure that transfers a block of data using the;8237A DMA controller in Figure 13-12. This is a;memory-to-memory block transfer.

;Calling parameters:SI = source address

; DI = destination addressCX - countES - segment of source and destination

= 0010= 007C= 0070= 0072= 0073= 007B= 0078= 007F= 0079= 0078

0000

0001 8C CO0003 8A C40005 CO E80008 E6 10OOOA E6 7C

OOOCOOOE0011001300150017

0019001B001E002000220024

8C COCl EO03 C6E6 708A C4E6 70

8C COCl EO03 C7E6 728A C4E6 72

0026 8B Cl0028 480029 E6 73002B 8A C4002D E6 73

002F BO 880031 E6 7B0033 BO 850035 E6 7B

00370039

BO 01E6 78

003B BO OE003D E6 7F

003F0041

BO 04E6 79

0043 E4 78

LATCHBCLEAR_FCHO_ACH1_ACH1_CMODECMMDMASKSREQSTATUS

TRANS

EQUEQUEQUEQUEQUEQUEQUEQUEQUEQU

PROC

MOVMOVSHROUTOUT

MOVSHLADDOUTMOVOUT

MOVSHLADDOUTMOVOUT

MOVDEC-OUTMOVOUT

MOVOUTMOVOUT

MOVOUT

MOVOUT

MOVOUT

10H7CH7 OH72H73H7BH78H7FH79H78H

; latch B;F/L flip flop; channel 0 address; channel 1 address; channel 1 count; mode; command; masks; request register; status register

FAR USES AX

AX,ESAL,AHAL, 4LATCHB , ALCLEAR_F , AL

AX,ESAX, 4AX, SICHO_A,ALAL,AHCHO_A, AL

AX,ESAX, 4AX,DICH1_A,ALAL,AHCH1_A,AL

AX,CXAXCH1_C,ALAL,AHCH1_C , AL

AL, 88HMODE , ALAL, 85HMODE , AL

AL,1CMMD, AL

AL,OEHMASKS , AL

AL,4REQ , AL

. REPEATIN.UNTIL

AL, STATUSAL &1

; program latch B

;clear F/L flip-flop

; program source address

; form source offset

; program destination address

; f orm destination offset

; program count; ad just count

; program mode

; enable block transfer

; unmask channel 0

; start DMA transfer

;wait until DMA complete

RET

ENDP

Programming the DMA controller requires a few steps, as illustrated in Example 13-1.The leftmost digit of the 5-digit address is sent to latch B. Next, the channels are programmed


after the F/L flip-flop is cleared. Note that we use channel 0 as the source and channel 1 as thedestination for a memory-to-memory transfer. The count is next programmed with a value that isone less than the number of bytes to be transferred. Next, the mode register of each channel isprogrammed, the command register selects a block move, channel 0 is enabled, and a softwareDMA request is initiated. Before return is made from the procedure, the status register is testedfor a terminal count. Recall that the terminal count flag indicates that the DMA transfer is com-pleted. The TC also disables the channel, preventing additional transfers.

Sample Memory Fill Using the 8237. In order to fill an area of memory with the same data, thechannel 0 source register is programmed to point to the same address throughout the transfer.This is accomplished with the channel 0 hold mode. The controller copies the contents of thissingle memory location to an entire block of memory addressed by channel 1. This has manyuseful applications.

For example, suppose that a video display must be cleared. This operation can be per-formed using the DMA controller with the channel 0 hold mode and a memory-to-memorytransfer. If the video display contains 80 columns and 25 lines, it has 2000 display positions thatmust be set to 20H (an ASCII space) to clear the screen.

Example 13-2 shows a procedure that clears an area of memory addressed by ES:DI. TheCX register transfers the number of bytes to be cleared to the CLEAR procedure. Notice that thisprocedure is nearly identical to Example 13-1, except that the command register is programmedso the channel 0 address is held. The source address is programmed as the same address asES:DI, and then the destination is programmed as one location beyond ES:DI. Also note that thisprogram is designed to function with the hardware in Figure 13-12 and will not function in thepersonal computer unless you have the same hardware.


EXAMPLE 13-2

A procedure that clears an area of memory using the8237A DMA controller in Figure 13-12. This is amemory-to-memory block transfer with a channel 0 hold.

Calling parameters:DI = offset address of area clearedES = segment address of area clearedCX = number of bytes cleared

0000

0001 8C CO0003 8A C40005 CO E8 040008 E6 10

OOOA E6 7C

OOOC 2E: AO 00000010 26: 88.05

LATCHBCLEAR_FCHO_ACH1_ACH1_CMODECMMDMASKSREQSTATUSZERO

CLEAR

EQUEQUEQUEQUEQUEQUEQUEQUEQUEQUEQU

PROC

MOVMOVSHROUT

OUT

MOVMOV

10H7CH70H72H73H7BH78H7FH79H78HOH

latch BF/L flip flopchannel 0 addresschannel 1 addresschannel 1 countmodecommandmasksrequest registerstatus registerzero

FAR USES AX

AX,ES ; program latch BAL,AHAL,4LATCHB , AL

CLEAR_F,AL ; clear F/L flip-flop

AL,CS:ZEROES:[DI],AL ; save zero in first

001300150018001A001C001E

00200022002500270028002A002C

8C COCl EO 0403 C7E6 708A C4E6 70

8C COCl EO 0403 C748E6 728A C4E6 72

002E0030 480031 4800320034

8B Cl

E6 738A C4

0036 E6 73

0038 BO 88003A E6 7B003C BO 85003E E6 7B

0040 BO 030042 E6 78

0044 BO OE0046 E6 7F

0048 BO 04004A E6 79

004C E4 78

MOVSHLADDOUTMOVOUT

MOVSHLADDINCOUTMOVOUT

MOVDECDECOUTMOVOUT

MOVOUTMOVOUT

MOVOUT

MOVOUT

MOVOUT

AX,ESAX, 4AX,DICHO_A,ALAL,AHCHO_A,AL

AX,ESAX, 4AX,DIAXCH1_A,ALAL,AHCH1_A,AL

AX,CXAXAXCH1_C , ALAL,AHCH1_C , AL

AL,88HMODE , ALAL, 85HMODE , AL

AL,3CMMD,AL

AL,OEHMASKS , AL

AL,4REQ , AL

.REPEATIN.UNTILRET

AL , STATUSAL &1

; program source address

; form source offset

/program destination address

; f orm destination offset

; program count; ad just count

; program mode

,- enable block hold transfer

; unmask channel 0

; start DMA transfer

;wait until DMA complete

DMA-Processed Printer InterfaceFigure 13-13 illustrates the hardware added to Figure 13-12 for a DMA-controlled printer inter-face. Little additional circuitry is added for this interface to a Centronics-type parallel printer. Thelatch is used to capture the data as it is sent to the printer during the DMA transfer. The write pulsepassed through to the latch during the DMA action also generates the data strobe (DS) signal to theprinter through the single-shot. The ACK signal returns from the printer each time it is ready for ad-ditional data. In this circuit, ACK is used to request a DMA action through a flip-flop.

Notice that the I/O device is not selected by decoding the address on the address bus.During the DMA transfer, the address bus contains the memory address and cannot contain theI/O port address. In place of the I/O port address, the DACK3 output from the 8237 selects thelatch by gating the write pulse through an OR gate.

Software that controls this interface is simple because only the address of the data and thenumber of characters to be printed are programmed. Once programmed, the channel is enabled,and the DMA action transfers a byte at a time to the printer interface each time that the interfacereceives the ACK single from the printer.

The procedure that prints data from the current data segment is illustrated in Exam-ple 13-3. This procedure programs the 8237, but doesn't actually print anything. Printing is ac-complished by the DMA controller and the printer interface.


FIGURE 13-13 DMA-processed printer interface.

ACK

EXAMPLE 13-3A procedure that prints data via the printer interfacein Figure 13-13.

Calling parameters:BX = offset address of printer dataDS = segment address of printer dataCX = number of bytes to print

= 0010= 007C= 0076= 0077= 007B= 0078= 007F= 0079

0000

0003 66| B80009 8C D8OOOB 66 | ClOOOF 500010 66| Cl0014 E6 10

LATCHBCLEAR_FCH3_ACH3_CMODECMMDMASKSREQ

PRINT

00000000

E8 04

E8 10

EQUEQUEQUEQUEQUEQUEQUEQU

PROC

MOVMOVSHRPUSHSHROUT

10H7CH76H77H7BH78H7FH79H

FAR USES AX

EAX, 0AX,DSEAX, 4AXEAX , 1 6LATCHB , AL

latch BF/L flifchannelchannelmodecommandmasksrequest

CX BX

program

> flop0 address1 count

register

latch B

0016 58 ;program address

13-3 SHARED-BUS OPERATION 513

00170019001B

001D001F002000220024

00260028

002A002C

002E0030RET

E68AE6

8B48E68AE6

BOE6

BOE6

BOE6

76C476

Cl

77C477

OB7B

0078

077F

OUTMOVOUT

MOVDECOUTMOVOUT

MOVOUT

MOVOUT

MOVOUT

CH3_A, ALAL,AHCH3_A,AL

AX,CX ; program countAX ; adjust countCH3_C,ALAL,AHCH3_C,AL

AL,OBH ; program modeMODE , AL

AL, 0 ; enable block hold transferCMMD , AL

AL,7 ;unmask channel 3MASKS , AL

A secondary procedure is needed to determine whether the DMA action has been com-pleted. Example 13-4 lists the secondary procedure that tests the DMA controller to see whetherthe DMA transfer is complete. The TEST_P procedure is called before programming the DMAcontroller to see whether the prior transfer is complete.

EXAMPLE 13-4

0001 E4 78

0009

;A procedure that tests for a complete DMA action

STATUS EQU 78H ;status register

TEST_P PROC NEAR USES AX

.REPEATIN AL,STATUS

.UNTIL AL &8

RET

TEST_P ENDP

Printed data can be double-buffered by first loading buffer 1 with data to be printed. Next,the PRINT procedure is called to begin printing buffer 1. Because it takes very little time to pro-gram the DMA controller, a second buffer (buffer 2) can be filled with new printer data while thefirst buffer (buffer 1) is printed by the printer interface and DMA controller. This process is re-peated until all data are printed.

13-3 SHARED-BUS OPERATION

Complex present-day computer systems have so many tasks to perform that some systems areusing more than one microprocessor to accomplish the work. This is called a multiprocessingsystem. We also sometimes call this a distributed system. A system that performs more than onetask is called a multitasking system. In systems that contain more than one microprocessor,some method of control must be developed and employed. In a distributed, multiprocessing,multitasking environment, each microprocessor accesses two buses: (1) the local bus and (2) theremote or shared bus.

514 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-3 SHARED-BUS OPERATION 515

FIGURE 13-14 A block diagram illustrating the shared and local buses.

This section of the text describes shared bus operation for the 8086 and 8088 microproces-sors using the 8289 bus arbiter. The 80286 uses the 82289 bus arbiter and the 80386/80486 usesthe 82389 bus arbiter. The Pentium-Pentium II directly support a multiuser environment, as de-scribed in Chapters 16, 17, and 18. These systems are much more complex and difficult to illus-trate at this point in the text, but their terminology and operation is essentially the same as for the

The local bus is connected to memory and I/O devices that are directly accessed by a singlemicroprocessor without any special protocol or access rules. The remote (shared) bus containsmemory and I/O that are accessed by any microprocessor in the system. Figure 13-14 illustratesthis idea with a few microprocessors. Note that the personal computer is also configured in thesame manner as the system in Figure 13-14. The bus master is the main microprocessor in thepersonal computer. What we call the local bus in the personal computer is the shared bus in thisillustration. The ISA bus is operated as a slave to the personal computer's microprocessor as wellas any other devices attached to the shared bus.

Types of Buses DefinedThe local bus is the bus that is resident to the microprocessor. The local bus contains the residentor local memory and I/O. All microprocessors studied thus far in this text are considered to belocal bus systems. The local memory and local I/O are accessed by the microprocessor that is di-rectly connected to them.

A shared bus is one that is connected to all microprocessors in the system. The shared busis used to exchange data between microprocessors in the system. A shared bus may containmemory and I/O devices that are accessed by all microprocessors in the system. Access to theshared bus is controlled by some form or arbiter that allows only a single microprocessor to access

the system's shared bus space. As mentioned, the shared bus in the personal computer is what weoften call the local bus in the personal computer because it is local to the microprocessor in thepersonal computer.

Figure 13-15 shows an 8088 microprocessor that is connected as a remote bus master. The termbus master applies to any device (microprocessor or otherwise) that can control a bus containing

READY(Local)

READY(Shared)

\ ADDRESS/DATA A NT-

FIGURE 13-15 The 8088 operated in the remote mode, illustrating the local and shared busconnections.


memory and I/O. The 8237 DMA controller presented earlier in the chapter is an example of aremote bus master. The DMA controller gained access to the system memory and I/O space tocause a data transfer. Likewise, a remote bus master gains access to the shared bus for the samepurpose. The difference is that the remote bus master microprocessor can execute variable soft-ware, whereas the DMA controller can only transfer data.

Access to the shared bus is accomplished by using the HOLD pin on the microprocessorfor the DMA controller. Access to the shared bus for the remote bus master is accomplished viaa bus arbiter, which functions to resolve priority between bus masters and allows only one de-vice at a time to access the shared bus.

Notice in Figure 13-15 that the 8088 microprocessor has an interface to both a local, resi-dent bus and the shared bus. This configuration allows the 8088 to access local memory and I/Oor, through the bus arbiter and buffers, the shared bus. The task assigned to the microprocessormight be data communications. It may, after collecting a block of data from the communicationsinterface, pass those data on to the shared bus and shared memory so that other microprocessorsattached to the system can access the data. This allows many microprocessors to share commondata. In the same manner, multiple microprocessors can be assigned various tasks in the system,drastically improving throughput.

The Bus ArbiterBefore Figure 13-15 can be fully understood, the operation of the bus arbiter must be grasped.The 8289 bus arbiter controls the interface of a bus master to a shared bus. Although the 8289 isnot the only bus arbiter, it is designed to function with the 8086/8088 microprocessors, so it ispresented here. Each bus master or microprocessor requires an arbiter for the interface to theshared bus, which Intel calls the Multibus and IBM calls the Micro Channel.

The shared bus is used only to pass information from one microprocessor to another; oth-erwise, the bus masters function in their own local bus modes by using their own local programs,memory, and I/O space. Microprocessors connected in this kind of system are often called par-allel or distributed processors because they can execute software and perform tasks in parallel.

8289 Architecture. Figure 13-16 illustrates the pin-out and block diagram of the 8289 bus ar-biter. The left side of the block diagram depicts the connections to the microprocessor. The rightside denotes the 8289 connection to the shared (remote) bus or Multibus.

The 8289 controls the shared bus by causing the READY input to the microprocessor tobecome a logic 0 (not ready) if access to the shared bus is denied. The blocking occurs wheneveranother microprocessor is accessing the shared bus. As a result, the microprocessor requestingaccess is blocked by the logic 0 applied to its READY input. When the READY pin is a logic 0,the microprocessor and its software wait until access to the shared bus is granted by the arbiter.In this manner, one microprocessor at a time gains access to the shared bus. No special instruc-tions are required for bus arbitration with the 8289 bus arbiter because arbitration is accom-plished strictly by the hardware.

Pin Definitions

AEN

ANYRQST

BCLKBPRN

The address enable output causes the bus drivers in a system to switch totheir three-state, high-impedance state.The any request input is a strapping option that prevents a lower-prioritymicroprocessor from gaining to the shared bus. If tied to a logic 0, normalarbitration occurs and a lower priority microprocessor can gain access tothe shared bus if CBRQ is also a logic 0.The bus clock input synchronizes all shared-bus masters.The bus priority input allows the 8289 to acquire the shared bus on thenext falling edge of the BLCK signal.


FIGURE 13-16 The8289 pin-out and blockdiagram. (Courtesy of IntelCorporation.)

S2CIOB[

SYSB/RESB CRESBCBCLKC

iNffcBREQ.CBPROCBPRNCGNDC

1 20

2 9

3 8

4 8289 7

5 BUS 6ARBITEF

6 ' 5

7 4

8 3

9 2

10 1

UVCC

3 si3 so3 CLK3 CocR] CRQLCK3 ANYRQST3 AEN3 CBRQ3 BUSY

LOCK-CLK-

CRQLCK-RESB-

ANYRQST -JOB-

ARBITRATION

&•>•^ STATE*" GENERATOR*•

>•!»•

CONTROL

&•!»•

/-v--K~y

— *•

•*-•4-

MULTIBUS ^_INTERFACE

-<-

_f ^

LOCALBUS

INTERFACE

| GND+5V (b)

- INIT-BcTR»- BREQ-BPRN»BPRO-BUSY»• CBRQ

MULTIBUS™- COMMAND

SIGNALS

BPRO The bus priority output is a signal that is used to resolve priority in asystem that contains multiple bus masters.

BREQ The bus request output is used to request access to the shared bus.BUSY The busy input/output indicates, as an output, that an 8289 has acquired

the shared bus. As an input, BUSY is used to detect that another 8289 hasacquired the shared bus.

CBRQ The common bus request input/output is used when a lower-prioritymicroprocessor is asking for the use of the shared bus. As an output,CBRQ becomes a logic 0 whenever the 8289 requests the shared bus andremains low until the 8289 obtains access to the shared bus.The clock input is generated by the 8284A clock generator and providesthe internal timing source to the 8289.The common request lock input prevents the 8289 from surrendering theshared bus to any of the 8289s in the system. This signal functions inconjunction with the CBRQ pin.

INIT The initialization input resets the 8289 and is normally connected to thesystem RESET signal.

IOB The I/O bus input selects whether the 8289 operates in a shared-bussystem (if selected by RESB) with I/O (IOB = 0) or with memory and I/O(IOB = 1).

LOCK The lock input prevents the 8289 from allowing any other microprocessorfrom gaining access to the shared bus. An 8086/8088 instruction thatcontains a LOCK prefix will prevent other microprocessors from accessingthe shared bus.

518 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-3 SHARED-BUS OPERATION 519

RESB The resident-bus input is a strapping connection that allows the 8289 tooperate in systems that have either a shared-bus or resident-bus system. IfRESB is a logic 1, the 8289 is configured as a shared-bus master. If RESB isa logic 0, the 8289 is configured as a local-bus master. When configured as ashared-bus master, access is requested through the SYSB/RESB input pin.

S2, SI, and SO The status inputs initiate shared-bus requests and surrenders. These pinsconnect to the 8288 system bus controller status pins.

SYSB/RESB The system bus/resident bus input selects the shared-bus system whenplaced at a logic 1 or the resident local bus when placed at a logic 0.

General 8289 Operation. As the pin descriptions demonstrate, the 8289 can be operated in threebasic modes: (1) I/O peripheral bus mode, (2) resident bus mode, and (3) single-bus mode. SeeTable 13-2 for the connections required to operate the 8289 in these modes. In the I/O peripheralbus mode, all devices on the local bus are treated as I/O, including memory, and are accessed by I/Iinstructions. All memory references access the shared bus and all I/O access the resident local bus.The resident bus mode allows memory and I/O accesses on both the local and shared buses. Fi-nally, the single-bus mode interfaces a microprocessor to a shared-bus, but the microprocessor hasno local memory or local I/O. In many systems, one microprocessor is set up as the shared-busmaster (single-bus mode) to control the shared-bus and become the shared-bus master. The shared-bus master controls the system through shared memory and I/O. Additional microprocessors areconnected to the shared bus as resident or I/O peripheral bus masters. These additional bus mastersusually perform independent tasks that are reported to the shared-bus master through the shared bus.

System Illustrating Single-bus and Resident-bus Connections. Single-bus operation interfaces amicroprocessor to a shared bus that contains both I/O and memory resources that are shared byother microprocessors. Figure 13-17 illustrates three 8088 microprocessors, each connected to ashared bus. Two of the three microprocessors operate in the resident-bus mode, while the thirdoperates in the single-bus mode. Microprocessor A, in Figure 13-17, operates in the single-busmode and has no local bus. This microprocessor accesses only the shared memory and I/O space.Microprocessor A is often referred to as the system bus master because it is responsible for co-ordinating the main memory and I/O tasks. The remaining two microprocessors (B and C) areconnected in the resident-bus mode, which allows them access to both the shared bus and theirown local buses. These resident-bus microprocessors are used to perform tasks that are indepen-dent from the system bus master. In fact, the only time that the system bus master is interruptedfrom performing its tasks are when one of the two resident-bus microprocessors needs to transferdata between itself and the shared bus. This connection allows all three microprocessors to per-form tasks simultaneously, yet data can be shared between microprocessors when needed.

In Figure 13-17, the bus master (A) allows the user to operate with a video terminal thatallows the execution of programs and generally controls the system. Microprocessor B handlesall telephone communications and passes this information to the shared memory in blocks. Thismeans that microprocessor B waits for each character to be transmitted or received and controlsthe protocol used for the transfers. For example, suppose that a IK byte-block of data are trans-mitted across the telephone interface and this occurs at the rate of 100 characters per second.

TABLE 13-2 8289 modesof operation. Mode Pin Connections

Single busResident busI/O busI/O bus and resident bus

IOB = 1 and RESB = 0JOB = 1 and RESB = 1JOB = 0 and RESB = 0IOB = 0 and RESB = 1

This means that the transfer requires 10 seconds. Rather than tie up the bus master for 10 sec-onds, microprocessor B patiently performs the data transfer from its own local memory and thelocal communications interface. This frees the bus master for other tasks. The only time the mi-croprocessor B interrupts the bus master is to transfer data between the shared memory and itslocal memory system. This data transfer, betweem microporcessor B and the bus master, re-quires only a few hundred microseconds.

Microprocessor C is used as a print spooler. Its only task is to print data on the printer.Whenever the bus master requires printed output, it transfers the task to microprocessor C. Mi-croprocessor C then accesses the shared memory and captures the data to be printed and stores itin its own local memory. Data are then printed from the local memory, freeing the bus master toperform other tasks. This allows the system to execute a program with the bus master, transferdata through the communications interface with microprocessor B, and print information on theprinter with microprocessor C. These tasks all execute simultaneously. There is no limit to thenumber of microprocessors connected to a system or the number of tasks performed simultane-ously using this technique. The only limit is that introduced by the system design and the de-signer's ingenuity.

Priority Logic Using the 8289In applications that use the 8289, there is always more than one microprocessor connected 10 ashared bus. Because only one can access the shared bus at a time, some method of resolving pri-ority must be employed. Priority prevents more than one microprocessor from accessing the busat a time. There are two methods for resolving priority with the 8289 bus arbiter: the daisy-chain(serial) scheme and the parallel-priority scheme.

Daisy-Chain Priority. The daisy-chain priority scheme connects the BPRO output to the BPRNinput of the next-lower priority 8289 and is the least expensive to implement. Figure 13-18 il-lustrates the daisy-chain scheme for connecting several 8289s in a system. Because the BPRNinput of the higher priority 8289 is grounded, it gets an immediate acknowledgment whenever itsmicroprocessor requests access to the shared bus. The BPRO output is a logic 0 if the 8289 andits microprocessor are inactive, and a logic 1 if the 8289 and its microprocessor are activelyusing the shared bus. If no requests are active, all BPRN inputs will see a logic 0. As soon as thehighest-priority 8289s receives a bus acknowledgment, its BPRO output goes high, blocking alllower-priority 8289s from accessing the shared bus. If more than one 8289 receives an acknowl-edgment, more than one 8289 will function at the same time. This scheme is seldom used be-cause two microprocessors can access the shared bus at a time. For this reason, Intelrecommends that this scheme be limited to no more than three 8289s in a system that uses a busclock of 10 MHz or less. With this frequency bus clock, no conflict occurs and only one micro-processor accesses the shared bus at a time. If more arbiters are connected, Intel suggests that thepriority be resolved using the parallel scheme.

Parallel PriorityFigure 13-19 illustrates a parallel-priority scheme in which four 8289 bus arbiters are connectedwith a parallel circuit. Here, a 74LS148, eight-input priority encoder is used to resolve priorityconflicts in parallel. In this example, only four of the inputs are used to resolve priority for thefour 8289s. The four unused encoder inputs are pulled up to a logic 1 to disable these unneededinputs to the encoder. Note that this circuit can be expanded to provide priority for up to eight8289s with their microprocessors.

The circuit in Figure 13-19 functions as follows. If all 8289 arbiters are idle (no requestsfor the shared bus through the SYSB/RESB input), all BREQ outputs are high and the outputs ofthe 74LS148 are logic Is (A and B are both 1). This means that the highest-priority 8289 willgain access to the shared bus if it is requested by its microprocessor. On the other hand, if a lowerpriority request is made, the BREQ output becomes a logic 0. This causes the priority encoder to


FIGURE 13-17 Three 8088 microprocessors that share a common bus system. Microprocessor A is the busmaster in control of the shared memory and CRT terminal. Microprocessor B is a bus slave controlling its localtelephone interface and memory. Microprocessor C is also a slave that controls a printer, disk memory system,and local memory.

place a logic 0 on the corresponding BPRN input pin of the 8289, allowing access to the sharedbus. For example, if the rightmost 8289 places a logic 0 on its BREQ output pin, the priority en-coder will have a zero on input 3. This causes the 74LS148 to generate a 00 on its output pins.The 00 causes the 74LS138 to activate the BPRN input of the rightmost 8289, giving it access tothe shared bus. This also locks out any other requests because the BUSY signal becomes a logic0. If simultaneous requests occur, they are automatically prioritized by the 74LS148, preventingconflicts no matter how many 8289s are connected in a system. For this reason, this priorityscheme is desirable.

Print Spooler and InterfaceFigure 13-20 shows the block diagram of a printer interface and spooler (print queue), which iscontrolled by an 8088 microprocessor. Here, two microprocessors are placed in a system withone (the system bus master) operated in single-bus mode and a second operated in the resident-


Fl G U R E 13-17 (continued)

FIGURE 13-18 Daisy-chain8289 priority resolver.

, , ,„,0 O

BUSY CBRQ

8289

BPRN BPRO

A ABUSY CBRQ

8289

BPRN BPRO

A ABUSY CBRQ

8289

BPRN BPRO

— CBRQ

-BPRO

bus mode. Because two microprocessors exist, one can print data while the other is used toprocess new information in the interim.

In this interface, the slave microprocessor transfers data to the printer from its local memorywithout intervention from the system bus master. Data are transferred to the local memory of theslave microprocessor whenever it accesses the shared memory for additional data.

Single-mode Bus-master Interface. Figure 13-21 illustrates the 8088 bus master, operated insingle mode, interfaced to the shared bus. The shared bus master has access to every memory lo-cation and I/O device on the shared bus. The BCLK signal is generated by an 8284A clock gen-erator used as a 10-MHz oscillator.

The 8289 arbiter is operated with no I/O bus, no resident bus, and ANYRQST pulled highso that the shared bus can be accessed for all memory and I/O transfers. This system uses thedaisy-chain priority scheme, which means that the BREQ signal is not connected. This interfaceallows the slave microprocessor to access shared memory whenever necessary and thus preventsthe slave microprocessor from locking the bus for too long.


FIGURE 13-19 Parallel-priority resolver for the 8289.

^

3

2

0

4 e5

6

7

'148Prioritysncode

E-4 —

A

C

r

rr

A

C1.4 O

Ei

E2

Eg

3

2

1

R 0

4

5

6

7

0

o

0

MK

FIGURE 13-20 Block dia-gram of two 8088s used tocontrol a printer interface andprint spooler.

8088HP

AAVV

Sharedbus

interface

Systemmemory

SystemI/O

ANVv

AAvV

VV

hared

bus

JINTR

Localmemory

Printerinterface

In addition to the normal bus signals, this circuit also provides the shared bus with a 2.5MHz PCLK signal for any I/O device. The RDY input is shown, in case system memory and I/Orequire wait states.


FIGURE 13-21 An 8088 connected for the single-bus mode of operation.

Resident-bUS Operation Of the Slave 8088. Figure 13-22 illustrates the slave 8088 microprocessorthat functions as a print spooler. This microprocessor is connected as a resident-bus master. This il-lustration depicts the resident-local-bus interface as well as the shared-bus interface.

Whenever the slave 8088 microprocessor accesses memory above location 7FFFFH, itplaces a logic 1 on the SYS/RESB input to the 8289 and the CEN pin of the shared-bus master's8288. This requests access to the shared bus through the 8289 bus arbiter. If the address is below


ILUCC



FIGURE 13-23 Memorymaps for the print spooler.(a) Shared-bus master, and(b) bus-slave memory map.

FFFFFMemory map Memory map

Sharedbus

800007FFFF

Sharedbus

Residentlocalbus

(b)

80000H, the SYS/RESB pin on the 8289 is grounded and a logic 1 is placed on the CEN pin ofthe local bus 8288. This requests access to the resident-local bus for control of the printer andresident-local bus memory. Notice that no attempt is made to access the shared-bus I/O becausethe purpose of the slave 8088 is to access the printer interface on its local bus as local I/O.

Figure 13-23 shows the memory maps of both the slave 8088 local memory and the sharedmemory and the local memory of the 8088 bus master. The bus master has access to all of theshared memory, while the slave can only access locations 80000H-FFFFFH. Transfers to theprint spooler are made through the upper half of the shared memory.

The resident-local bus in this system contains EPROM, DRAM, and a printer interface.The EPROM contains the program that controls the slave 8088, the DRAM contains the data forthe printer, and the printer interface controls the printer. Figure 13-24 illustrates these three de-vices on the resident-local bus of the slave 8088 microprocessor.

The decoder in this illustration selects EPROM for locations OOOOOH-OFFFFH, the printerfor locations 10000H-1FFFFH, and the DRAM for locations 20000H-7FFFFH. This allows thespooler to hold up to 384K bytes of data (see Figure 13-25). If the printer can produce 1,000lines per minute (high-speed printer), then this represents about three minutes of printing andabout 50—75 printed pages of data. If the system is expanded with a fixed memory system, thecapacity of the spooler can become almost boundless because of the huge capacity of a modernfixed-disk memory system. For simplicity's sake, this is not added to this example.

The printer is interfaced to the slave microprocessor through a 74LS244 that is operated asa strobed-output interrupting device. Whenever the printer completes printing a character, as sig-naled by the ACK signal, an interrupt is generated, causing the slave microprocessor to retrievedata from the print queue for the printer. This process continues until the queue is empty, whenthe slave microprocessor disables interrupt requests until new information is placed in the queuefor printing.

Print Spooler Software, The software for the print spooler is fairly straightforward. The entiresoftware listing is provided in sections so that a study can be made of initialization, data transfer,and interrupt-controlled printer service procedures. The only software not illustrated is thatwhich are required to program and initialize the system. When the system is initialized, the inputand output pointers of the queue are both set up with address 20000H. This condition (equalpointers) indicates that the queue is empty. The segment portion of the pointers contains 2000Hand the offset portion contains OOOOH.

Example 13-5 lists the software that transfers data into the print spooler from the sharedbus. In this software, the bus master loads a block of shared memory with printer data, called aprint buffer (BUFFER beginning at location 80002H). Then it signals the slave 8088 that data


FIGURE 13-24 Residentlocal bus for the print spooler.

BUSY flip-flop

-

A16 ——— cA17 ———— C

"18

A19——— c

1+5V

ACK —— ——

r-D°7 A

1 Do N

3ET

f£

ABC

'1

E2

E3

K

»

>

01

»J56

ICLR

PI k'

Q D

Q

-c SET

~c CLEAR

3 —— |

1

Vn1 r1

PIIORC

= f l

l\/

^0

A4

——

r

1

">

•\

-/

-c

— K— /1 1 1 1 1 1 1 1 1 1 1 1 1 (

" N*s

\

Al5

)

A0\DO

RDWRSELT

SEL3SEL4SEL5SEL6

I EPROM

DO 2K x 8

: OE CE

I

74LS244Buffer

I? 07

\ \ID 00

OE OE

4

DRAMARRAY

Of

DRAMs

————— *- DS

\ Printer——— ,/ data

FIGURE 13-25 8088 resi-dent local bus memory map.

Memory map

20000

10000

00000

Printer

- 384K Bytes

64K Bytes


are available through a flip-flop, which acts as an indicator to the slave. This flag flip-flop is setby the master whenever printer data are available and cleared by the slave after the slave has re-moved the data from the shared memory. One additional piece of information is also placed inthe shared memory for the slave — the length of the block of data. Location 80000H holds aword that indicates the length of the printed block of data. The maximum size of the buffer is64K bytes.

EXAMPLE 13-5theA procedure found in the master

FLAG to determine if the slavesystem unais busy. If

i_ ueaua unethe slave

is not busy, data are transferred to the print bufferand the FLAG is set to indicatefor printing.

Calling parameters:

DS:SI = address of printer

that data

data

are available

CX = number of bytes to print

0000 LOAD PROC FAR USES ES

. REPEAT0001 E4 00 IN AL,0

.UNTIL AL==0

0007 BF 0002 MOV DI , 2OOOA B8 8000 MOV AX,8000HOOOD 8E CO MOV ES,AXOOOF 26: 89 OE 0000 MOV ES:[0],CX0014 F3/ A4 REP MOVSB0016 BO FF MOV AL,OFFH0018 E6 00 OUT 0,AL

RET

;test FLAG

; off set of; segment of

; save count; save data

; set FLAG

bufferbuffer & count

to buffer

001C LOAD ENDP

Once the slave notices a logic 1 in the flag flip-flop, it begins transferring data from theshared memory into its own local memory. The data are stored in the local memory organized asa FIFO (first in, first out), or queue. In this example, the size of the queue is 384K bytes. Ex-ample 13-6 lists the software used by the slave to load the queue from the shared memory buffer.In this software, the slave tests the flag flip-flop to see whether the master has filled the buffer inthe shared memory. If the buffer is filled, the slave microprocessor transfers its contents form theshared memory into its queue. Once the transfer is complete, the slave clears the flag flip-flop sothat the master may begin filling the buffer with additional printer data.

EXAMPLE 13-6

0000

;A procedure found in the slave system that tests the;FLAG to determine if data are available for printing.;If data are available, data are transferred into the;queue for the printer.

TRANS PROC FAR

0000 E4 000002 A8 01

0008 B8 8000OOOB 8E D8OOOD 8B OE 00000011 BE 0002 •

. REPEATIN AL , 0TEST AL,1

.UNTIL AL = = 0

MOV AX,8000HMOV DS , AXMOV CX,DS: [0]MOV SI, 2

;test FLAG

;if not finished

; segment of buffer & count

;get count; address buffer

13-3 SHARED-BUS OPERATION

0014 E8 OOOD

529

0024

;fill queue

;clear FLAG

;input pointer

;output pointer

;Procedure that fills the printer queue.

FILL PROC NEAR

00170018001A

001C

001C001E00200022

FBE6 00EB E4

0000000000000000

TRANS

; Data

IN_PSIN_POOUT_PSOUT_PO

STIOUTJMP

0,ALTRANS

ENDP

used

DWDWDWDW

with FILL

•p•p•p•p

0024 FC CLD0025 2E: Al 001C R MOV AX,CS:IN_PS0029 8E CO MOV ES,AX002B 2E: 8B 3E 001E R MOV DI,CS:IN_PO

.REPEAT0030 E8 0014

0035 A40036 E8 00240039 8C CO003B 2E: A3 001C R003F 2E: 89 3E 001E R

0046 C30047

0047

CALL TESTF.UNTIL IZERO?MOVSBCALL INCPMOV AX,ESMOV CS:IN_PS,AXMOV CS:IN_PO,DI

.UNTILCXZRET

FILL ENDP

TESTF PROC

0047 E8 0011 CALL004C 8C D8 MOV004E 2E: 3B 06 0020 R CMP0053 75 05 JNE0055 2E: 3B 3E 0022 R CMP005A

005D

005D

005D 47

0062 8C CO0064 05 1000

006C B8 2000

006F 8E CO

0071 C3

0072

NEAR USES DI DS

INCPAX, DSAX,CS:OUT_PSTESTF1DI,CS:OUT_PO

;clear direction

;load input address

;test for full queue;while full;store byte;increment pointer

; save input pointer

; increment pointer

TESTF1:RET

TESTF ENDP

INCP PROC

INC DI.IF DI == 0

MOV AX,ESADD AX,1000H.IF AX == 8000HMOV AX,2000H.ENDIFMOV ES,AX

.ENDIFRET

ENDP

Example 13-7 lists the software that prints data from the queue. This software is interruptdriven, and therefore runs as a background program virtually hidden from the software listed in Ex-ample 13-6, except for the interrupt enable instruction. Whenever the printer interface, through aflip-flop, indicates that it is ready to accept additional data, an interrupt occurs calling this interruptservice procedure. The procedure extracts data from the queue and sends them to the printer.


EXAMPLE 13-7

0072 PRINT PROC FAR USES AX BP DS DI ES

007C 8B EC007E 8B 46 OC0081 80 E4 FD0084 89 46 OC

0089 B8 1000008C 8E CO008E 8A 050090 26: A2 00000094 E8 001E

CALL TESTE.IF ZERO?

MOVMOVANDMOV

.ELSEMOVMOVMOVMOVCALL

. ENDIFIRET

;if emptyBP,SP /interrupt offAX, [BP+12]AH, OFDH[BP+12] ,AX

AX, 1000HES,AXAL, [DI]ES:[0],AL ; print dataINCO

PRINT ENDP

009D TESTE PROC

009DOOA100 A3OOA800 ADOOAFOOB4OOB4

OOB5

OOB5

OOB5

OOBAODBC

OOC4

OOC7OOC9

OOCDOOD2

OOD3

2E: Al 0020 R8E D82E: 8B 3E 0022 R2E: 3B 06 001C R75 052E: 3B 3E 001E R

TESTE1:C3

TESTE

INCO

47

8C D805 1000

B8 2000

8E D82E: A3 0020 R

2E: 89 3E 0022 RC3

INCO

MOV AX , CS : OUT_PSMOV DS , AXMOV DI , CS : OUT_POCMP AX,CS:IN_PSJNE TESTE1CMP DI , CS : IN_PO

RET

ENDP

PROC NEAR

INC DI.IF DI == 0

MOV AX,DSADD AX,1000H.IF AX == 8000H

MOV AX,2000H. ENDIFMOV DS , AXMOV CS : OUT_PS , AX

. ENDIFMOV CS : OUT_PO , DIRET

ENDP

13-4 DISK MEMORY SYSTEMS

Disk memory is used to store long-term data. Many types of disk storage systems are availabletoday and they use magnetic media, except the optical disk memory that stores data on a plasticdisk. Optical disk memory is either a CD-ROM (compact disk/read only memory) that is read,but never written, or a WORM (write once/read mostly) that is read most of the time, but can bewritten once by a laser beam. Also becoming available is optical disk memory that can be readand written many times, but there is still a limitation on the number of write operations allowed.

13-4 DISK MEMORY SYSTEMS 531

The latest optical disk technology is called DVD (digital versatile disk). This section of thechapter provides an introduction to disk memory systems so that they may be used with com-puter systems. It also provides details of their operation.

Floppy Disk MemoryThe most common and the most basic form of disk memory is the floppy, or flexible disk. Thismagnetic recording media is available in three sizes: the 8" standard, 5l/4" mini-floppy, and the3l/2" micro-floppy. Today, the 8" standard version has all but disappeared, giving way to themini- and micro-floppy disks. The 8" disk is too large and difficult to handle and stockpile. Tosolve this problem, industry developed the 5V4" mini-floppy disk. Today, the micro-floppy diskhas just about replaced the mini-floppy in newer systems because of its reduced size, ease ofstorage, and durability. Even so, a few systems are still marketed with both the mini- and micro-floppy disk drives.

All disks have several things in common. They are all organized so that data are stored intracks. A track is a concentric ring of data that is stored on a surface of a disk. Figure 12-36 il-lustrates the surface of a 5lk" mini-floppy disk, showing a track that is divided into sectors. Asector is a common subdivision of a track that is designed to hold a reasonable amount of data.In many systems, a sector holds either 512 or 1024 bytes of data. The size of a sector can varyfrom 128 bytes to the length of one entire track.

Notice in Figure 13-26 that there is a hole through the disk that is labeled an index hole.The index hole is designed so that the electronic system that reads the disk can find the begin-ning of a track and its first sector (00). Tracks are numbered from track 00, the outermost track,in increasing value toward the center or innermost track. Sectors are often numbered from sector00 on the outermost track, to whatever value is required to reach the innermost track and its lastsector.

7776 51/4 " Mini-floppy Disk. Today, the 5V4" floppy is probably the most popular disk size usedwith older microcomputer systems. Figure 13-27 illustrates this mini-floppy disk. The floppy

FIGURE 13-26 The formatof a 51/4" floppy disk.

Sector

532 CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O 13-4 DISK MEMORY SYSTEMS 533

FIGURE 13-27 The 51/4"mini-floppy disk.

Write protect notch _

Drive hub-

- Indexhole

Head slot

disk is rotated at 300 RPM inside its semi-rigid plastic jacket. The head mechanism in a floppydisk drive makes physical contact with the surface of the disk, which eventually causes wear anddamage to the disk.

Today, most mini-floppy disks are double-sided. This means that data are written on boththe top and bottom surfaces of the disk. A set of tracks called a cylinder consists of one top andone bottom track. Cylinder 00, for example, consists of the outermost top and bottom tracks.

Floppy disk data are stored in the double-density format, which uses a recording techniquecalled MFM (modified frequency modulation) to store the information. Double-density, double-sided (DSDD) disks are normally organized with 40 tracks of data on each side of the disk. Adouble-density disk track is typically divided into nine sectors, with each sector containing 512bytes of information. This means that the total capacity of a double-density, double-sided disk is40 tracks per side x 2 sides x 9 sectors per track x 512 bytes per sector, or 368,640 (360K) bytesof information.

Earlier disk memory systems used single-density and FM (frequency modulation) to storeinformation in 40 tracks on one or two sides of the disk. Each of the eight or nine sectors on thesingle-density disk stored 256 bytes of data. This meant that a single-density disk stored 90Kbytes of data per side. A single-density, double-sided disk stored 180K bytes of data.

Also common today are high-density (HD) mini-floppy disks. A high-density mini-floppydisk contains 80 tracks of information per side, with eight sectors per track. Each sector contains1024 bytes of information. This gives the 5l/4" high-density, mini-floppy disk a total capacity of80 tracks per side x 2 sides x 15 sectors per track x 512 bytes per sector, or 1,228,800 (approxi-mately 1.2 M) bytes of information.

The magnetic recording technique used to store data on the surface of the disk is callednon-return to zero (NRZ) recording. With NRZ recording, magnetic flux placed on the surfaceof the disk never returns to zero. Figure 13-28 illustrates the information stored in a portion of atrack. It also shows how the magnetic field encodes the data. Note that arrows are used in this il-lustration to show the polarity of the magnetic field stored on the surface of the disk.

The main reason that this form of magnetic encoding was chosen is that it automaticallyerases old information when new information is recorded. If another technique were used, a

Data

Track

FIGURE 13-28 The non-return to zero (NRZ) recording technique

separate erase head would be required. The mechanical alignment of a separate erase head and aseparate read/write head is virtually impossible. The magnetic flux density of the NRZ signal isso intense that it completely saturates (magnetizes) the surface of the disk, erasing all prior data.It also ensures that information will not be affected by noise because the amplitude of the mag-netic field contains no information. The information is stored in the placement of the changes ofthe magnetic field.

Data are stored in the form of MFM (modified frequency modulation) in modern floppydisk systems. The MFM recording technique stores data in the form illustrated in Figure 13-29.Notice that each bit time is 2.0 jis wide on a double-density disk. This means that data arerecorded at the rate of 500,000 bits per second. Each 2.0 jus bit time is divided into two parts: onepart is designated to hold a clock pulse and the other holds a data pulse. If a clock pulse is present,it is 1 (is wide, as is a data pulse. Clock and data pulses are never present at the same time in onebit period. (Note that high-density disk drives halve these times so that a bit time is 1.0 }is and aclock or data pulse is 0.5 u,s wide. This also doubles the transfer rate to 1 million bits per second.)

If a data pulse is present, the bit time represents a logic 1. If no data or no clock is present,the bit time represents a logic 0. If a clock pulse is present with no data pulse, the bit time alsorepresents a logic 0. The rules followed when data are stored using MFM are as follows:

1. A data pulse is always stored for a logic 1.2. No data and no clock is stored for the first logic 0 in a string of logic Os.3. The second and subsequent logic Os in a row contain a clock pulse, but no data pulse.

The reason that a clock is inserted as the second and subsequent zero in a row is to main-tain synchronization as data are read from the disk. The electronics used to recapture the datafrom the disk drive use a phase-locked loop to generate a clock and a data window. The phase-locked loop needs a clock or data to maintain synchronized operation.

The 31/2" Micro-floppy disk. Another very popular disk size is the 3V2" micro-floppy disk. Re-cently, this size floppy disk has begun to sell very well and is the dominant floppy disk size. Themicro-floppy disk is a much improved version of the mini-floppy disk described earlier. Figure13-30 illustrates the 3lh" micro-floppy disk.

FIGURE 13-29 Modifiedfrequency modulation (MFM)used with disk memory.

C i D C : D C | D C | D

534

FIGURE 13-30 The 31/2"micro-floppy disk.

CHAPTER 13 DIRECT MEMORY ACCESS AND DMA-CONTROLLED I/O

Write protect .


i

o

„ Drive hub

. Head slot

\Head door

Disk designers noticed several shortcomings of the mini-floppy, which is a scaled downversion of the 8" standard floppy, soon after it was released. Probably one of the biggest prob-lems with the mini-floppy is that it is packaged in a semi-rigid plastic cover that bends easily.The micro-floppy is packaged in a rigid plastic jacket that will not bend easily. This provides amuch greater degree of protection to the disk inside the jacket.

Another problem with the mini-floppy is the head slot that continually exposes the surfaceof the disk to contaminants. This problem is also corrected on the micro-floppy because it is con-structed with a spring-loaded sliding head door. The head door remains closed until the disk isinserted into the drive. Once inside the drive, the drive mechanism slides open the door, ex-posing the surface of the disk to the read/write heads. This provides a great deal of protection tothe surface of the micro-floppy disk.

Yet another improvement is the sliding plastic write-protection mechanism on the micro-floppy disk. On the mini-floppy disk, a piece of tape was placed over a notch on the side of thejacket to prevent writing. This plastic tape easily became dislodged inside disk drives, causingproblems. On the micro-floppy, an integrated plastic slide has replaced the tape write-protectionmechanism. To write-protect (prevent writing) the micro-floppy disk, the plastic slide is movedto open the hole though the disk jacket. This allows light to strike a sensor that inhibits writing.

Still another improvement is the replacement of the index hole with a different drive mech-anism. The drive mechanism on the mini-floppy allows the disk drive to grab the disk at anypoint. This requires an index hole so that the electronics can find the beginning of a track. Theindex hole is another trouble spot because it collects dirt and dust. The micro-floppy has a drivemechanism that is keyed so that it only fits one way inside the disk drive. The index hole is nolonger required because of this keyed drive mechanism. Because of the sliding head mechanismand the fact that no index hole exists, the micro-floppy disk has no place to catch dust or dirt.

Two types of micro-floppy disks are widely available: the double-sided, double-density(DSDD) and the high-density (HD). The double-sided, double-density micro-floppy disk has 80tracks per side, with each track containing nine sectors. Each sector contains 512 bytes of infor-mation. This allows 80 tracks per side x 2 sides x 9 sectors x 512 bytes per sector, or 737,280(720K) bytes of data to be stored on a double-density, double-sided floppy disk.

The high-density, double-sided micro-floppy disk stores even more information. The high-density version has 80 tracks per side, but the number of sectors is doubled to 18 per track. Thisformat still uses 512 bytes per sector, as did the double-density format. The total number of bytes

on a high-density, double-sided micro-floppy disk is 80 tracks per side x 2 sides x 18 sectors pertrack x 512 bytes per sector, or 1,474,560 (1.44M) bytes of information.

Recently, a new size SVz" floppy disk has been introduced, the EHD (extended high den-sity) floppy disk. This new format stores 2.88M bytes of data on a single floppy disk. At thistime, this format is expensive and will take time to become common. Also available is the flop-tical disk, which stores data magnetically by using an optical tracking system. The floptical diskstores 21M bytes of data.

Hard Disk MemoryLarger disk memory is available in the form of the hard disk drive. The hard disk drive is oftencalled a fixed disk because it is not removable like the floppy disk. A hard disk is also often calleda rigid disk. The term Winchester drive is also used to describe a hard disk drive, but less com-monly today. Hard disk memory has a much larger capacity than the floppy disk memory. Harddisk memory is available in sizes exceeding 1G byte of data. Common, low-cost (less than $0.30per megabyte) sizes are presently 3.2G bytes to 12G bytes.

There are several differences between the floppy disk and the hard disk memory. The harddisk memory uses a flying head to store and read data from the surface of the disk. A flying head,which is very small and light, does not touch the surface of the disk. It flies above the surface ona film of air that is carried with the surface of the disk as it spins. The hard disk typically spins at3000 to 10,000 R.P.M, which is more than 10 times faster than the floppy disk. This higher rota-tional speed allows the head to fly (just as an airplane flies) just over the top of the surface of thedisk. This is an important feature because there is no wear on the hard disk's surface, as there iswith the floppy disk.

Problems can arise because of flying heads. One problem is a head crash. If the power isabruptly interrupted or the hard disk drive is jarred, the head can crash onto the disk surface,which can damage the disk surface or the head. To help prevent crashes, some drive manufac-turers have included a system that automatically parks the head when power is interrupted. Thistype of disk drive has auto-parking heads. When the heads are parked, they are moved to a safelanding zone (unused track) when the power is disconnected. Some drives are not auto-parking;they usually require a program that parks the heads on the innermost track before power is dis-connected. The innermost track is a safe landing area because it is the very last track filled by thedisk drive. Parking is the responsibility of the operator in this type of disk drive.

Another difference between a floppy disk drive and a hard disk drive is the number of headsand disk surfaces. A floppy disk drive has two heads, one for the upper surface and one for thelower surface. The hard disk drive may have up to eight disk surfaces (four platters), with up totwo heads per surface. Each time that a new cylinder is obtained by moving the head assembly, 16new tracks are available under the heads. See Figure 13-31, which illustrates a hard disk system.

Heads are moved from track to track by using either a stepper motor or a voice coil. Thestepper motor is slow and noisy, while the voice coil mechanism is quiet and quick. Moving thehead assembly requires one step per cylinder in a system that uses a stepper motor to position theheads. In a system that uses a voice coil, the heads can be moved many cylinders with onesweeping motion. This makes the disk drive faster when seeking new cylinders.

Another advantage of the voice coil system is that a servo mechanism can monitor the am-plitude of the signal as it comes from the read head and make slight adjustments in the positionof the heads. This is not possible with a stepper motor, which relies strictly on mechanics to po-sition the head. Stepper-motor-type head positioning mechanisms can often become misalignedwith use, while the voice coil mechanism corrects for any misalignment.

Hard disk drives often store information in sectors that are 512 bytes long. Data are ad-dressed in clusters of eight or more sectors, which contain 4096 bytes (or more) on most harddisk drives. Hard disk drives use either MEM or RLL to store information. MEM is describedwith floppy disk drives. Run-length limited (RLL) is described here.


FIGURE 13-31 A hard diskdrive that uses four heads per Disk plattersplatter.

Actuator arm

Head [J

Drive spindle -

n

Stepper motor

A typical older MFM hard disk drive uses 18 sectors per track so that 18 K bytes of data arestored per track. If a hard disk drive has a capacity of 40M bytes, it contains approximately 2280tracks. If the disk drive has two heads, this means that it contains 1140 cylinders; if it containsfour heads, then it has 570 cylinders. These specifications vary from disk drive to disk drive.

RLL Storage. Run-length limited (RLL) disk drives use a different method for encoding thedata than MFM. The term RLL means that the run of zeros (zeros in a row) is limited. A commonRLL encoding scheme in use today is RLL 2,7. This means that the run of zeros is always be-tween two and seven. Table 13-3 illustrates the coding used with standard RLL.

Data are first encoded by using Table 13-3 before being sent to the drive electronics forstorage on the disk surface. Because of this encoding technique, it is possible to achieve a 50 per-cent increase in data storage on a disk drive when compared to MFM. The main difference is thatthe RLL drive often contains 27 tracks instead of the 18 found on the MFM drive. (Some RLLdrives also use 35 sectors per track.)

In most cases, RLL encoding requires no change to the drive electronics or surface of thedisk. The only difference is a slight decrease in the pulse width using RLL, which may requireslightly finer oxide particles on the surface of the disk. Disk manufacturers test the surface of thedisk and grade the disk drive as either an MFM-certified or an RLL-certified drive. Other thangrading, there is no difference in the construction of the disk drive or the magnetic material thatcoats the surface of the disks.

Figure 13-32 shows a comparison of MFM data and RLL data. Notice that the amount oftime (space) required to store RLL data is reduced when compared to MFM. Here a 101001011is coded in both MFM and RLL so that these two standards can be compared. Notice that thewidth of the RLL signal has been reduced so that three pulses fit in the same space as a clock and

TABLE 13-3 Standard RLL2,7 coding. Input Data Stream RLL Output

000100100010110110011

000100010010010000100100100000100000001000


Data RLL101001011 =010001001001001000

MFM

RLL

010 001 001 001 001 000

FIGURE 13-32 A comparison of MFM with RLL using data 101001011.

a data pulse for MFM. A 40M-byte MFM disk can hold 60M bytes of RLL-encoded data. Be-sides holding more information, the RLL drive can be written and read at a higher rate.

All hard disk drives use either MFM or RLL encoding. There are a number of disk driveinterfaces in use today. The oldest is the ST-506 interface, which uses either MFM or RLL data.A disk system using this interface is also called either MFM or RLL disk system. Newer stan-dards are also found in use today, which include ESDI, SCSI, and IDE. All of these newer stan-dards use RLL, even though they normally do not call attention to it. The main difference is theinterface between the computer and the disk drive. The IDE system is becoming the standardhard disk memory interface.

The enhanced small disk interface (ESDI) system, which has disappeared, is capable oftransferring data between itself and the computer at rates approaching 10 M bytes per second. AnST-506 interface can approach a transfer rate of 860 K bytes per second.

The small computer system interface (SCSI) system is also in use because it allows up toseven different disk or other interfaces to be connected to the computer through same interfacecontroller. SCSI is found in some PC-type computers and also in the Apple Macintosh system.An improved version, SCSI-II, has started to appear in some systems. In the future, this interfacemay be replaced with IDE in most applications.

The newest system is integrated drive electronics (IDE), which incorporates the diskcontroller in the disk drive and attaches the disk drive to the host system through a small inter-face cable. This allows many disk drives to be connected to a system without worrying about busconflicts or controller conflicts. IDE drives are found in newer IBM PS-2 systems and manyclones. Even Apple computer systems are starting to be found with IDE drives in place of theSCSI drives found in older Apple computers. The IDE interface is also capable of driving otherI/O devices besides the hard disk. This interface also usually contains at least a 32K-byte cachememory for disk data. The cache speeds disk transfers. Common access times for an IDE driveare often less than 10 ms, where the access time for a floppy-disk is about 200 ms.

Optical Disk MemoryOptical disk memory (see Figure 13-33) is commonly available in two forms: the CD-ROM(compact disk/read only memory) and the WORM (write once/read mostly). The CD-ROM isthe lowest cost optical disk, but it suffers from lack of speed. Access times for a CD-ROM are


FIGURE 13-33 The optical CD-ROM memory system.

typically 300 ms or longer, about the same as a floppy disk. (Note that slower CD-ROM devicesare on the market and should be avoided.) Hard disk magnetic memory can have access times aslittle as 11 ms. A CD-ROM stores 660M bytes of data, or a combination of data and musical pas-sages. As systems develop and become more visually active, the use of the CD-ROM drive willbecome even more common.

The WORM drive sees far more commercial application than the CD-ROM. The problemis that its application is very specialized due to the nature of the WORM. Because data may bewritten only once, the main application is in the banking industry, insurance industry, and othermassive data storing organizations. The WORM is normally used to form an audit trail of trans-actions that are spooled onto the WORM and retrieved only during an audit. You might call theWORM an archiving device.

Many WORM and read/write optical disk memory systems are interfaced to the micro-processor by using the SCSI or ESDI interface standards used with hard disk memory. The dif-ference is that the current optical disk drives are no faster than the most floppy drives. Some CD-ROM drives are interfaced to the microprocessor through proprietary interfaces that are not com-patible with other disk drives.

The main advantage of the optical disk is its durability. Because a solid state laser beam isused to read the data from the disk, and the focus point is below a protective plastic coating, thesurface of the disk may contain small scratches and dirt particles and still be read correctly. Thisfeature allows less care of the optical disk than a comparable floppy disk. About the only way todestroy data on an optical disk is to break it or deeply scar it.

The read/write CD-ROM drive is here and its cost is dropping rapidly. In the near future, weshould start seeing the read/write CD-ROM replacing floppy disk drives. The main advantage isthe vast storage available on the read/write CD-ROM. Soon, the format will change so that manyG bytes of data will be available. The new versatile read/write CD-ROM, called a DVD, became

13-5 VIDEO DISPLAYS 539

available in late 1996 or early 1997. The DVD functions exactly as the CD-ROM except that thebit density is much higher. The CD-ROM stores 660 M bytes of data, while the current-genreDVD stores 4.7G bytes or 8.5G bytes, depending on the current standard. The future standard,which requires a new drive, stores up to 17G bytes of data.

13-5 VIDEO DISPLAYS

Modern video displays are OEM (original equipment manufacturer) devices that are usuallypurchased and incorporated into a system. Today, there are many different types of video dis-plays available. Of the types available, either color or monochrome versions are found.

Monochrome versions usually display information using amber, green, or paper-white dis-plays. The paper-white display is becoming extremely popular for many applications. The mostcommon of these applications are desk-top publishing and computer-aided drafting (CAD).

The color displays are more diverse. Color display systems are available that accept in-formation as a composite video signal, much as your home television, as TTL voltage level sig-nals (0 or 5 V), and as analog signals (0-0.7 V). Composite video displays are disappearingbecause the available resolution is too low. Today, many applications require high-resolutiongraphics that cannot be displayed on a composite display such as a home television receiver.Early composite video displays were found with Commodore 64, Apple 2, and similar computersystems.

Video SignalsFigure 13-34 illustrates the signal sent to a composite video display. This signal is composedof several parts that are required for this type of display. The signals illustrated represent thesignals sent to a color composite-video monitor. Notice that these signals include not onlyvideo, but also include sync pulses, sync pedestals, and a color burst. Notice that no audiosignal is illustrated because one often does not exist. Rather than include audio with the com-posite video signal, audio is developed in the computer and output from a speaker inside thecomputer cabinet. It can also be developed by a sound system and output in stereo to externalspeakers. The major disadvantages of the composite video display are the resolution and colorlimitations. Composite video signals were designed to emulate television video signals so thata home television receiver could function as a video monitor.

Most modern video systems use direct video signals that are generated with separate syncsignals. In a direct video system, video information is passed to the monitor through a cable thatuses separate lines for video and also synchronization pulses. Recall that these signals were com-bined in a composite video signal.

A monochrome (one color) monitor uses one wire for video, one for horizontal sync, andone for vertical sync. Often, these are the only signal wires found. A color video monitor uses threevideo signals. One signal represents red, another green, arid the third blue. These monitors areoften called RGB monitors for the video primary colors of light: red (R), green (G), and blue (B).

The TTL RGB MonitorThe RGB monitor is available as either an analog or TTL monitor. The RGB monitor uses TTLlevel signals (0 or 5 V) as video inputs and a fourth line called intensity to allow a change in in-tensity. The RGB video TTL display can display a total of 16 different colors. The TTL RGBmonitor is used in the CGA (color graphics adapter) system found in older computer systems.

Table 13-4 lists these 16 colors and also the TTL signals present to generate them. Eightof the 16 colors are generated at high intensity and the other eight at low intensity. The three


Color burst

Sync pulse

Sync pedestal -

Video line

. Black level

FIGURE 13-34 The composite video signal.

video colors are red, green, and blue. These are primary colors of light. The secondary colors arecyan, magenta, and yellow. Cyan is a combination of blue and green video signals, and is blue-green in color. Magenta is a combination of blue and red video signals, and is a purple color.Yellow (high-intensity) and brown (low-intensity) are both a combination of red and green videosignals. If additional colors are desired, TTL video is not normally used. A scheme was devel-oped by using low and medium color TTL video signals, which provided 32 colors, but it provedof little application and never found widespread use in the field.

Figure 13-35 illustrates the connector most often found on the TTL RGB monitor or aTTL monochrome monitor. The connector illustrated is a 9-pin connector. Two of the connec-tions are used for ground, three for video, two for synchronization or retrace signals, and onefor intensity. Notice that pin 7 is labeled normal video. This is the pin used on a monochromemonitor for the luminance or brightness signal. Monochrome TTL monitors use the same 9-pinconnector as RGB TTL monitors.

TABLE 13-4 16 colorsfound in the CGA display. Intensity

0000000011111111

Red

0000111100001111

Green

0011001100110011

Blue

0101010101010101

Color

BlackBlueGreenCyanRedMagentaBrownWhiteGrayBright BlueBright GreenBright CyanBright RedBright MagentaYellowBright White


FIGURE 13-35 The 9-pinconnector found on a TTLmonitor.

DB9 Pin Function

1

2

3

4

5

6

7

8

9

Ground

Ground

Red video

Green video

Blue video

Intensity

Normal video

Horizontal retrace

Vertical retrace

The Analog RGB MonitorIn order to display more than 16 colors, an analog video display is required. These are oftencalled analog RGB monitors. Analog RGB monitors still have three video input signals, butdon't have the intensity input. Because the video signals are analog signals instead of two-levelTTL signals, they are any voltage level between 0.0 V and 0.7 V, which allows an infinitenumber of colors to be displayed. This is because an infinite number of voltage levels betweenthe minimum and maximum could be generated. In practice, a finite number of levels are gener-ated. This is usually either 256K, 16M, or 24M colors, depending on the standard.

Figure 13-36 illustrates the connector used for an analog RGB or analog monochromemonitor. Notice that the connector has 15 pins and supports both RGB and monochrome analogdisplays. The way data are displayed on an analog RGB monitor depends upon the interfacestandard used with the monitor. Pin 9 is a key, which means that no hole exists on the femaleconnector for this pin.

Most analog displays use a digital-to-analog converter (DAC) to generate each colorvideo voltage. A common standard uses a 6-bit DAC for each video signal to generate 64 dif-ferent voltage levels between 0 V and 0.7 V. There are 64 different red video levels, 64 differentgreen video levels, and 64 different blue video levels. This allows 64 x 64 x 64, or 262,144(256K) colors to be displayed.

DB15 Pin Function

1 Red video2 Green video (monochrome video)3 Blue video4 Ground5 Ground6 Red ground7 Green ground (monochrome ground)8 Blue ground9 Blocked as a key

10 Ground11 Color detect (ground on a color monitor)12 Monochrome detect (ground on a monochrome monitor)13 Horizontal retrace14 Vertical retrace15 Ground

FIGURE 13-36 The 15-pin connector found on an analog monitor.


Other arrangements are possible, but the speed of the DAC is critical. Most modern dis-plays require an operating conversion time of 25 ns to 40 ns maximum. When converter tech-nology advances, additional resolution at a reasonable price will become available. If 7-bitconverters are used for generating video, 128 x 128 x 128, or 2,097,152 (2M) colors are dis-played. In this system, a 21-bit color code is needed so that a 7-bit code is applied to each DAC.8-bit converters also find applications and allow 256 x 256 x 256, or 16,777,216 (16M) colors.

Figure 13-37 illustrates the video generation circuit employed in many common video stan-dards such as the short-lived EGA (enhanced graphics adapter) and VGA (variable graphicsarray), as used with an IBM PC. This circuit is used to generate VGA video. Notice that eachcolor is generated with an 18-bit digital code. Six of the 18 bits are used to generate each videocolor voltage when applied to the inputs of a 6-bit DAC.

A high-speed palette SRAM (access time of less than 40 ns) is used to store 256 different18-bit codes that represent 256 different hues. This 18-bit code is applied to the digital-to-analog converters. The address input to the SRAM selects one of the 256 colors stored as 18-bitbinary codes. This system allows 256 colors out of a possible 256K colors to be displayed atone time. In order to select any of 256 colors, an 8-bit code that is stored in the computer'svideo display RAM is used to specify the color of a picture element. If more colors are used ina system, the code must be wider. For example, a system that displays 1024 colors out of 256Kcolors requires a 10-bit code to address the SRAM that contains 1024 locations, each con-taining an 18-bit color code. Some newer systems use a larger palette SRAM to store up to 64Kof different color codes.

The Apple Macintosh-IIci uses a 24-bit binary code to specify each color in its color videoadapter. Each DAC is eight bits wide. This means that each converter can generate 256 differentvideo voltage levels. There are 256 x 256 x 256, or 16,777,216 different possible colors. As withthe IBM VGA standard, only 256 colors are displayed at a time. The SRAM in the Apple inter-face is 256 x 24 instead of 256 x 18.

Whenever a color is placed on the video display, provided that RTC is a logic 0, the systemsends the 8-bit code that represents a color to the DO-D7 connections. The PAL 16R8 then gen-erates a clock pulse for U10, which latches the color code. After 40 ns (one 25 MHz clock), thePAL generates a clock pulse for the DAC latches (U7, U8, and U9). This amount of time is re-quired for the palette SRAM to look up the 18-bit contents of the memory location selected byU10. Once the color code (18-bit) is latched into U7-U9, the three DACs convert it to threevideo voltages for the monitor. This process is repeated for each 40 ns-wide picture element(pixel) that is displayed. The pixel is 40 ns wide because a 25 MHz clock is used in this system.Higher resolution is attainable if a higher clock frequency is used with the system.

If the color codes (18-bits) stored in the SRAM must be changed, this is always accom-plished during retrace when RTC is a logic 1. This prevents any video noise from disrupting theimage displayed on the monitor.

In order to change a color, the systems uses the SO, SI, and S2 inputs of the PAL to selectUl, U2, U3, or U10. First, the address of the color to be changed is sent to latch U10, which ad-dresses a location in the palette SRAM. Next, each new video color is loaded into Ul, U2, andU3. Finally, the PAL generates a write pulse for the WE input to the SRAM to write the newcolor code into the palette SRAM.

Retrace occurs 70.1 times per second in the vertical direction and 31,500 times per secondin the horizontal direction for a 640 x 480 display. During retrace, the video signal voltage sentto the display must be 0 V, which causes black to be displayed during the retrace. Retrace itselfis used to move the electron beam to the upper left-hand corner for vertical retrace and to the leftmargin of the screen for horizontal retrace.

The circuit illustrated causes U4-U6 buffers to be enabled so that they apply 00000 each tothe DAC latch for retrace. The DAC latches capture this code and generate 0 V for each videocolor signal to blank the screen. By definition, 0 V is considered to be the black level for videoand 0.7 V is considered to be the full intensity on a video color signal.


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The resolution of the display, for example 640 x 480, determines the amount of memoryrequired for the video interface card. If this resolution is used with a 256-color display (eight bitsper pixel), then 640 x 480 bytes of memory (307,200) are required to store all of the pixels forthe display. Higher-resolution displays are possible, but, as you can imagine, even more memoryis required. A 640 x 480 display has 480 video raster lines and 640 pixels per line. A raster lineis the horizontal line of video information that is displayed on the monitor. A pixel is the smallestsubdivision of this horizontal line.


FIGURE 13-38 A videoscreen illustrating the rasterlines and retrace.

Video line '

Horizontal retrace '

Vertical retrace

Figure 13-38 illustrates the video display, showing the video lines and retrace. The slant ofeach video line in this illustration is greatly exaggerated, as is the spacing between lines. This il-lustration shows retrace in both the vertical and horizontal directions. In the case of a VGA dis-play, as described, the vertical retrace occurs exactly 70.1 times per second and the horizontalretrace occurs exactly 31,500 times per second. (The Apple Macintosh-IIci uses a vertical rate of66.67 Hz and a horizontal rate of 35 KHz to generate a 640 x 480 color display.)

In order to generate 640 pixels across one line, it takes 40 ns x 640, or 25.6 jis. A hori-zontal time of 31,500 Hz allows a horizontal line time of 1/31,500, or 31.746 jis. The differencebetween these two times is the retrace time allowed to the monitor. (The Apple Macintosh Ilcihas a horizontal line time of 28.57 |0,s.)

Because the vertical retrace repetition rate is 70.1 Hz, the number of lines generated is de-termined by dividing the vertical time into the horizontal time. In the case of a VGA display (a640 x 400 display), this is 449.358 lines. Only 400 of these lines are used to display information;the rest are lost during the retrace. Because 49.358 lines are lost during the retrace, the retracetime is 49.358 x 31.766 (is, or 1568 [is. It is during this relatively large amount of time that thecolor palette SRAM is changed or the display memory system is updated for a new video dis-play. In the Apple Macintosh Ilci computer (640 x 480), the number of lines generated is 525lines Of the total number of lines, 45 are lost during vertical retrace.

Other display resolutions are 800 x 600 and 1024 x 768. The 800 x 600 SVGA (superVGA) display is ideal for a 14" color monitor, while the 1024 x 768 EVGA or XVGA (extendedVGA) is ideal for a 21" or 25" monitor used in CAD systems. These resolutions sound like justanother set of numbers, but realize that an average home television receiver has a resolution ap-proximately 400 x 300. The high-resolution display available on computer systems is muchclearer than that available as home television. A resolution of 1024 x 768 approaches that foundin 35 mm film. The only disadvantage of the video display on a computer screen is the numberof colors displayed at a time, but as time passes, this will surely improve. Additional colors allowthe image to appear more realistically because of subtle shadings that are required for a truehigh-quality, life-like image.

If a display system operates with a 60 Hz vertical time and a 15,600 Hz horizontal time, thenumber of lines generated is 15,600/60, or 260 lines. The number of usable lines in this system ismost likely 240, where 20 are lost during vertical retrace. It is clear that the number of scanninglines is adjustable by changing the vertical and horizontal scanning rates. The vertical scanning

13-6 SUMMARY 545

rate must be greater than or equal to 50 Hz, or flickering will occur. The vertical rate must not behigher than about 75 Hz or problems with the vertical deflection coil may occur. The electronbeam in a monitor is positioned by an electrical magnetic field generated by coils in a yoke thatsurrounds the neck of the picture tube. Because the magnetic field is generated by coils, the fre-quency of the signal applied to the coil is limited.

The horizontal scanning rate is also limited by the physical design of the coils in the yoke.Because of this, it is normal to find the frequency applied to the horizontal coils within a narrowrange. This is usually 30,000 Hz-37,000 Hz or 15,000 Hz-17,000 Hz. Some newer monitors arecalled multisync monitors because the deflection coil is taped so that it can be driven with dif-ferent deflection frequencies. Sometimes, both the vertical and horizontal coils are both taped fordifferent vertical and horizontal scanning rates.

High-resolution displays use either interlaced or non-interlaced scanning. The non-interlacedscanning system is used in all standards except the highest. In the interlaced system, the video imageis displayed by drawing half the image first with all of the odd scanning lines, then the other half isdrawn using the even scanning lines. Obviously, this system is more complex and is only more effi-cient because the scanning frequencies are reduced by 50 percent in an interlaced system. For ex-ample, a video system that uses 60 Hz for the vertical scanning frequency and 15,720 Hz for thehorizontal frequency generates 262 (15,720/60) lines of video at the rate of 60 full frames persecond. If the horizontal frequency is changed slightly to 15,750 Hz, 262.5 (15,750/60) lines aregenerated, so two full sweeps are required to draw one complete picture of 525 video lines. Noticehow just a slight change in horizontal frequency doubled the number of raster lines.

13-6 SUMMARY

1. The HOLD input is used to request a DMA action, and the HLDA output signals that thehold is in effect. When a logic 1 is placed on the HOLD input, the microprocessor (1) stopsexecuting the program; (2) places its address, data, and control bus at their high-impedancestate; and (3) signals that the hold is in effect by placing a logic 1 on the HLDA pin.

2. A DMA read operation transfers data from a memory location to an external I/O device. ADMA write operation transfers data from an I/O device into the memory. Also available is amemory-to-memory transfer that allows data to be transferred between two memory loca-tions by using DMA techniques.

3. The 8237 direct memory access (DMA) controller is a four-channel device that can be ex-panded to include an additional channel of DMA.

4. Disk memory comes in the form of floppy disk storage that is found as either the 5lfa" mini-floppy disk or 3!/2" micro-floppy disk. Both disks are found as double-sided, double-density(DSDD), or as high-density (HD) storage devices. The DSDD 5V4" disk stores 360 K bytesof data and the HD 5V4" disk stores 1.2 M bytes of data. The DSDD 3V2" disk stores 720 Kbytes of data and the HD 3l/2" disk stores 1.44 M bytes of data.

5. Floppy disk memory data are stored using NRZ (non-return to zero) recording. This methodsaturates the disk with one polarity of magnetic energy for a logic 1 and the opposite polarityfor a logic 0. In either case, the magnetic field never returns to 0. This technique eliminatesthe need for a separate erase head.

6. Data are recorded on disks by using either modified frequency modulation (MFM) or run-length limited (RLL) encoding schemes. The MFM scheme records a data pulse for a logic1, no data or clock for the first logic 0 of a string of zeros, and a clock pulse for the secondand subsequent logic 0 in a string of zeros. The RLL scheme encodes data so that 50 percentmore information can be packed onto the same disk area. Most modern disk memory sys-tems use the RLL encoding scheme.


7. Video monitors are either TTL or analog. The TTL monitor uses two discrete voltage levelsof 0 V and 5.0 V. The analog monitor uses an infinite number of voltage levels between0.0 V and 0.7 V. The analog monitor can display an infinite number of video levels, whilethe TTL monitor is limited to two video levels.

8. The color TTL monitor displays 16 different colors. This is accomplished through threevideo signals (red, green, and blue) and an intensity input. The analog color monitor can dis-play an infinite number of colors through its three video inputs. In practice, the mostcommon form of color analog display system (VGA) can display 256K different colors.

9. The video standards found today include VGA (640 x 480), SVGA (800 x 600), and EVGAor XVGA (1024 x 768). In all three cases, the video information can be 256 colors out of atotal possible 256K colors.

13-7 QUESTIONS AND PROBLEMS

1. Which microprocessor pins are used to request and acknowledge a DMA transfer?2. Explain what happens whenever a logic 1 is placed on the HOLD input pin.3. A DMA read transfers data from _______ to _______.4. A DMA write transfers data from _______ to _______.5. The DMA controller selects the memory location used for a DMA transfer through what bus

signals?6. The DMA controller selects the I/O device used during a DMA transfer by which pin?7. What is a memory-to-memory DMA transfer?8. Describe the effect on the microprocessor and DMA controller when the HOLD and HLDA

pins are at their logic 1 levels.9. Describe the effect on the microprocessor and DMA controller when the HOLD and HLDA

pins are at their logic 0 levels.10. The 8237 DMA controller is a _____ channel DMA controller.11. If the 8237 DMA controller is decoded at I/O ports 2000H-200FH, what ports are used to

program channel 1 ?12. Which 8237 DMA controller register is programmed to initialize the controller?13. How many bytes can be transferred by the 8237 DMA controller?14. Write a sequence of instructions that transfer data from memory location 21000H-210FFH

to 20000H-200FFH by using channel 2 of the 8237 DMA controller. You must initialize the8237 and use the latch described in Section 12-1 to hold A19-A16.

15. Write a sequence of instructions that transfer data from memory to an external I/O device byusing channel 3 of the 8237. The memory area to be transferred is at location 20000H-20FFFH.The 5l/4" disk is known as a _______- floppy disk.The 3V4" disk is known as a - floppy disk.

16.17.18. Data are recorded in concentric rings on the surface of a disk known as a ________.19. A track is divided into sections of data called _______.20. On a double-sided disk, the upper and lower tracks together are called a _______.21. Why is NRZ recording used on a disk memory system?22. Draw the timing diagram generated to write a 1001010000 using MFM encoding.23. Draw the timing diagram generated to write a 1001010000 using RLL encoding.24. What is a flying head?25. Why must the heads on a hard disk be parked?26. What is the difference between a voice coil head position mechanism and a stepper motor

head positioning mechanism?

13-7 QUESTIONS AND PROBLEMS

27. What is a WORM?28. What is a CD-ROM?29. What is the difference between a TTL monitor and an analog monitor?30. What are the three primary colors of light?31. What are the three secondary colors of light?32. What is a pixel?

547

_ lines of video informa-33. A video display with a resolution of 800 x 600 contains __tion, with each line divided into _____ pixels.

34. Explain how a TTL RGB monitor can display 16 different colors.35. Explain how an analog RGB monitor can display an infinite number of colors.36. If an analog RGB video system uses 7-bit DACs, it can generate ______ different colors.37. Why does standard VGA allow only 256 different colors out of 256K colors to be displayed

at one time?38. If a video system uses a vertical frequency of 60 Hz and a horizontal frequency of 32,400

Hz, how many raster lines are generated?

dma

Technology

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highspeed memory

memory transfers

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