Low Power DLL Design

Yanqing Zhangyanqing@virginia.eduDLL Design for Low Power and JitterOutlineDLL Quick ReviewSeminal PapersFirst dual loop with infinite phase capture rangeFirst true dual loop architectureSummary of DLL Design IssuesA Walk Through TimeThe first all digital DLL (1999)The first mixed mode DLL (1999)Process variation problemFalse lock problemFast lock acquisitionPFD jitterCP jitterSummary of DLL Design SpaceDiscussion Questions

OutlineDLL Quick ReviewSeminal PapersFirst dual loop with infinite phase capture rangeFirst true dual loop architectureSummary of DLL Design IssuesA Walk Through TimeThe first all digital DLL (1999)The first mixed mode DLL (1999)Process variation problemFalse lock problemFast lock acquisitionPFD jitterCP jitterSummary of DLL Design SpaceDiscussion Questions

DLL Quick Over/Re-ViewCPPDLPF

VCDLVcontDLL=PLL without frequency synthesis. VCDL replaces VCO. Delay line instead of frequency generator. Used to generate multiple phases of same frequency of clock

Used to generate multiple phases of clock-same frequencyAdvantage 1: less noise without VCOAdvantage 2: VCDL gain only, one less pole, more stability more relaxedPD only, charge pump not necessary, but usually used for infinite gain4DLL Quick Over/Re-ViewAdvantages:Doesnt have jitter from VCOVCDL pure gainone less polestability relaxedno zero Disadvantages:Reference noise feed throughFinite delay range, no new frequenciesSuspect to jitter from Vcont OutlineDLL Quick ReviewSeminal PapersFirst dual loop with infinite phase capture rangeFirst true dual loop architectureSummary of DLL Design IssuesA Walk Through TimeThe first all digital DLL (1999)The first mixed mode DLL (1999)Process variation problemFalse lock problemFast lock acquisitionPFD jitterCP jitterSummary of DLL Design SpaceDiscussion Questions

Dual Loop DLL DesignFirst ever dual loop designInfinite delay locking (2)Fully differential signals in loop[1]Phase InterpolationFreq MultiplyingDuty Cycle Correction (DCC)140 ps p2p jitter @ 250 MHz65 mW @ 2.5 V1 ps/mV supply sensitivityDual Loop DLL Design

Quadrature mixingFully differentialless supply sensitivityless jitterSlew rate limitedPhase gain induces dithering(jitter) when in lockDifferential controlsPhase SelectsClock SignalsI weightQ weight[1]Dual Loop DLL Design

[1]Fast lock acquisitionFully differentialVoltage headroom limitednot for contemporary designsPhase select signalsLoad isolationturbo for fast acquisitionDual Loop DLL Design (2) True dual loopcoarse loop+fine loop

Quadrature mixing slew rate limitedjitter sensitiveinterpolate smaller phases

Clocks bufferedless slewless jitterStage to stage isolation or load matchingno data dependency jitter

PD offset identified as a problemMismatch/Variation in delay cells identified as a problem

Fully digital domain[2]Dual Loop DLL Design (2)

All buffer delay elements differential for less supply sensitivityUses replica biasing for good linearity, wide operating rangeAlways static current[2]Dual Loop DLL Design (2)

Phase step must be smallsmall dithering amplitudeless jitterSeamless phase transitionGate-drain feedthrough vs. data dependency[2][2]Dual Loop DLL Design (2)80kHz-400MHz locking range68 ps p2p jitter @250MHz102 mW power dissipation @3.3V0.4ps/mV supply sensitivity

[2]Self-biased TechniqueSelf-biased throughout DLLBias tracks changes in Vccconstant currentconstant delayimproved jitterCharge pump current scales with frequencyDead-zone improved due to fully symmetric topology

Delay cellBias CircuitCharge Pump[3][3][3]Self-biased Technique262 ps p2p jitter @ 250 MHz29 mW @ 2.5 VCrudely designed dual loopShows tradeoff of design effortless jittermore power

OutlineDLL Quick ReviewSeminal PapersFirst dual loop with infinite phase capture rangeFirst true dual loop architectureSummary of DLL Design IssuesA Walk Through TimeThe first all digital DLL (1999)The first mixed mode DLL (1999)Process variation problemFalse lock problemFast lock acquisitionPFD jitterCP jitterSummary of DLL Design SpaceDiscussion Questions

Summary of DLL DesignMetrics of interest include:P2p jitterPowerSupply sensitivityOperating rangeAcquisition timeSources of jitter include:Supply/substrate inducedReference feedthroughDigital control resolutionDelay line resolutionPhase mixer capabilitiesVcont ditheringProcess variation

Design issues include:Jitter reduction in VCDLPD accuracy and speedCP current balanceDigital integrationHarmonic locking and startupDuty cycle correctionProcess variation controlFast lock acquisition

Comparison for the Early YearsOperating RangeMain FrequencyP2p jitterPowerMain ContributionYear[1]250 MHz250 MHz140 ps65 mWPhase Interpolation for infinite delay lock1994[2]80 kHz-400MHz250 MHz68 ps102 mWTrue coarse-fine dual loop1997[3]2.5 kHz-400MHz250 MHz262 ps29 mWSelf-biased technique1996Observation: the less jitter, the more powerK=jitterpower a more fair comparison metric?Rest of papers to: spark interest, good paper to go to if ur looking into a certain subjectHistory of DLLs, jitter and powerDont give away all their secrets18OutlineDLL Quick ReviewSeminal PapersFirst dual loop with infinite phase capture rangeFirst true dual loop architectureSummary of DLL Design IssuesA Walk Through TimeThe first all digital DLL (1999)The first mixed mode DLL (1999)Process variation problemFalse lock problemFast lock acquisitionPFD jitterCP jitterSummary of DLL Design SpaceDiscussion Questions

Pseudo All-digital DLLAside from DCC, all digitalDigital differential delay lineShorter line brings lower power, less jitter accumulationLatch coupling decreases PVT variationBetter resolutionState controlled looppower down mode256 ps p2p jitter @400MHz340 mW @ 3.3 VDoesnt address supply noise.

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Mixed-mode DLLDigital coarse+analog fineCounter less area and power than digital delay lineSeveral jitter suppression methodsCounting averages out reference feedthrough jitterLow gain in fine loop reduces Vcont jitterDifferential elements in fine loop reduce supply jitterFast lock acquisition from digital coarse loopNo multiple phases.Only for CDR and deskewing114 ps p2p jitter @300MHz70 mW @ 3.3V

[5]Process Variation SuppressionCross fed signals suppress effects of process variations in multiple clock phase generation26 ps p2p jitter @150 MHz

[6]False Lock ProblemAuxiliary loop for automatic cycle detectionStandard practices to reduce jitter in VCDLAux loop can power downLow gain CP to reduce jitter and power56 ps p2p jitter @ 133 MHz30 mW @ 2.5V

[7]23Fast Lock AcquisitionOne shot asynchronous fast lock circuitControl word stored to save powerFF power saved by ICFFFine delay unit resolution to reduce resolution jitterDelay unit cap basedless supply sensitivity30 ps p2p jitter @ 100 MHz0.3 mW @ 1 V

[8]PFD JitterOne shot jitter reduced with improved PFDless jitter on VcontSubdued more with smaller gain CP58 ps p2p jitter @ 100 MHz15 mW @ 1.8V

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Charge Pump CalibrationFreq synthesis (if N, M prime)Short, differential delay line = low power (5 GHz)Calibrated CPCP injects much noise into systemShort channel effects Switching imbalanceCurrent matchingCalibrated vs. uncalibrated = 1 ps vs. 20 psDiff amp must be designed carefullyA main source of jitter8 ps p2p jitter @ 5 GHz36 mW @ 1.2V

[10]OutlineDLL Quick ReviewSeminal PapersFirst dual loop with infinite phase capture rangeFirst true dual loop architectureSummary of DLL Design IssuesA Walk Through TimeThe first all digital DLL (1999)The first mixed mode DLL (1999)Process variation problemFalse lock problemFast lock acquisitionPFD jitterCP jitterSummary of DLL Design SpaceDiscussion Questions

Comparison Across the Years Operating RangeMain FrequencyP2p jitterPowerMain ContributionYear[1]250 MHz250 MHz140 ps65 mWPhase Interpolation for infinite delay lock1994[2]80 kHz-400 MHz250 MHz68 ps102 mWTrue coarse-fine dual loop1997[3]2.5 kHz-400 MHz250 MHz262 ps29 mWSelf-biased technique1996[4]300,400 MHz400 MHz245 ps340 mWPseudo All-digital1999[5]4-400 MHz300 MHz114 ps70 mWMixed-mode dual loop, jitter suppression1999[6]150 MHz150 MHz26 ps??Process mismatch induced jitter 2003[7]30-200 MHz133 MHz56 ps30 mWFalse lock problem2004[8]??100 MHz30 ps0.3 mWFast lock acquisition2005[9]50-150 MHz100 MHz58 ps15 mWPFD one shot jitter, dynamic charge pump gain2007[10]0.5-5 GHz5 GHz8 ps36 mWCharge pump calibration2008Summary of TrendsThrough time, power has decreased, jitter has decreased, frequency increaseshow is this possible?Some advances inherent: process scaling, voltage scalingSome advances effort of designers: differential components, digital integration, etc.

Summary of TrendsThere are so many issues ([1]-[10]), how do I know what the significance of each is?No way to isolate a variable (no pare-to curve imminent)What is a reasonable metric of comparison?Is it fair to say that a jitter of 250 ps for 100MHz lock is bad?Is it fair to say consuming 3x power @10GHz is bad when compared @100 MHz?Should attempt to normalize some metric

Summary of TrendsP2p jitterFrequencyPower% Jitter/FreqxPowerMain Contribution[1]140 ps250 MHz65 mW3.5%2.27 mWPhase Interpolation for infinite delay lock[2]68 ps250 MHz102 mW1.7%1.73 mWTrue coarse-fine dual loop[3]262 ps250 MHz29 mW6.55%1.89 mWSelf-biased technique[4]245 ps400 MHz340 mW9.8%33.3 mWPseudo All-digital[5]114 ps300 MHz70 mW3.42%2.39 mWMixed-mode dual loop, jitter suppression[6]26 ps150 MHz??0.39%??Process mismatch induced jitter [7]56 ps133 MHz30 mW0.74%0.22 mWFalse lock problem[8]30 ps100 MHz0.3 mW0.3%.0009 mWFast lock acquisition[9]58 ps100 MHz15 mW0.58%0.08 mWPFD one shot jitter, dynamic charge pump gain[10]8 ps5 GHz36 mW4%1.44 mWCharge pump calibrationSummary of Trends

Where is the design space now?Power efficiency of lower frequencies extremely goodspace for lower power sacrificing jitterEfficiency of RF frequencies similar to a decade agopioneering research spaceSummary of TrendsSo what is the general design strategy?Choose a jitter constraint suitable to the application frequency rangeThere are three main places to control jitter: choosing the right architecture, the charge pump, the VCDL

OutlineDLL Quick ReviewSeminal PapersFirst dual loop with infinite phase capture rangeFirst true dual loop architectureSummary of DLL Design IssuesA Walk Through TimeThe first all digital DLL (1999)The first mixed mode DLL (1999)Process variation problemFalse lock problemFast lock acquisitionPFD jitterCP jitterSummary of DLL Design SpaceDiscussion Questions

Discussion QuestionsWhat are the assumptions made on the reference clock?What are some of the sources of noise?Why is duty cycle important?Which blocks are the most important? Think in terms of: power consumption, jitter suppression.How far can digital integration go? Which applications are suitable for digital DLLs?