digital&icaprojectand&verificaon& place&and&route& · lef: library...
TRANSCRIPT
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Digital IC-‐Project and Verifica=on
Place and Route
Oskar Andersson
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Outline
• Backend ASIC Design flow (Physical Design) • General steps
• Input files • Floorplanning • Placement • ClockTree-‐synthesis • Rou=ng
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Typical Backend Design Flow
• Synthesis: – Synopsys Design Compiler (Design Vision)
• Placement: – Encounter Digital Implementa=on
• Backend netlist Verifica=on – Modelsim
• Fabrica=on – ASIC vendor, e.g. UMC, ST, TSMC
Synthesis
Placement & Routing
Backend netlist Verification
Fabrication
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
SoC Encounter Flow
Floorplan
IO Placement
Cell Placement
IO Filler Placement Connect Power Clk tree synthesis
Core Filler Placement
Design Rule Check
Tech
Libraries
Netlist, GDS
Signal Route
Netlist
Power Planning
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
• Floorplan: – Placement area – IOs – RAM/ROM
SoC Encounter Flow
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
• Power Planning - Design a power ring - Add horizontal and
vertical power stripes
SoC Encounter Flow
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
• Place Cells: – Place all the standard
cells into the rows
SoC Encounter Flow
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Clock Tree Synthesis: – Places clock buffers – Timing constraints
– Skew etc
SoC Encounter Flow
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
• Connect Power Supply: – Core Power – Pad Power
• Add FILLER cells • core filler cells • IO filler cells
SoC Encounter Flow
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
• Route Clock tree: – Finds an “optimal” way – Reduces skew
• Route signal nets – Final step
SoC Encounter Flow
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Demo Layout
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Technology Descrip=on Files
LEF: Library Exchange Format
– Technology: Design rules, Capacitance, Resistance, Antenna factor, Vias Ø header.lef
– Cells & pads: Size, Class, Placement, Pin Information,
Obstructions. Ø Standard_cell.lef Ø IO.lef
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
LEF-‐Example: Inverter MACRO IV CLASS CORE ; FOREIGN IV 0.000 0.000 ; ORIGIN 0.00 0.00 ; SIZE 3.00 BY 12.00 ; SYMMETRY x y ; SITE CORE ; PIN A DIRECTION INPUT ; ANTENNASIZE 1.4 ; PORT LAYER metal1 ; RECT 0.50 5.00 1.00
5.50 ; END END A
OBS LAYER metal1 ; RECT 1.90 6.50 2.60
7.20 ; RECT 0.40 4.90 1.00
5.60 ;
Physical cell size
Terminals with physical placement
A Q
gnd!
vdd! vdd!
gnd!
A Q
Obstruc=ons
Layout Abstract LEF
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Design Description Files
Enc: Encounter Format – Netlist, Layout
DEF: Design Exchange Format (not used in
our flow. – Netlist, Layout
Verilog – Netlist, generated from synthesis tool
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Required Data for PnR (Faraday 130nm)
• LEF: Library Exchange Format – header.lef – standardCell.lef : Cell Library – IO.lef : Pad Library – memory.lef : custom
• lib/tlf: libraries that contain =ming informa=on • sdc: Synopsys Design Constraint (generated during synthesis).
Op=onal • Memory: memory.lib • Design (netlist): your_design.v
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Star=ng the SoC Encounter ini#de dicp13 velocity Remember to maintain the directory hierarchy.
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Design Import
Will be provided
Needs to be specified
Design -‐> Import Design /usr/local-‐eit/cad2/far130/syn2010/
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Floorplan
• A star=ng floorplan is created (required area is es=mated by the tool)
• Global and detailed rou=ng grids are created
• The core rows are created • Sites for IOs are created
– IO and block to core distance is defined by the user
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Floorplanning
RAM
IO Site
rows
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Core Rows
Vdd GND
If rows are flipped and abut VDD and GND can be shared by 2 rows. Default setting!
Vdd
GND Vdd
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Floorplan Setup
IO to core distance
Core utilization
Floorplan -‐> Specify Floorplan
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Block Placement
Flight lines will indicate location of the pins
Block: Circuitry that is pre-routed, e.g., RAM.
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
IO Placement
• Specify loca=on/orienta=on of pads – Input, output – core-‐power, pad-‐power
• Recommenda=on: – Put core power supply on top or bo'on – Use gaps in the pad frame for addi=onal power
supply. – !No CORE power supply at the corners! – The more supplies the be`er
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Power Rings
• Power paths are planned and modified before rou=ng
• Crea=on of power rings that surround all blocks and core.
• Crea=on of stripes over rows • Connects rings, stripes and pads
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Power Rings cont’d
vdd
stripes gnd
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Power Ring Setup
Choose upper layers (say metal 3 or 4)
Power-‐> Power planning -‐> Add Rings Power-‐> Power planning -‐> Add Stripes
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Connec=ng Power (sRoute)
between • IO power pins within IO rows
• CORE ring wires and the IO power pins
• stripes and core rings
• block power pins and the CORE ring wires
Route-‐> Special Route
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Cell Placement
• Initial cell placement
• Moves, swaps changes orientation of cells to minimize required wire length
• Optimizes for wire length and net crossings • A post CTS optimization may be carried out
to optimize the design
Place -> Standard Cells
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Clock Tree Synthesis
• Clockpad and output need to defined in a specifica=on file. – clockpad/O
• Clock tree is synthesized and routed with highest priority to minimize clock skew.
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Clock Skew
• Absolute Skew -Delay from input to leaf cell
• Relative Skew
-Delay difference between leaf cells
Danger! Too much clock skew may: 1) Force you to reduce clock rate 2) Cause malfunction at any clock
rate
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Distributed Buffers in H-tree
Small relative skew
Absolute skew of less importance
Clock
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
• create_clock –period value –name clk_name
–add [get_ports clk]
• Generate Clock tree specification createClockTreeSpec –output file_name.ctstch
-routeClknet -buffer buffer_list
• Specify CTS file and synthesize clock tree. specifyClockTree -clkfile file_name.ctstch
clockDesign –specFile file_name.ctstch –clk clk_name
deleteTrialRoute
CTS commands
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Synthesized Clock tree
Clock buffers are placed in the core row gaps
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Core filler cell
Core filler cells ensure the continuity of power/ground rails and N+/P+ wells in the row. Filler cells will close any gap it is important to perform CTS before filler cell placement.
before after Place -> Filler -> Add filler Place -> Filler -> Add IO filler
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Signal Rou=ng
• Signal rou=ng – Connects cells according to netlist – Metal wires are connected over several layers
• Rou=ng =me is strongly dependent on the design complexity Route -> Nano Route
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Verification and Tapeout
Verification (in SoCEnc) – Connectivity, Antenna ....
Export
– Verilog (netlist) – sdf (timing) – GDS II
Post-layout simulation
tapeout
Verify
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
Rou=ng Script
• Each command is automa=cally wri`en in a script file encounter.cmd
• Script needs to be trimmed (remove unnecessary commands)
• Easy to change parameters • Can be reused with modifica=ons • Time to do PnR itera=vely is reduced • Serves as documenta=on and makes it possible to repeat the flow
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Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on Place and Route
What’s next?
• Con=nue in the lab with Assignment 1 – The design needs to be taken through
– Simula=on, including post-‐synthesis – Synthesis – Place and Route