digital to analog converter part 2 - renesas e … microcontrollers/digital_to... · the pitfalls...

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© 2008, Renesas Technology America, Inc., All Rights Reserved 1 Course Introduction Purpose This course provides an overview of the PWM type Digital-to-Analog (D/A) converter (or simply, D/A) that some H8 series microcontrollers (MCUs) provide. Objectives Learn about applications for PWM D/As. Understand the PWM D/A implementation and how this on-chip peripheral function is controlled. Get tips for applying the on-chip PWM D/A converter included on some H8 series MCUs: the PWM14 (or PWMX) peripheral. Content 19 pages 3 questions Learning Time 25 minutes

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Page 1: DIGITAL TO ANALOG CONVERTER PART 2 - Renesas e … Microcontrollers/Digital_to... · the pitfalls of implementing analog circuits with digital process technology Offer greater resolution

© 2008, Renesas Technology America, Inc., All Rights Reserved

1

Course Introduction

Purpose

� This course provides an overview of the PWM type Digital-to-Analog

(D/A) converter (or simply, D/A) that some H8 series microcontrollers

(MCUs) provide.

Objectives

� Learn about applications for PWM D/As.

� Understand the PWM D/A implementation and how this on-chip

peripheral function is controlled.

� Get tips for applying the on-chip PWM D/A converter included on some

H8 series MCUs: the PWM14 (or PWMX) peripheral.

Content

� 19 pages

� 3 questions

Learning Time

� 25 minutes

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© 2008, Renesas Technology America, Inc., All Rights Reserved

2

PWM D/A Applications

Radio tuners

High-precision voltage-to-frequency converters (VCOs)

Digital servo systems

And more

High-resolution analog-output applications

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© 2008, Renesas Technology America, Inc., All Rights Reserved

3

Convert a number to an analog representation while avoiding

the pitfalls of implementing analog circuits with digital process

technology

Offer greater resolution than traditional D/As such as R-2R types

Eliminate many of the errors inherent in traditional D/A designs

Reduce the constraints on the output filter

Renesas Solution: PWM14 D/A Converter

� Low impedance digital buffer drives high-impedance

analog circuit, eliminating effects of capacitive and

resistive loading

� Resolution depends only on number of bits in the

counter/compare circuit

PWM D/A Design Goals

D/A Converter

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© 2008, Renesas Technology America, Inc., All Rights Reserved

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PWM Conversion Basics

t1 t2 t1 = t2

0.00 Volts

2.50 Volts

0V

5V

Vout = 1.25 Volts

Output level is not affected by frequency

if the filter is designed correctly.

0 3

Output A

Output B

25%

25%

f1

f2

R

C

A

B

Vout = Vcc x Duty Cycle

Vout = 2.50 Volts

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© 2008, Renesas Technology America, Inc., All Rights Reserved

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Output Frequency, Filters

Nyquist criteria: Must generate output samples at 2x the highest

frequency of the waveform being recreated

(MINIMUM requirement—faster sample rates are better)

Filtering the output: If you output samples at twice the frequency,

you may need a filter with a very sharp roll-off

�to decrease ripple to an acceptable level.

Sampling at higher rates allows the use of

simpler, less-expensive filters.

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© 2008, Renesas Technology America, Inc., All Rights Reserved

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H8 PWM D/A Converter

DACR: PWM D/A Control Register (6 bits)

DADRA: PWM D/A Data Register A (15 bits)

DADRB: PWM D/A Data Register B (15 bits)

DACNT: PWM D/A Counter (14 bits)

Module Data Bus

PWX0

PWX1

Bus Interface

Internal ClockØ

Basic CycleCompare-match A

Basic CycleCompare-match B

Fine-adjustmentPulse Addition B

Fine-adjustmentPulse Addition A

Basic Cycle Overflow

Internal Data Bus

ComparatorA

ComparatorB

14-bit Up Counter(DACNT)

DataRegister (DADRA)

Control Register (DACR)

ControlLogic

Clock Selection

Module Stop

Ø/2

Clock

DataRegister (DADRB)

All-digital design

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© 2008, Renesas Technology America, Inc., All Rights Reserved

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Registers in Detail

� IIEC: Controls the multiplexing of the access to the SCI and

the IIC / PWMX registers

� REGS: Controls access to various registers within the

PWMX peripheral.

Design issue: You must use a software driver that will maintain the

values of these pointer bits when a context switch

occurs within the application.

In some H8 MCUs, various addresses are shared by

different registers within a module.

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© 2008, Renesas Technology America, Inc., All Rights Reserved

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Counter Register

Design tips: - Writing to this register will affect the conversion cycle

on both channels (PWMX0 and PWMX1) of the

PWM14 converter.

- When reading this register, shift down by 2 to isolate

the counter bits (i.e., count_value = DACNT >> 2).

Design constraint: DACNT register must be written and read with a 16-bit

access. (An 8-bit access will yield incorrect results.)

DACNT

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DA Data Registers

Design constraints: - Although the register could be read with either an

8-bit or 16-bit access; however, you must write it

using a 16-bit access to get correct results.

- Only certain values will actually cause a pulse to be

output on the output pin, based on the CFS bit.

DADR

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PWM14 Control Register

Clock Select (0 = system clock = tcyc; 1 = system clock/2 = tcyc x 2)

Output select (0 = DIRECT = sum the low part of the waveform;

1 = INVERTED = sum the high parts of the waveform

PWM Enable (0=disabled; 1 = enabled)

Controls the output of the individual channels (0=disabled

1= enabled. [These are the ONLY channel-unique bits in this register.])

Design tip: Do not use the TEST bit in a normal application;

doing so will cause improper converter operation.

DACR

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© 2008, Renesas Technology America, Inc., All Rights Reserved

13

Controlling the PWM output

When CKS = 0, T = tPROCESSOR CLOCK

When CKS = 1, T = (tPROCESSOR CLOCK ) x 2

Conversion time = T x 16384 (for 14-bit resolution)

Basic Cycle: If CFS = 0, tf = T x 64

If CFS = 1, tf = T x 256

Output: If OS = 0, DACNT represents total tL time

If OS = 1, DACNT represents total tH time

tL tH

CKS = 0

CKS = 1

If CKS=0, the T = 1/10MHz conversion = T x 16384 = 1638.4µs

With this CKS setting,if CFS = 0, Base cycle = T x 64 = 1/10MHz x 64 = 6.4µsif CFS = 1, Base cycle = T x 256 = 1/10MHz x 256 = 25.6µs

If CKS=1, the T = (1/10MHz) x 2 conversion = T x 2 x 16384 = 3276.8µs

With this CKS setting:if CFS = 0, Base cycle = T x 64 = 1/10MHz x 2 x 64 = 12.8µsif CFS = 1, Base cycle = T x 256 = 1/10MHz x 2 x 256 = 51.2µs

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Filters Revisited

For a 10MHz CPU clock and a 14-bit PWM D/A conversion:

Conversion time = 1638.4µs

Basic cycle = 6.4µs

Therefore, the basic cycle is a full 8 octaves below the conversion frequency.

Remnants of the basic cycle will be about 48dB below the conversion frequency.

Assuming that we are trying to recreate the conversion frequency, remnants of the

basic cycle are still 42dB below the frequency we are trying to recover.

From PWM D/A

To analog circuit

R

C

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© 2008, Renesas Technology America, Inc., All Rights Reserved

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Maximum Output Frequency

According to the Nyquist criteria, the theoretical maximum frequency

that the PWM D/A can generate = 1/2 x Conversion time.

� With a 10MHz clock and a full 14-bit conversion:

– Conversion time = 1638.4µs

– Highest output frequency = 305.17Hz

� With a 10MHz clock and a 10-bit conversion:

– Conversion time = 102.4µs

– Highest output frequency = 4882.81Hz

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High-Accuracy Digital Servo

MCU Outside the Feedback Loop

MCU Filter Voice-Coil Motor

PWM D/A

OutDriver

Position

FeedbackSignal to

Track

AnalogControl Circuit

Calibration

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High-Accuracy Digital Servo

Microcontroller Filter Voice-Coil Motor

PWM D/A

OutDriver

Position FeedbackSignal to Track

MCU Inside the Feedback Loop

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Summary

PWM D/A basics

H8 PWMX design

Registers

Design tips

Applications