Digital Signal Processor (DSP)Digital Signal Processor (DSP)ByBy

Steve D. Wong Steve D. Wong (166/198A)(166/198A)

Ervin Rosario-Figueroa Ervin Rosario-Figueroa (166/198A)(166/198A)

Lana DamLana Dam

Ivan Pierre-LouisIvan Pierre-Louis

Cuong NguyenCuong Nguyen

Spring 2003Spring 2003

San Jose State University

Department of Electrical Engineering

OutlineOutline

IntroductionIntroduction SpecificationSpecification Project PurposeProject Purpose

IntroductionIntroduction Design of a 4-Bit Digital Signal Processor Design of a 4-Bit Digital Signal Processor

(DSP) using CMOS Logic. (DSP) using CMOS Logic. DSP is composed of a Multiplier, D Flip DSP is composed of a Multiplier, D Flip

Flop and a Subtractor. Flop and a Subtractor. Up/Down Counter will be used as a test Up/Down Counter will be used as a test

vector for the system. vector for the system.

SpecificationsSpecifications

Functional SpecificationFunctional Specification 4-Bit Multiplier4-Bit Multiplier 4-Bit Full Subtractor4-Bit Full Subtractor D Flip FlopD Flip Flop 4-Bit Up/Down Counter4-Bit Up/Down Counter

Technical SpecificationsTechnical Specifications Design Wn & Wp = 3 Design Wn & Wp = 3 mm Power <= 0.25WattPower <= 0.25Watt

Clock Frequency << 200 MHzClock Frequency << 200 MHzVVDDDD = 5 Volts = 5 Volts

Schematic (4-Bit Multiplier)Schematic (4-Bit Multiplier)

SchematicLayout

Test Bench (4-Bit Multiplier)Test Bench (4-Bit Multiplier)

Simulation (4-Bit Multiplier)Simulation (4-Bit Multiplier)

Layout (4-Bit Multiplier)Layout (4-Bit Multiplier)

Extract (4-Bit Multiplier)Extract (4-Bit Multiplier)

LVS (4-Bit LVS (4-Bit Multiplier)Multiplier)

Schematic (4-Bit Subtractor)Schematic (4-Bit Subtractor)

Test Bench (4-Bit Subtractor)Test Bench (4-Bit Subtractor)

Simulation (4-Bit Subtractor)Simulation (4-Bit Subtractor)

Layout (4-Bit Subtractor)Layout (4-Bit Subtractor)

Extract (4-Bit Subtractor)Extract (4-Bit Subtractor)

LVS (4-Bit LVS (4-Bit Subtractor)Subtractor)

Schematic (D Flip Flop)Schematic (D Flip Flop)

Test Bench (D Flip-Flop)Test Bench (D Flip-Flop)

Simulation (D Flip Flop)Simulation (D Flip Flop)

Layout (D Flip-Flop)Layout (D Flip-Flop)

Extract (D Flip Flop)Extract (D Flip Flop)

LVS LVS (D Flip Flop)(D Flip Flop)

Schematic (Up/Down Counter)Schematic (Up/Down Counter)

Test Bench (Up/Down Counter)Test Bench (Up/Down Counter)

Simulation (Up/Down Counter)Simulation (Up/Down Counter)

Layout (Up/Down Counter)Layout (Up/Down Counter)

Extract (Up/Down Counter)Extract (Up/Down Counter)

LVS (Up/Down Counter)LVS (Up/Down Counter)