224 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 47, NO. 1, FEBRUARY 1998

Digital Power Metering ManifoldChung-Ping Young and Michael J. Devaney,Member, IEEE

Abstract—An innovative distributed approach to power me-tering on multiple branch circuits supplied from a commondistribution panel is presented. The power-metering manifold’smaster–slave design results in substantial savings in analog cir-cuitry, digital hardware, and communication components whencompared with the conventional single monitor per circuit ap-proach.

Index Terms—Demand, energy, industrial, measurement, me-tering, multicircuit, power.

I. INTRODUCTION

A LTHOUGH microprocessor-based digital power metershave been available for several years [1]–[5], the compar-

atively high cost of the conventional single circuit monitors haslargely confined their use to major feeders and critical loads.This paper introduces an innovative distributed approach tomulticircuit monitoring that results in a substantial reductionin the cost per circuit monitored, without sacrificing the perfor-mance of the single circuit meters. The approach, referred toas the digital power metering manifold, applies to the multiplebranch circuits supplied from a common distribution panel.This manifold system consists of one master monitor and upto 16 slave monitors.

The master monitor is the control center of the manifold. Itacquires all the voltage data, which is common to the loadsfed from the panel, and provides this voltage-point data, aswell as rms summary data, via a high-speed, synchronousserial data link to a number of dependent slave monitors, eachof which monitors multiple branch circuits. This master alsodetermines the supply frequency, provides the synchronoussampling strobe for all analog data acquisition in the manifold,maintains the real time clock, and handles the local display andremote communications tasks for all monitors. In addition,it provides conventional power metering on the panel mainbreaker or feeder.

At each of the slave monitors, the voltage point data fromthe master is used with the time-coincident current data tocompute the real power. Each slave instrument also computesthe rms current values for all the circuits which it monitors. Ituses the rms voltage data, supplied by the master, to determinethe reactive and apparent powers as well as the demand andenergy associated with the slave’s individual branch circuits.

This distributed approach to multicircuit power meteringresults in significant reductions in both hardware requirementsand overall computational burden. Instead of requiring a

Manuscript received June 1, 1997; revised April 1, 1998.The authors are with the Digital Power Instrumentation Group, Department

of Electrical Engineering, University of Missouri, Columbia, MO 65211 USA(e-mail: cp_young@hotmail.com; devaney@ece.missouri.edu).

Publisher Item Identifier S 0018-9456(98)05487-4.

single instrument per three-phase circuit as supported byconventional power monitors, this manifold approach permitseach slave to support power metering for up to two three-phase, four-wire branch circuits, up to four three-phase, three-wire branch circuits or up to eight single-phase circuits. Furthereconomies are achieved by providing a single power supply,single local display and a single isolated external communica-tions interface to the remote host for the entire manifold. Inaddition, the precision voltage analog-conditioning circuitryappears only once—reducing both the component cost as wellas the calibration requirements for the manifold. Similarly, therms voltage computational effort is performed only once, in themaster, rather than being replicated in each monitor—reducingboth effort and code space requirements.

Additional functionality is provided by using the syn-chronous serial communication bus coupling the master toits slaves to convey command and status information. Viathis route, the master can assess the state of circuit breakersassociated with each circuit being monitored in order to detectand report a tripped breaker to the remote host. In a similarmanner, the meter can activate a re-closable breaker to restoreservice to a load. This same communication path permitsthe master to instruct each slave to store its current demandpower in a special “captured demand register,” when themaster updates its peak demand. This permits the remotehost computer to then determine the contribution of each ofthe manifold multiple circuits to the new demand peak. Inaddition, since the multiple slave units monitor only currentsand are coupled to their loads through current transformers,each of the slaves is effectively isolated from the powersystem.

II. POWER METERING ALGORITHMS

The basic idea of power metering has been described inmany papers [2]–[5]. The statistically-based algorithms for thedesign of a digital ac panel meter established for a unipolaranalog-to-digital (A/D) converter with a biased input are asfollows [2].

A. RMS

If sampled data , , , are acquired, therms value of the signal is then given by

(1)

0018–9456/98$10.00 1998 IEEE

YOUNG AND DEVANEY: DIGITAL POWER METERING MANIFOLD 225

where is standard deviation and is the scale factor toconvert the computation result of a set of digital samples tothe signal’s rms value. The factors and for calculatingrms voltage and current, respectively, are

(2)

where and are maximum rms ratings asso-ciated with the voltage or current measurement system andis the number of bits of the A/D converter.

B. Power

If samples of voltage signals , , , , andcurrent signals , , , are acquired at the samesampling instants, the real power,, is given as

(3)

where the terms in parenthesis represent the mean of theproducts and the product of the means of the voltage andcurrent samples. The apparent power,, is shown as

(4)

III. H ARDWARE ARCHITECTURE

The power metering manifold consists of one master mon-itor and up to 16 slave monitors. The Motorola MC68HC16microcontroller unit (MCU), performing calculations, controlsand communications, is the core component of each masterand slave, while analog signal conditioning circuitry interfacesall ac signals, from the monitored circuits, with the inputs ofthe A/D converter module in each MCU. The analog signalconditioning circuits are different in the master and slaves.The master employs the same module as a conventional powermeter, which consists of three voltage dividers and four currenttransformers, to condition both voltage and current signals ofa three-phase branch circuit [2]–[5]. However, in the slavemonitors, the voltage conditioning circuits are removed andfour identical current conditioning circuits are added. Thus,eight current conditioning circuits are available in each slave.

Fig. 1 depicts the functional block diagram of the powermetering manifold, which involves a master monitor connectedwith multiple slave monitors via a synchronous serial commu-nication bus, i.e., the queued serial peripheral interface (QSPI)bus of the HC16 [6]. The QSPI is a full-duplex, synchronousserial interface for communicating with peripherals and otherMCU’s. A serial clock signal is generated on the line SCK, bythe master, to synchronize communications between the masterand slaves. All the slaves are always selected by assertingtheir slave select (SS) pins, as both voltage related data andcommands from the master are broadcast simultaneously to allslaves on the master-out–slave-in (MOSI) line. The master canreceive sample data on current or power parameters from the

Fig. 1. Digital power metering manifold block diagram.

designated slave on the master-in–slave-out (MISO) line, whena single slave monitor is requested to report its branch circuitstatus. A multiplexer decodes the master’s four peripheralchip-select (PCS[ ]) pins, so that the selected slave reportsto the master.

The slaves receive all voltage related data as well as timingand synchronization signals from the master. The timing con-trol signals are generated from the output compare (OC[])pins of the general purpose timer (GPT) module [6] of themaster and fed to the slaves to enable both their sample-and-hold (S/H) circuitry and hardware interrupts. Calculating thereal power in the slave presents a synchronization challenge,namely that is received from the master and multiplied bythe obtained locally from the slave. Registration of voltagedata from the master with the corresponding time coincidentcurrent data from the slave is critical as any skew in thisregistration will result in an erroneous and artificial shift inthe power factor. It is for this reason that the master controlsthe synchronous sampling by simultaneously strobing all S/Hcircuits. The sample strobe is generated, in response to thefrequency of the system voltage, as measured by the master,on all input channels for the entire manifold. The OC2 pin ofthe master’s GPT is configured for sending the S/H strobe tothe master and all slaves to maintain synchronization of allvoltage and current point data acquisition. The sampling rateis selected to be 64 points per fundamental cycle to monitor upto the thirty-first harmonic. This rate simplifies the firmwareprogramming and permits the manifold to reach zero-blind-

226 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 47, NO. 1, FEBRUARY 1998

time metering, which monitors every, sample pair duringeach power cycle. The OC3 pin of the master is connectedto the interrupt request pin (IRQ6) of the slaves to providea hardware interrupt to synchronize the point data processing.Moreover, the synchronization of the 64-cycle metering updateperiod of the slaves is maintained by a registration pulse frommaster’s OC4 line.

The power metering manifold supports both three-wire andfour-wire, three-phase power system metering connections aswell as multiple single phase circuits. In three-wire mode, allslaves operate in three-phase three-wire and the line-to-linevoltages are broadcast on the synchronous serial bus. PhasesA and C are metered and phase B is derived, so each slavecan monitor up to four three-phase three-wire branch circuits.A motor control center is a typical application for this case.In four-wire mode, the slaves can be either three-phase, four-wire or single phase or both and the line-to-neutral voltages arebroadcast. Each slave can monitor two three-phase, four-wirebranch circuits with metered neutrals or up to eight single-phase circuits. Fig. 2(a) and (b) show different modes for thethree-phase power system wiring connections of the slave.

IV. SOFTWARE DESIGN

The firmware of the master and slave monitors, as pro-grammed in both assembly and C languages, is developedin the same basic software structure, but some tasks aretreated differently, by virtue of the difference in their analogsignal conditioning circuitry. The zero-blind-time meteringrequirement mandates that the fundamental software structure,including the control of some MCU modules, digital signalprocessing, and the integer calculations, is accomplished inassembly language to provide the fastest throughput. On theother hand, the C language is employed in calculating allprecise floating point power parameters at the end of eachmetering update cycle, i.e., 64 fundamental cycles.

Fig. 3 shows the general firmware flow of the power meter-ing manifold. Each program execution of the master and slavestarts from system initialization and then enters an infinitemonitor loop. The discrete Fourier transform calculationsand power parameter computations are implemented at thedesignated time slot during each metering update cycle.

The master also estimates the frequency and determinesthe new sampling period to maintain synchronous timingcontrol of the manifold. Both Fourier and zero (mean) crossingestimation strategies were evaluated. A modified zero crossingapproach was selected because it was substantially morerobust when tracking off-nominal frequency excursions. Thefrequency estimation is performed by computing the reciprocalof the average period, which is the total duration between thestarting and ending positive-going mean crossing point, fromthe first cycle until the end of the sixty-third cycle, divided bythe number of elapsed power cycles, while the floating pointfrequency update computation is launched at the beginning ofthe sixty-fourth cycle during each metering update cycle. Asliding 16-point filter is employed to avoid noise and spikes,which may result in multiple zero-crossings. The tick valuein the master’s output compare register, which corresponds to

(a)

(b)

Fig. 2. System wiring connection of slave monitor: (a) quad three-wireconnection and (b) dual four-wire connection.

the sampling interval, is derived from the estimated frequency.This fixed value is revised before the beginning of the nextmetering update cycle and is then used for the next 64 powercycles.

An AD PROCESS interrupt service routine (ISR) is invokedby both the master and slave to deal with the point-dataprocessing. The master’s routine starts when it has an outputcompare match in the GPT module. However, there is no GPTfunction in the slaves, as the master controls the timing. TheAD PROCESS routine of the slave is invoked by the hardwareinterrupt request, IRQ6, which is fed from the master’s OC3

YOUNG AND DEVANEY: DIGITAL POWER METERING MANIFOLD 227

(a)

(b)

Fig. 3. Digital power metering manifold software structure: (a) master and(b) slave.

line. Both the master and slave are designed to be interruptedsimultaneously by the GPT and IRQ6, respectively, at eachof the 64 points-per-cycle sampling rate. This ISR stores A/Dresults and enables the next A/D conversion and the QSPIcommunication. It also accumulates the cycle running sums atthe end of each power system cycle. The master acquires thevoltage sample data, stores it in the transmitting buffer, andbroadcasts it every four sampling periods to all slaves.

The QSPIROUTINE ISR of each master and slave isinvoked when the QSPI is completed, so that the received datais restored in the buffer for command interpreting or powerparameter computation.

V. EVALUATION

The master monitor functions as an independent powermeter and its accuracy has been evaluated to within 0.1% forrms voltage and current and 0.2% for power by comparingwith the readings of a Square D PowerLogic Industrial PowerMeter. With corresponding master voltage and slave currentdata in temporal registration, the accuracy of the powermetering manifold depends solely on the precision of themaster and slave A/D converters and the stability of theiranalog conditioning circuits. Consequently, the manifold’s

Fig. 4. Percentage relative error of real power, apparent power and powerfactor with respect to full scale (nominal) power, slave versus master.

relative accuracy is evaluated by comparing the slave readingsto those of the master on the same circuit.

From the software viewpoint, the acquired power parametersfor the master and slaves on the same load are equal. Infact, the relative errors come from the current signal condi-tioning, calibration and quantization of the actual hardwarecomponents. Therefore, the rms current, real power, apparentpower and power factor, etc., which are partially or totallyderived from the current samples are examined for accuracy.From (4), relative error of rms current will be equal to thatof apparent power, since the master and slaves hold identicalrms voltages. Fig. 4 depicts the percentage relative error ofreal power, apparent power, and power factor of the slaverelative to the master in the three-phase, four-wire connectionwith a resistive load. It shows that the relative errors of thereal and apparent powers are both less than 0.025% when theload is over 50% nominal power, and the power factor errorsalways stay close to zero. In case that the relative error ofthe power factor approaches zero, the relative errors of realpower and apparent power are nearly identical. The relativeerror of power factor, as demonstrated in Fig. 4, is lower than0.0003% when over 50% load with each power factor betterthan 0.003% when compared with the Industrial Power Meter.

VI. CONCLUSIONS

A prototype manifold metering system has been developedaround multiple Motorola MC68HC16 microcontroller-basedmetering platforms. This results in the reduction in totalnumber of power monitors in the metering manifold by factorsof two to four for three-phase circuits when compared tothat in the conventional single monitor per circuit approach.Significant economy is also achieved as external communi-cation interface, local display, power supply, the potentialtransformers, and voltage conditioning circuits are requiredonly once for the manifold. This not only cuts cost butdecreases the number of precision components, calibration andcomputation for the voltage conditioning circuitry. Accuracycan be improved by increasing the precision of the A/Dconverters and harmonic resolution enhanced by doubling thesample rate to 128 points per cycle.

228 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 47, NO. 1, FEBRUARY 1998

REFERENCES

[1] J. A. Asumadu, M. J. Devaney, L. Wallis, and J. Bond, “Industrial powermeasurement and control design,” inConf. Rec. IEEE IAS Annu. Meet.,Oct. 1992, pp. 1777–1781.

[2] J. A. Asumadu and M. J. Devaney, “Algorithm for the design of a lowcost digital ac panel meter,” inProc. IEEE IMTC/94,May 1994, pp.1132–1135.

[3] A. C. Corney and R. T. Pullman, “Digital sampling laboratory wattmeter,” IEEE Trans. Instrum. Meas.,vol. 36, pp. 54–59, Feb. 1987.

[4] J. J. Hill and W. E. Alderson, “Design of a microprocessor-based digitalwatt meter,”IEEE Trans. Ind. Electron. Contr. Instrum.,vol. 28, no. 3,pp. 180–184, 1981.

[5] R. S. Turgel, “Digital watt meter using a sampling method,”IEEE Trans.Instrum. Meas.,vol. IM-23, pp. 337–341, Dec. 1974.

[6] Motorola Inc., M68HC16 Family MC68HC16Z1 User’s Manual,Mo-torola Literature Distribution Center, 1992.

Chung-Ping Young was born in Taipei, Taiwan,R.O.C. He received the B.S. degree in electronicengineering from Chung-Yuan Christian University,Taiwan, in 1985, and the M.S. and Ph.D. degreesin electrical engineering from the University ofMissouri, Columbia, in 1994 and 1997, respectively.

He has been a Research Assistant in power me-tering and power quality measurement at Universityof Missouri, Columbia, since 1994.

Michael J. Devaney(S’60–M’64), for a photograph and biography, see thisissue, p. 188.