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The King Abdullah II School for Electrical Engineering

Electronics Engineering Department

Digital Electronics Lab. (EE21339)

Prepared By: Eng. Eyad Al-Kouz

February, 2011

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There is a quotation that I have seen, which I

am told was originally stated by Confucius. I present it here as a very practical statement on how the human mind approaches the learning process:

I hear, and I forget. I see, and I remember. I do, and I understand.

One of the best ways to understand something is to get your hands on it and actually experiment with it. In electronics, this means putting small circuits together, powering them up, and seeing first hand what they do.

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Digital Electronics Lab. (EE 21339) Table of Contents:

• Experiments to be covered:

Exp. No.

Experiment Title

1.

The Transistor Switch

2.

The TTL Logic Characteristics

3.

The NMOS Switch

4.

The CMOS Logic Characteristics

5.

Interfacing TTL and CMOS Gates

6.

The 555 Timer

7.

Triggering Circuits

8.

A/D and D/A Converters

9.

Oscillators made from Inverters

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Experiment (1):

The Transistor Switch

1.1 Reference Microelectronic Circuits by Sidra & Smith, chapter 14. 1.2 Objectives To study the characteristics of BJT as a switch and as a basic logic inverter. Circuits for a logic gate is considered. 1.3 Discussion A bipolar junction transistor (BJT) may be made to act like a simple ON/OFF switch. In such an application, the transistor is operated in the saturation region to simulate the ON (Closed) switch condition and in the cutoff region to simulate the OFF (Open) switch condition. The input applied to the base of the transistor either turns it ON (Saturates) or OFF (Cutoff) as shown in figure 1.1. When the transistor switch is ON, VCE -VCE (Sat); and when the transistor is OFF, VCE = VCC. One common use of a transistor switch is the inverter circuit. Notice that for a logic "0" input the transistor will be OFF and the output will be equal to VCC; a logic "1 ". On the other hand a logic "1" at the input saturates the transistor and results in an output voltage VCE (Sat) of approximately 0.2 -0.3 Volts; a logic "0". Figure 1.2 shows a two-input NOR gate of the RTL family. It can be easily shown that if one of the inputs is high (logic "1 ") then the corresponding switch will be ON and the output is low (logic "0"). On the other hand, a high at the output needs both switches to be OFF. Clearly, this is obtained if both inputs are simultaneously low. Figure 1.3 shows a more complex circuit for a TTL inverter.

Figure 1.1

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Figure 1.2

Figure 1.3 5.4 Procedure

1. Connect the transistor switch as shown in figure 1.1. 2. Apply 0 V (ground) at the input Vi. Measure and record the voltage at the output Vo. 3. Apply DC 5 V at the input Vi. Measure and record the voltage at the output Vo.

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4. Apply a 5-Vpp 1 kHz sine wave at the input and use the oscilloscope to observe and record the input as well as the output voltage waveforms. 5. Increase the input frequency slowly and observe its effect on the output waveform. 6. Use the oscilloscope (in the X-Y mode) to plot the transfer characteristics of the inverter in figure 1.1. Arrange that Vo is displayed vertically and Vi is displayed horizontally on the screen. Use a triangular wave input of 5V p-p at 1 kHz applied to the input. 7. Connect the RTL gate as shown in figure 1.2 and carry out an experiment to verify the truth table of the RTL gate. 8. Connect the circuit shown in figure 1.3, and carry out the steps from 1 to 6. 1.5 Questions

1. Find the noise margin Δ0 and Δ1 from the transfer characteristics of the RTL inverter shown in figure 1.1. 2. Find the noise margin Δ0 and Δ1 from the transfer characteristics of the TTL inverter shown in figure 5.3.

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Experiment (2):

The TTL Logic Characteristics 2.1 Reference Microelectronic Circuits by Sidra & Smith, chapter 14. 2.2 Objectives To examine the input/output characteristics, voltage transfer characteristics, fan-out, propagation delay time of a TTL gate. 2.3 Discussion

The transistor-transistor logic (TTL) is the most widely used logic family. The TTL electrical specifications are usually of interest to the designer of a digital system. A brief

below. Input/output characteristics logic gatecharacteristics is given discussion of these specification typically include the following maximum and minimum voltage levels:

VIH = Minimum gate input voltage which will reliably be recognized as logic 1 (high). VIL = Maximum gate input voltage which will reliably be recognized as logic 0 (low). VOH = Minimum voltage at the gate output when it is a logic 1 (high). VOL = Maximum voltage at the gate output when it is a logic 0 (low).

The manufacturer of the gate guarantees that when the input signal Vi is less than VIL,

the output Vo will be greater than VOH under the worst-case conditions. He also guarantees that when Vi exceeds VIH, the output will be less than VOL under the worst-case conditions. The voltages VIL VIH, VOL and VOH are specified for input and output current levels not to exceed IIL, IIH, IOL and IOH respectively. The low-level noise margin NML is defined as:

OLILL VVNM −=

The high-level noise margin NMH is defined as:

IHOHH VVNM −=

* Voltage transfer characteristics: One of the main properties of any digital circuit is the voltage transfer Characteristics which relates the output voltage to the input voltage under static conditions. The three regions of operation for the output transistor (cutoff, active and saturation) can be easily identified on the curve. The logic level, VOL, VOH, VIL. and VIH can be found from these characteristics.

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* Fan-out: In practice, the output of one gate is often connected to the input of one or more gates. The fan-out describes the maximum number of load gates of similar design as the drive gate, that can be connected to the output of a logic, that is, the driver gate. * Propagation delay time: These times are measured between two reference levels on the input and output voltage waveforms as shown in figure 6.1. A turn-on delay time (tPHL) is measured as the output changing from a high voltage level to a low voltage level. The turn-off delay time (tPLH) is measured as the output changing from low level to a high level. The average propagation delay time is defined as:

2LHHL tptptp +

=

Procedure 2.4

1. Use the oscilloscope (in the X-Y mode) to plot the transfer characteristics of the 7404 TTL inverter. Arrange that Vo is displayed horizontally on the screen. Use a triangular wave input of 5 Vp-p at 1kHz (TTL compatible). 2. Label the regions of operation (cutoff, active, saturation) on the transfer characteristics. Also determine VIL, VIH, VOL and VOH from the curve. 3. Connect the circuit as shown in figure 2.2. Measure the voltage at the input of the inverter. Using your measured voltage and Ohm's law, calculate the current in the resistor. This current is the input high current IIH. 4. Measure the output voltage of the gate. Since the input is high, the output will be low. This voltage is called VOL. 5. Connect the circuit as shown in figure 2.3. Measure VIL. and VOH. Calculate IIL. Calculate IIL and IOH applying Ohm's law. 6. Compare your measured values with values in data sheet and calculate the low and high level noise margins. 7. The ring oscillator circuit shown in figure 2.4 is often used to measure the average propagation delay time of a logic gate. The period of oscillation frequency is equivalent to the total propagation delay time of the five gates, which make up the ring. The average propagation delay time is therefore the period of the oscillation divided by twice the number of gates within the ring. 8. Connect the circuit as shown in figure 2.5. Measure the output voltage Vo when the fan-out is 1, 2, 3, 4 and 5 gates. Using these measurement determine the maximum number of gates which can be connected at the output of the driver gate such that Vo ≥VIH and Vo ≤ VIL.

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Figure 2.1

Figure 2.2

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Figure 2.3

Figure 2.4

Figure 2.5

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Experiment (3):

The NMOS Switch 3.1 Reference Microelectronic Circuits by Sidra & Smith, chapter 13. 3.2 Objectives

To study the characteristics of MOSFET as a switch and as a basic logic inverter. Circuits for a logic gate is considered. 3.3 Discussion

The Complementary MOSFET (CMOS) is rapidly becoming the most favored because of its lower power dissipation, shorter propagation delay, and shorter rise and fall times. .The input applied to the Gate of the transistor either turns it ON (Saturates) or OFF (Cutoff) as shown in figure 3.1.

An inverter is built from NMOS transistor depends on the load of the basic switch, i.e., a resistor, an enhancement-type load, or a depletion-type load. Each has advantages and disadvantages. Figure 3.1 shows two types: A depletion-type load and a resistor.

Figure 3.2 shows a two-input NOR gate of the NMOS depletion-type family. It can be easily shown that if one of the inputs is high (logic "1 ") then the corresponding switch will be ON and the output is low (logic "0"). On the other hand, a high at the output needs both switches to be OFF. Clearly, this is obtained if both inputs are simultaneously low. Figure 3.3 shows another gate that you will proceed in defining it in the laboratory. 3.4 Procedure

1. Connect the transistor switch as shown in figure 3.1 (a). 2. Apply 0 V (ground) at the input Vi. Measure and record the voltage at the output Vo. 3. Apply DC 5 V at the input Vi. Measure and record the voltage at the output Vo. 4. Apply a 5 Vp-p 1 kHz triangular wave at the input and use the oscilloscope to observe and record the input as well as the output voltage waveforms. 5. Increase the input frequency slowly and observe its effect on the output waveform. 6. Use the oscilloscope (in the X-Y mode) to plot the transfer characteristics of the inverter in figure 3.1 (a). Arrange that Vo is displayed vertically and Vi is displayed horizontally on the screen. Use a triangular wave input of 5V peak- to-peak at 1 kHz applied to the input. 7. Connect the NMOS depletion-type load gate as shown in figure 3.1 (b) and carry out the steps from 1-6. Observe any change happens by changing the load type.

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8. Connect the circuit shown in figure 3.2, and carry out the experiment by building the truth table of the gate, then define the gate. 9. Connect the circuit shown in figure 3.3, and carry out the experiment by building the truth table of the gate, then define the gate.

Figure 3.1 (a) Figure 3.1 (b)

Figure 3.2

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Figure 3.3

3.5 Questions 1. Find the noise margin Δ0 and Δ1 from the transfer characteristics of the inverter shown in figure 3.1 (a). 2. Find the noise margin Δ0 and Δ1 from the transfer characteristics of the inverter shown in figure 3.1 (b). 3. In your analysis compare the results TTL switch and the NMOS depletion-type load in terms of the noise margin and rise and fall times.

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Experiment (4):

The CMOS Logic Characteristics 4.1 Reference Microelectronic Circuits by Sidra & Smith, chapter 13. 4.2 Objectives To examine the input/output characteristics, voltage transfer characteristics, fan-out, and propagation delay time of a CMOS.

4.3 Discussion

The CMOS logic gate is the most widely used logic family because of their low power dissipation. A brief discussion of these characteristics is given below. Input/Output

pecification typically includes the following maximum and gate s ogiccharacteristics lminimum voltage levels:

VIH = Minimum gate input voltage which will reliably be recognized as logic 1 (high). VIL = Maximum gate input voltage which will reliably be recognized as logic 0 (low). VOH = Minimum voltage at the gate output when it is a logic 1 (high). VOL = Maximum voltage at the gate output when it is a logic 0 (low). The manufacturer of the gate guarantees that when the input signal Vi is less than VIL., the output Vo will be greater than VOH under the worst-case conditions. He also guarantees that when Vi exceeds VIH, the output will be less than VOL under the worst-case conditions. The voltages VIL, VIH, VOL and VOH are specified for input and output current levels not to exceed IIL, IIH, IOL and IOH respectively. The low-level noise margin NML is defined as:

OLILL VVNM −=

The high-level noise margin NMH is defined as:

IHOHH VVNM −=

* Voltage transfer characteristics: One of the main properties of any digital circuit is the voltage transfer characteristics which relate the output voltage to the input voltage under static conditions. The three regions of operation for the output transistor (cutoff, active and saturation) can be easily identified on the curve. The logic level, VOL, VOH, VIL and VIH can be found from these characteristics.

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* Fan-out: In practice, the output of one gate is often connected to the input of one or more gates. The fan-out describes the maximum number of load gates of similar design as the drive gate, that can be connected to the output of a logic, that is, the driver gate.

* Propagation delay time: These times are measured between two reference levels on the input and output voltage waveforms as shown in Figure 4.1. A turn-on delay time (tPHL) is measured as the output changing from a high voltage level to a low voltage level. The turn-off delay time (tPLH) is measured as the output changing from low level to a high level. The average propagation delay time is defined as:

2LHHL tptptp +

= 4.4 Procedure 1. Use the oscilloscope (in the X-Y mode) to plot the transfer characteristics of the 4069 CMOS inverter. Arrange that Vo is displayed horizontally on the screen. Use a triangular wave input of 5Vp-p at 1 kHz. 2. Label the regions of operation (cutoff, active, saturation) on the transfer characteristics. Also determine VIL, VIH, VOL and VOH from the curve. 3. Connect the circuit as shown in figure 4.2. Measure the voltage at the input of the inverter. Using your measured voltage and Ohm's law, calculate the current in the resistor. This current is the input high current IIH. 4. Measure the output voltage of the gate. Since the input is high, the output will be low. This voltage is called VOL. 5. Connect the circuit as shown in figure 4.3. Measure VIL and VOH. Calculate IIL and IOH applying Ohm's law. 6. Compare your measured values with values in data sheet and calculate the low and high level noise margins. 7. The ring oscillator circuit shown in figure 4.4 is often used to measure the average propagation delay time of a logic gate. The period of oscillation frequency is equivalent to the total propagation delay time of the five gates, which make up the ring. The average propagation delay time is therefore the period of the oscillation divided by twice the number of gates within the ring. 8. Connect the circuit as shown in figure 4.5. Measure the output voltage Vo when the fan-out is 1, 2, 3, 4 and 5 gates. Using these measurement determine the maximum number of gates which can be connected at the output of the driver gate such that Vo ≥ VIH and Vo ≤ ViL. 9. Make a complete analysis report, in which you state clearly a comparison between CMOS Inverter and TTL inverter characteristics.

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Figure 4.1

Figure 4.2

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Figure 4.3

Figure 4.4

Figure 4.5

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Experiment (5):

Interfacing TTL and CMOS Gates 5.1 Reference Microelectronic Circuits by Sidra & Smith, chapter 13 & 14.

5.2 Objectives To Study the interfacing circuits between TTL and CMOS gates.

5.3 Discussion Interfacing means connecting electrically different circuits and devices. Sometimes, a direct connection is not possible and it is necessary to use an interface between the driver and driven gates. The interface circuit takes the output signal from the driver gate and conditions it so that it satisfies the input requirements of the driven gate. The electrical characteristics of the TTL and CMOS gates must fulfill the following conditions in order to be logically compatible:

)()()()()()()()(

drivenVdriverVdrivenVdriverVdrivenNIdriverIdrivenNIdriverI

ILOL

IHOH

ILOL

IHOH

≤≥≥≥

Where IIL. IIH,.IOH, VIL, VOL, VIH and VOH are taken from the data sheets and N is the number of driven gates. If one or more of the above conditions is not satisfied, an interface circuit is necessary for proper operation. TTL driving CMOS having the same supply voltage: By referring to the data sheets of the TTL and CMOS, it is obvious that condition 3 is not satisfied since VOH (TTL) = 2.4 V is less than VIH (CMOS) = 3.5 V. A solution is presented in figure 5.1 that is to connect the TTL output to +5 V through a pull-up resistor. TTL driving high-voltage CMOS: The interface circuit is called a level translator since it changes the high state logic level from a TTL level to VDD. Figure 5.2 shows one possible solution using discrete transistors for a TTL gate driving a CMOS with a supply voltage VDD.

CMOS driving TTL: In general a typical CMOS output cannot drive a standard TTL load because in the low state the TTL output produces a lmA current that has to flow back through the Ron of the CMOS channel producing an output voltage VOL which exceeds the maximum allowable low-state input voltage of the TTL gate. If the supply voltages for CMOS and TTL are the same, then a noninverting buffer can be used as an interface.

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If the CMOS has a high-voltage power supply, then a level translator can be used as an interface as shown in figure 5.3. CMOS-to- TTL level translators are also available as ICs. The 4049 and 4050 are CMOS devices that can perform high-to- low level translator. Figure 5.4 shows a possible solution using the 4050 ICs.

5.4 Procedure 1. Connect the circuit shown in figure 5.1 without a pull-up resistor R and measure the output voltages Vo1 and Vo2 when Vi is 0-and 5V. 2. Repeat 1 in the presence of the pull-up resistor with R=5k. 3. Connect the circuit shown in figure 5.2, and measure the output voltages Vol, Vo2 and Vo3 when Vi = 0 V and 5 V. 4. Refer to figure 5.2, how many level translators can be connected to the output of the TTL if it can source 400 mA of current before it drops below the VOH of 2.4V. 5. Connect the circuit shown in figure 5.3, and measure the output voltages Vo1, Vo2 and Vo3 when Vi = 0 and 10V. 6. Connect the circuit shown in figure 5.4, and measure the output voltages Vol, Vo2 and Vo3 when Vi = 0 and 10V.

Figure 5.1

Figure 5.2

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Figure 5.3

Figure 5.4

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Experiment (6):

The 555 Timer 6.1 Reference Microelectronic Circuits by Sidra & Smith, chapter 12, sections 12.4, 12.5, 12.6, and 12.7. 6.2 Objectives 1. To become familiar with some of the ac characteristics of the 555 Timer. 2. To examine and measure typical astable multivibrator waveforms generated with a 555 Timer. 3. To show how a 555 Timer may be used as a voltage controlled oscillator. 6.3 Discussion

The 555 timer integrated circuit is a very extensively used product. Whole books have been written around this one chip and its many applications. It is not appropriate to attempt a total explanation of the operation of this circuit in these pages. Only a brief synopsis is presented.

The 555 timer contains two comparator circuits, a flip-flop stage, a transistor, and an output stage. There is an internal voltage divider consisting of three 5kΩ resistance which set the triggering levels of the two comparator circuits. The triggering voltages are always a function of the power supply voltage, either 1/3 of Vcc or 2/3 of Vcc. An external RC timing circuit is applied to the comparator terminals. When the charging capacitor voltage reaches the 2/3 Vcc level, the flip-flop resets and its output level goes close to 0V. When the discharging capacitor voltage reaches the 1/3 Vcc level, the flip-flop sets and its output level goes close to Vcc.

With a power supply of 15 V, typical waveforms would have the output switching between approximately 0 V and 15 V, while the capacitor waveform would be switching between 5 V and 10 V, which are the 1/3 Vcc and 2/3 Vcc levels.

Usually, it is fairly difficult to obtain square waves with 50% duty cycles. A control voltage terminal may be used to apply a dc voltage which will control the oscillator frequency. 6.4 Procedure * 555 Astable Multivibrator 1. Connect the circuit of figure 6.1 using an LM555 timer chip, 1kΩ for R1 and R2, and 0.1μF for the timing capacitor.

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Figure 6.1: Astable Multivibrator Circuit 2. Use a dual trace scope to view the output waveform and the waveform across the timing capacitor in proper phase with each other. Sketch both of these waveforms together in table 6.1. 3. On the output waveform, measure the on time when the output is high, measure the off time when the output is low, and measure the frequency. Record these measurements in Table 6.1. 4. Change both R1 and R2 to 10kΩ and repeat steps 2 and 3. 5. Change both R1 and R2 to 100kΩ and repeat steps 2 and 3.

Table 6.1: Astable Multivibrator Measurements

Waveforms Measurements Step

2, 3

4

5

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* 50% Duty Cycle Multivibrator 6. Connect the circuit of figure 6.2 using nit LM555 timer chip, 50kΩ for R1 (two 100kΩ in parallel), 22kΩ for R2, and 0.01μF for the timing capacitor. Note that the connections around the resistors are different from the previous circuit.

Figure 6.2: 50% Duty Cycle Circuit 7. Use a dual trace scope to view the output waveform and the waveform across the timing capacitor in proper phase with each other. Sketch both of these waveforms together in table 6.2. 8. On the output waveform, measure the on time when the output is high, measure the off time when the output is low, calculate duty cycle and measure the frequency. Record these measurements in table 6.2. 9. Change R1to 100kΩ and R2 to 27kΩ and repeat steps 7 and 8.

Table 6.2: 50% Duty cycle Measurements

Waveforms Measurements Step

7, 8

9

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* Voltage Controlled Oscillator 10. Connect the circuit of figure 6.3 using an LMS55 timer chip, 10kΩ for R1and R2,

and 0.1μF for the timing capacitor. Set the control voltage to 5.0 V initially. 11. Measure the frequency of the output waveform and record it in the table 6.3. 12. Adjust the control voltage to 10 V and repeat step 11. 13. Adjust the control voltage to 15 V and repeat step 11.

Figure 6.3: Voltage Controlled Oscillator Circuit

Table 6.3: Oscillator frequency Measurements

15 V

10 V

5.0 V

Control Voltage

Frequency

uestionsQ.5 6 1. The frequency of the astable is given by the formula below. "C" refers to the timing capacitor. Calculate the theoretical frequencies and compare to those measured in table 6.1.

( )CRRf

22144.1

+=

2. The duty cycle of the astable is given by the formula below. Calculate the theoretical duty cycles and compare to those which you can calculate from measurements in table 6.1. ( )

( ) %100221

21∗

++

=RR

RRDC 3. Comment on your measurements of duty cycle in table 6.2. 4. Refer to table 6.3. Calculate the change of frequency per volt of change in control voltage.

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Experiment (7):

Triggering Circuits 7.1 Reference Microelectronics Circuits by Sidra & Smith, chapter 12, sections 12.5-12.7. 7.2 Objective

1. To study the operation of a simple op-amp Schmitt trigger circuit. 2. To observe an "input versus output" oscilloscope plot for an op-amp Schmitt trigger circuit. 3. To examine the operation of a zero crossing op-amp detector circuit. 7.3 Discussion A typical Schmitt trigger circuit is shown in figure 7.1. If the inputs were reversed in polarity, it would seem the same as a non-inverting op-amp with the usual negative feedback. As the circuit is, however, the feedback is positive instead of negative, so the op-amp is unstable. This means it will oscillate, in this case, switching back and forth between the positive and negative rails. The voltages at which the circuit switches are of interest to anyone studying this circuit.

Figure 7.1: Schmitt Trigger Op-Amp Circuit

To understand the switching voltages, consider the voltages shown on figure 7.2 (a). Assume the circuit is powered by ±15 V split supply. The input could be a l0 Vp-p sine wave at the instant shown, the sine wave could be at 1.00 V, with the polarity as shown in figure 7.2 (a). Assuming the output was at the positive 15 V rail, voltage divider action of R1 and R2 (see figure 3.1) would produce a feedback voltage of 2.63 V across R1 in the polarity shown in figure 7.2 (a). With the input and feedback voltages as shown, the op-

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amp input voltage would be 1.63V with the polarity shown in figure 7.2 (a). The 1.63 V would be multiplied by the open loop gain of the op-amp, which might easily be 100,000 or more. This would be (1.63)*(100,000) and the output of the op amp would be held at the positive rail, or + 15 V. Assume now that the input rises to exactly 2.63 V. Refer to the voltages given in figure 7.2 (b). From top to bottom, these are the op-amp input, the generator input, and the feedback voltage. These voltages now replace the three voltages shown on the schematic. If the input and feedback voltages were both 2.63V, the op-amp input would be 0.00 V. But when the op-amp input becomes 0.00 V, the output would also be 0.00 V, and therefore the feedback voltage would drop to 0.00V as shown in the voltages of figure 7.2 (c). If the feedback voltage was 0.00V, and the generator voltage was 2.63 V, the op-amp input voltage would become 2.63 V. This would mean that the output voltage would be (-2.63)*(100,000) and the output of the op-amp would be held at the negative rail, or -15V. This would cause the feedback voltage to become 2.63 V, with the polarity as shown in figure 7.2 (d). Now the op-amp input voltage would become 5.26 V, which would continue to hold the output at -15 V.

The student may wish to use separate diagrams to show the above changes as they occur. A blackboard is ideal since the changes may be made easily, as they happen. Understanding the Schmitt Trigger action is not really difficult, describing it is quite another matter as the preceding paragraph shows.

Figure 7.2: Schmitt Trigger Switching Voltages

The output will continue to stay at -15 V until the generator voltage drops to -2.63 V, at which point one can work through a similar scenario to show the output will change as expected.

The switching points of a Schmitt trigger circuit are often shown on an "input versus output" plot. For this circuit, such a plot is illustrated in figure 7.3. This may be viewed on most oscilloscopes quit easily. The triggering levels of a Schmitt trigger may be altered by the addition of reference voltages into the circuit.

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Figure 7.3: Schmitt Trigger Vi verses Vo plot

The zero crossing detector shown in figure 7.4 is basically a comparator circuit, except that an RC shaping circuit has been added to the output.

Figure 7.4: Zero Crossing Detector This circuit would normally have an output of +V whenever the input is positive, an -V whenever the input is negative. The addition of the RC circuit causes the output square wave to change to a spike corresponding to each time the input waveform crosses zero volts.

7.4 Procedure * Schmitt Trigger Circuit

1. Connect the circuit of Figure 7.5. Connect a 10 Vp-p 1kHz sine wave to the input of the circuit.

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Figure 7.5: Schmitt Trigger Circuit

2. Measure and record in table 7.1 the input and output waveforms of the circuit of figure 7.5, drawn in proper phase with each other. 3. If possible, set your scope for viewing an X-Y waveform. Connect the X input of the scope to the input of the circuit, and connect the Y input of the scope to the output of the circuit. 4. After making sure that the X-Y waveform is centered vertically and horizontally, measure and record the waveform in table 7.1.

Table 7.1: Schmitt Trigger Measurements

Waveforms Measurements Step

2

4

* Schmitt Trigger Circuit With Reference 5. Modify the circuit of figure 3.5 into that shown in figure 7.6. Use the same 10 Vp-p 1 kHz sine wave to the input of the circuit.

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Figure 7.6: Schmitt Trigger with reference

6. Measure and record in table 7.2 the input and output waveforms of the circuit of figure 7.6, drawn in proper phase with each other. 7. If possible, set your scope for viewing an X-Y waveform. Connect the X input of the scope to the input of the circuit, and connect the Y input of the scope to the output of the circuit. 8. After making sure that the X-Y waveform is centered vertically and horizontally, measure and record the waveform in table 7.2.

Table 7.2: Schmitt Trigger with reference Measurements

Waveforms Measurements Step

6

8

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* Zero Crossing Detector 9. Connect the circuit of figure 7.7. Connect a 3 Vp-p 100Hz sine wave to the input of the circuit.

Figure 7.7: Zero Crossing Detector Circuit

10. Measure and record in table 7.3 the input and Pin 6 waveforms for the circuit of figure 7.7, drawn in proper phase with each other. 11. Measure and record in table 7.3 the input and output waveforms for the circuit of figure 7.7, drawn in proper phase with each other.

Table 7.3: Zero Crossing Detector Measurements

Waveforms Measurements Step

10

11

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7.5 Questions 1. Refer to table 7.1. Did the waveform of step 2 appear to switch at approximately +2.6 V and -2.6 V as expected? 2. Refer to table 7.1. Did the waveform of step 4 appear to switch at approximately +2.6 V and -2.6 V as expected? 3. Refer to table 7.2. How did the addition of the 1.5 V battery affect the switching voltages? 4. Refer to table 7.3. Explain how the RC circuit changes the square wave into a series of positive and negative spikes.

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Experiment (8):

A/D and D/A Converters 8.1 Reference Microelectronics Circuits by Sidra & Smith, chapter 10, sections 10-11.

8.2 Objectives

1. To demonstrate the concept of Analog-to-Digital Converter (ADC) 2. To demonstrate the concept of Digital-la-Analog Converter (DAC)

8.3 Discussion Most physical variables are analog in nature. Quantities such as temperature, pressure and weight can have an infinite number or values. Converting an analog value to a digital equivalent (binary number) is called digitizing the value. Such operation is performed by an Analog-to-Digital Converter (ADC). After processing the digital data, it is often necessary to convert the results of such operation back to analog values; this function is performed by a Digital-to-Analog converter (DAC).

A DAC having a 4-bit input produces only 24 = 16 different analog output voltages, corresponding to the 16 different values that can be represented by the 4-bit input, The output of the converter is, therefore, not truly analog, The greater the number of input bits, the greater the number tile output values and the closer the output resembles a true analog quantity. Resolution is a measure of this property.

The above can also be said about the ADC except that the output will determine its resolution instead of the input.

8.4 Procedure * R-2R Ladder DAC: Figure 8.1 illustrates a simplified approach to DAC (4-bit). The buffer op-amp is used to provide a high impedance to the R-2R ladder. 1. Find analytically the output (Vo) in terms of D0, D1, D2 and D3. 2. Design a 4-bil, R-2R ladder DAC whose full-scale output voltage is -10 V. Logical levels are 1 (+5 V) and 0 (0 V). 3. Find the output for the following binary combination 1010, 1110, 0001, 0101, and 1100.

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Figure 8.1: R-2R Ladder DAC

* A Simplified version of A/D Converter There are a number of methods to perform analog-to-digital conversion. The fastest is the flash and the modified flash because the signal is processed in a parallel fashion. The successive approximation is widely used but it is not faster than the flash. Figure 8.2 shows a simplified version of the flash-type ADC.

Figure 8.2: A simplified version of the Flash-type ADC

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A reference voltage is connected to a voltage divider that divide into 3 (2n- 1) equal increment levels. Each level is compared to the analog input by a voltage comparator. All comparator outputs are connected to a priority encoder. A priority encoder produces a binary output corresponding to the input having the highest priority. 4. Use A dc voltage of a max of 5 V, a reference voltage of 5 V and a resistance of 10kΩ, tabulate the three different outputs of the comparators that corresponds to a certain input. 5. Design an encoder to translate the output of the comparators into its binary outputs (use logic gates in your design).

Questions.5 8

1. For the DAC circuit in figure 8.1, find the resolution and the increment between the successive output voltages given the full-scale range to be 10. 2. For the DAC circuit in figure 8.2, find the resolution and the increment between the

successive output voltages given the full-scale range to be 10. Then compare your result with question 1.

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Experiment (9):

Oscillators made from Inverters 9.1 Reference Microelectronic Circuits by Sidra & Smith, chapter 13. 9.2 Objectives To design an oscillator from the TTL and CMOS inverters and to be familiar with its characteristics. 9.3 Discussion

A simple circuit that uses two TTL inverters to produce an approximate square wave at Q1 and Q2 as shown in figure 9.1. The frequency of oscillation is related to R and C by the following relationship:

RCf

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= The value of R should not exceed 500Ω. for standard TTL. The oscillator shown in figure 9.2 can be modified so that the oscillator can be controlled by a separate logic control input. This control input will determine whether or not oscillation will occur. Figure 9.4 shows a popular CMOS astable multivibrator built from NOR gates. We can easily prove using the specified waveforms that the frequency of oscillation is as follows:

CRT 4.1= Figure 9.5 shows a simple and popular monostable multivibrator. Consider Ron of the gate is negligible, we can calculate the frequency of oscillation as follows:

⎥⎦⎤

⎢⎣⎡

−=

thdd

dd

VVVCRT ln

9.4 Procedure

1. Connect the circuit shown in figure 9.1 using the Hex inverter chip. Then observe the output at Q and Q' and measure the frequency of oscillation and compare it to the calculated value. Also find experimentally the maximum and minimum frequencies which we can get from this oscillator. (Hint, change the value of the capacitors). 2. Connect the circuit shown in figure 9.2. Apply a square-wave (TTL compatible) at input x with 500Hz. Observe the input and output then repeat for other frequencies. 3. If the pulses at the output of the oscillators are not pure square waves, you can use a Schmitt trigger as a wave shaper as shown in figure 9.3.

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4. Show how we can use the controlled oscillator such that the output will be on for 7 pulses and off for 3 pulses by controlling the frequency and duty cycle of the input signal. 5. Connect the circuit shown in figure 9.4 using the CMOS NOR gate and accurately plot the outputs Vol, Vo2, and Vi. Also measure the frequency of oscillation. Change the value of C and note the change in the frequency of oscillation, compare with the calculated value. 6. Insert a resistor 10*R in the connection between the common node of C and R and the input node Gl and then accurately plot the voltage at node Vo1, Vo2 and Vi .Also measure the frequency of oscillation and compare it to the one measured in (5). 7. Connect the circuit shown in figure 9.5 using the CMOS NOR gate insert a pulse signal of duration equals to τ such that τ > (tpl + tp2) and accurately plot the outputs Vol and Vo2. Also measure the frequency of oscillation. Change the value of C and note the change in the frequency of oscillation, compare with the calculated value. 8. What the value of R should be if the frequency is set to 1Hz and C=1μF.

Figure 9.1

Figure 9.2 Figure 9.3

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Figure 9.4

Figure 9.5