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Development of GEM trigger electronics for the J-PARC E16 experiment

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2015 J. Phys.: Conf. Ser. 664 082043

(http://iopscience.iop.org/1742-6596/664/8/082043)

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Development of GEM trigger electronics for the

J-PARC E16 experiment

Y. Obara1, E. Hamada2, M. Ikeno2, D. Kawama3, Y. Morino2, W.Nakai1,3, K. Ozawa2, H. Sendai2 , T. N. Takahashi4, M. M. Tanaka2,T. Uchida2, S. Yokkaichi31Department of Physics, University of Tokyo, Bunkyo-ku, Tokyo, 113-0033, Japan2Institute of Particle and Nuclear Studies (IPNS), High Energy Accelerator ResearchOrganization (KEK), Tsukuba, Ibaraki, 305-0801, Japan3RIKEN Nishina Center, Wako, Saitama, 351-0198,Japan4Research Center for Nuclear Physics (RCNP), Ibaraki, Osaka,567-0047, Japan

E-mail: yobara@post.kek.jp

Abstract. At the J-PARC E16 experiment[1], we measure mass spectra of vector mesons innuclei from the e+e− decay channel with high precision and high statistics. We have developedthe trigger system consisting of newly developed ASD ASICs which can extract signals fromthe GEM foil used as a cathode plane of the induction gap in a GEM chamber and digitalelectronics using FPGAs which processes binary signals from the ASIC.

1. IntroductionThe purpose of the J-PARC E16 experiment is to investigate an origin of hadron mass and thechiral symmetry restoration in nuclear matter. In the experiment, we measure mass spectra ofvector mesons in nuclei from the e+e− decay channel with high precision and high statistics.Shown in Fig. 1, a spectrometer of the experiment is developed and, GEM Trackers (GTR),which are composed of three layers of tracking planes in a magnetic field, are used to measuremomenta of the decay electrons in high counting-rate environment. Hadron Blind Detectors(HBD), which are gas Cerenkov counters using GEM, and Lead Glass Calorimeters (LG) areplaced outside the GTR to identify electrons. Efficient trigger system selecting events of e+e−

decays from huge background events must be constructed in order to reduce the trigger rate to1-2 kHz that our data acquisition system can cope with.

2. E16 trigger systemThe design of the E16 trigger system is shown in Fig. 2. The e+e− event trigger consists of three-fold coincidence of signals from the most outside GTR, HBD and LG. The number of channelsfor the trigger of GTR, HBD and LG is approximately 620, 940, and 1000, respectively. Thetrigger signals of 300 × 300 mm2 GTR and HBD are picked up from a cathode plane of aninduction gap of GEM chambers, namely, the last GEM foil in the stack, by Amplifier-Shaper-Discriminator (ASD) ASICs. The binary signals from the ASD preamp boards are converted tothe timing information on the Trigger Merger board (TRG-MRG). The merged information ofhit channels and timing on the TRG-MRG is sent to a global trigger decision module using a

21st International Conference on Computing in High Energy and Nuclear Physics (CHEP2015) IOP PublishingJournal of Physics: Conference Series 664 (2015) 082043 doi:10.1088/1742-6596/664/8/082043

Content from this work may be used under the terms of the Creative Commons Attribution 3.0 licence. Any further distributionof this work must maintain attribution to the author(s) and the title of the work, journal citation and DOI.

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0◦ ∼ ±12◦ both vertically and horizontally to avoid beam halo. Schematicview of the geometrical acceptances are shown in Fig.11.

GEM trackerPad chamber

Target

LeadGlass Calorimeter

beam

coilreturnyoke

CsI + GEM

Cherenkovradiator

polepiece

Figure 10: Schematic view of the proposed new spectrometer (planview/beam view). Green and red area represents pole piece and coil, re-spectively.

The list of detectors is shown in Table 1. The spectrometer has a largemagnet and detectors. We will use the same magnet used by E325. The track-ing device consists of 3 layers of GEM trackers and outside tracker. Particlemomentum is mainly determined by Gas Electron Multiplier(GEM) trackers.The GEM tracker is originally developed for the COMPASS experiment[21]for high rate counting and is also used at RCNP[22]. The outside tracker

15

Figure 1. Schematic view of the spectrometer

GTR100x100

GTR200x200

GTR300x300

HBD

LG

E16 256ch APV25hybrid

E16 256ch APV25hybrid

E16 256ch APV25hybrid

HBD ASD

SRS 128ch APV25hybrid

GTR ASD

APV25repeater

GTR/HBD FEMSRS-ADC/FEC

TRG-MRG

LG FEMDRS4+discri

Belle2FTSW

Belle2UT-3

TRG-MRG

TRG-MRG

network switch DAQ PCs

Data flowTrigger primitiveL1-trigger, global clockslow clontrol

~56000ch

~36000ch

~1000ch

~940ch

~620ch

~1000ch

FIG. 60: Overview of the readout and trigger system.

window of data acquisition. The scaling factor is estimated to be ∼16 for the GTR whose

time window is ∼500 nsec. According to the number of hits per event detected by VTC used

in E325, which was ∼15, the expected number of tracks per triggered event on each GTR

layer is ∼246. HBD (LG) has less hits due to the narrow time window, 150 nsec (200 nsec).

In the present calculation of the data size, it is assumed that each sample point of waveforms

has 2 Bytes and zero suppression algorithm is applied on each FEM. For the trigger rate of

2k events/spill, E16 DAQ needs to process ∼660M Bytes/spill. The experimental area and

the counting room is linked with several 10GbE optical fibers.

The detail of analog frontend circuits, digitizer modules, and trigger modules are described

in following subsections.

7.2. APV chip and preamp for the GEM readout

The FEM for GTR and HBD is based on the Scalable Readout System (SRS) [24], which

is developed by the CERN-RD51 collaboration [16]. We use SRS for the slow control of the

APV25 chips, digitization of analog data from the APV25 chips and transfer of digital data

to a computer [25].

Signals from strips of GTR or pads of HBD are fed into the preamp hybrid card using

67

Figure 2. A block diagram of data acquisition and trigger system.

high-speed optical link. We utilize two modules for the trigger decision, and generation of globaltrigger and clock distribution, Universal Trigger Board (UT3) and Front-end Timing Switch(FTSW), which are developed for Level-1 trigger system of the Belle-II experiment[2].

Details of the trigger electronics which consists of analog and digital signal processings aredescribed in a following section.

3. Trigger electronicsThe trigger electronics of the GEM chambers consists of analog and digital signal processingunits as preamp boards for the detectors and digital signal processing units having the TRG-MRG which receives digital signals from the preamp cards and sends hit information to theglobal trigger decision module, UT3 and the FTSW.

21st International Conference on Computing in High Energy and Nuclear Physics (CHEP2015) IOP PublishingJournal of Physics: Conference Series 664 (2015) 082043 doi:10.1088/1742-6596/664/8/082043

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3.1. Analog signal processingWe developed new Amplifier-Shaper-Discriminator (ASD) ASICs which can deal with largedetector capacitance originating from GEM and have a short shaping time to handle the highrate counting. A photograph of the ASD ASIC chip is shown in Fig. 3. The first idea toextract the trigger signal from these GEM detectors, such as GTR and HBD, is utilizing signalsof strips or pads on the anode readout plane which are originally used for tracking or electronidentification. However, this idea requires R&D of complex front-end circuits and a large numberof channels for the fast signal outputs. In order to avoid these problems, trigger signals are pickedup from a cathode plane of an induction gap of these GEM chambers, namely, the last GEMfoil in the stack. Considering using signals from the GEM foil, it is difficult to cope with largecapacitance of the order of nF by using normal preamps.

The trigger electronics for GTR need to cope with the large detector capacitance ofapproximately 2 nF, a fast shaping time, and a good signal-to-noise ratio for the minimuminput charge of 10 fC. The cathode plane of a GEM foil of the most outside GTR, whose sizeis 300 × 300 mm2, has detector capacitance of about 50 nF. The GEM foil is divided into 24segments in order to reduce the capacitance to about 2 nF and also a counting rate in eachsegment. These segments can be used for roughly track charged particles. The rough trackinghas an important role of decreasing a background of electrons which do not come from targets.In the forward region of the spectrometer, the maximum hit rate of each segment is expected tobe 1-2 MHz. Thus, we set the shaping time to 25 ns corresponding to a pulse width of about 200ns. The electric circuit of the ASIC was designed to suppress Equivalent Noise Charge (ENC)under 2 × 104 for the input detector capacitance of 2 nF. The ASD ASIC chip satisfying theabove requirements has been developed by our group in cooperation with the Open-It[3] project.The ASIC has a digital section containing an 8-bit register for control of a comparator on-off,a polarity of the comparator and an adjustment of each comparator threshold. A channel-by-channel fluctuation of the threshold can be compensated by the adjustment using a 4-bit internalDAC. The ASIC for the GTR is modified and used as the electronics for the trigger of the HBD.

A prototype of a preamp board with the ASIC chips was produced as shown in Fig. 4. Sizeof the board should be enough small to be installed in small spaces of GTR modules. Oneof functions of the preamp board is to convert discriminated digital outputs of the ASIC toparallel LVDS signals which are sent to the TRG-MRG. Also, the board is required to receiveslow control signals from the TRG-MRG to activate and control digital functions of the ASIC.We confirmed that the cathode signals from the GEM foil of GTR can be extracted using the

GEM foil trigger

フォイル読み出し用ASICFigure 3. A photograph of the ASD ASIC chip.

Figure 4. A photograph of the ASD preampboard.

21st International Conference on Computing in High Energy and Nuclear Physics (CHEP2015) IOP PublishingJournal of Physics: Conference Series 664 (2015) 082043 doi:10.1088/1742-6596/664/8/082043

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Figure 5. A photograph of the TRG-MRG.

LVDS Receiver

GTR-ASD

TDC

slow control

trigger,clock I/FGTX

Xilinx AuroraLAN I/F

MUXDEMUX

FIFO

time stamp offset adjustment

hit detection

FIFO

to Belle2 UT-3 from Belle2 FTSW

FPGA

FMC x2

to/from PC

24ch/card

96ch/FMC

FIG. 71: A block diagram of TRG-MRG. TRG-MRG consists of one carrier card with high speed

optical links and two mezzanine cards for the receiver of the frontend output signals.

length of ∼250 bits. Each frame contains up to 8 hits and additional information such as the

data source ID, number of hits and error status flags. The data frame is 64b66b (or 8b10b)

encoded and sent to UT3 every 64 nsec by using Xilinx Aurora 64b66b (or 8b10b) protocol.

The required bit rate is ∼4 Gbps/lane while the 64b66b(8b10b) encoding inserts 3(25)% ad-

ditional bits for the stable data communication. With the above bit rate, each GTX link can

process 125M cps. In order to cope with up to 2M cps per channel, the number of trigger

segments per GTX link is set to be 48-64 channels. In the present design of TRG-MRG, the

link speed including the encoding overhead is set to be 5 Gbps for the communication with

GTX ports of UT3 using 8b10b encoding, and 10 Gbps for the communication with GTH

ports of UT3 using 64b66b encoding. When a hit rate exceeds the maximum transfer rate of

TRG-MRG due to, say, the bad spill structure, some hits are lost and an error bit is set in

the status flags in the data frame.

UT3 is a triple-slot wide 6U VME module with a Xilinx Virtex-6 HXT FPGA and 16 Quad-

SFP (QSFP) modules, i.e. 64 multi-gigabit transceivers. In our experiment, UT3 gathers

L1-trigger primitive signals from 2548 trigger segments and generate a Level-1 trigger using

a coincidence matrix of GTR × HBD × LG. The L1 trigger is broadcast via the FTSW as

a serialized and 8b10b encoded data. FTSW is a double-slot wide 6U VME module, which

serves as a 1:20 fan-out module of the trigger and clock signal. The trigger and clock are

transmitted as AC-coupled LVDS signals using category-7 (CAT7) LAN cables.

78

Figure 6. A block diagram of the TRG-MRG.

preamp board.

3.2. Digital signal processingDigital signals from the ASD preamp board are handled by the TRG-MRG. The TRG-MRGconsists of a carrier card and two mezzanine cards as shown in Fig. 5. The TRG-MRG carriercard has a Xilinx Kintex-7 FPGA, two FMC slots, eight SFP+ transceiver slots and the trigger-clock interfaces. The board is a 9U form factor without a back plane. The TRG-MRG mezzaninecard has 96 channel LVDS receivers per card and the slow control interface for the ASD preampboards.

Firmware of the TRG-MRG has been developed for pre-processing and serializing the triggersignals from GTR, HBD and LG. The LVDS signals from the ASD preamp boards are convertedto timing information with better than 10 ns resolution on the TRG-MRG board as shown inFig. 6. Time stamps of the ASD hits are determined by the global clock of 125 MHz. A differenceof a cable delay is compensated by delay buffers on the FPGA. Timing information is packedin a data frame with a fixed length of about 250 bits. The data frame contains up to 8 hits,and additional information such as the data source ID, number of hits and error flags. The dataframe is 64b66b encoded and sent to the UT3 module every 64 ns using Xilinx Aurora 64b66bprotocol. Test of the TRG-MRG is on going. The UT3 module is a triple-slot wide 6U VMEmodule with a Xilinx Virtex-6 HXT FPGA and 64 multi-gigabit transceivers. The UT3 modulegathers trigger signals from 2548 trigger segments and generates a Level-1 event trigger using acoincidence matrix of GTR × HBD × LG. The event trigger is broadcasted via the FTSW as aserialized and encoded data.

4. SummaryAn ASD ASIC for the trigger using signals from the cathode plane of a GEM foil was developed.A preamp card with the ASICs was developed. We confirmed that the ASIC satisfies therequirements and the cathode signal from GTR can be extracted using the preamp card.

In order to handle digital signals from the ASIC, we developed the TRG-MRG which convertsthe LVDS signals to information of hit channels and timing and sends the information to the

21st International Conference on Computing in High Energy and Nuclear Physics (CHEP2015) IOP PublishingJournal of Physics: Conference Series 664 (2015) 082043 doi:10.1088/1742-6596/664/8/082043

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UT3 using Xilinx Aurora 64b66b protocol. Firmware of the TRG-MRG has been developed andtest is on going.[1] http://j-parc.jp/researcher/Hadron/en/pac 0606/pdf/p16-Yokkaichi 2.pdf[2] Iwasaki Y et al 2011 Level 1 Trigger System for the Belle II Experiment, Nuclear Science, IEEE Transactions

58, 4, 1807-1815. doi: 10.1109/TNS.2011.2119329[3] http://openit.kek.jp/

21st International Conference on Computing in High Energy and Nuclear Physics (CHEP2015) IOP PublishingJournal of Physics: Conference Series 664 (2015) 082043 doi:10.1088/1742-6596/664/8/082043

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