designing dc to dc converters with dpa-switchtm dc to dc converters with dpa-switchtm • covers...

8-1 DPA Seminar 11252003

Designing DC to DC Converterswith

DPA-SwitchTM

• Covers 0-100 watt, 24/48 VDC input applications


Agenda

• Introduction

• DPA-Switch Operation– Basics– Built-in Features– User Configurable Features

• Designing with DPA-Switch

• Hints and Tips

• Application Examples

• Questions and Answers


Introduction


Company Overview

• Leader in high voltage monolithic power conversion ICs

• > One billion devices shipped

• Revolutionary products

• Proven quality and delivery performance

• Pioneer in energy efficiency (EcoSmart®)

• Power Integrations was the world’s first semiconductor company to introduce highly energy efficient power conversion ICs, based on its patented EcoSmart® technology.

• TinySwitch received the 1999 Discover magazine award for the best technological innovation, in their ENVIRONMENT category, for its power saving EcoSmart features.

• 10% of the world’s electrical energy is wasted by products that are in standby.

• EcoSmart technology practically eliminates standby waste.


Technology Leadership

• Integrated high-voltage, high frequency MOSFET

• Patented device structure

• Uses industry standard 3 µ CMOS process

• Widely available capacity


Discrete PWM CircuitStart-up

PWM ControllerThermal Shutdown

High Voltage MOSFET

Gate Drive

Current Limit

Oscillator

Feedback Compensation

• Power Integrations’ ICs integrate the high-voltage MOSFET, PWM controller and:

– The MOSFET gate-drive circuit

– A high-voltage current source (start-up circuit)

– “Loss-less” DRAIN current sensing and limiting

– oscillator timing components

– feedback compensation

– Thermal protection


Equivalent Power Integrations Solution

20 to 50 components eliminated

• The Newest PI product families also feature integrated functions such as:

– A 10 ms soft-start function

– A switching frequency dithering (jitter) function that lowers the “annoyance factor” of EMI and makes it easier for a design to reliably meet EMI specifications

– Line Under-Voltage (UV) lockout, Over Voltage (OV) shutdown and maximum duty-cycle reduction (DCMAX) functions

– An auto-restart function that limits short-circuit and overload power delivery

– Externally programmable, “loss-less” DRAIN current limiting

– remote ON/OFF capability

– very low standby and no-load power consumption (PI’s patented EcoSmart Technology)


TIME

Continuous Innovation

• Power Integrations continuously introduces innovative new power conversion ICs.


Output Power (Watts)

TinySwitch-II TinySwitch

2 W - 20 W

LinkSwitch 0 W - 4 W

TOPSwitch-GX 10 W - 250 W

DPA-Switch 0 W - 100 W

Cost Effective Over Wide Power Range

• Power Integrations’ ICs cost effectively cover:

– 95% of all AC-DC power supplies, within the range of under one watt to 250 watts

LinkSwitch <1 W to 4 W

TinySwitch-II 2 W to 20 W

TOPSwitch-GX 10 W to 250 W

– 24/48 V DC-DC applications, within the range of under one watt to 100 watts

DPA-Switch <1 W to 100 W

• This graph only approximates the power capabilities of each product family. For more accurate data, see the output power table on each product family data sheet.


Comprehensive Design Support

• Design Accelerator Kits– Fully tested power supply– Product samples– Complete design documentation

• PI Expert design software

• Technical documents on website

• Power Integrations has the most comprehensive design tools in the industry.


Global Applications Support

Fully Equipped Applications Labs

Fully equipped PI applications labs are located worldwide:

• United States

– San Jose, California Chicago, Illinois Atlanta, Georgia

• Europe

– London, UK Munich, Germany Milano, Italy

• Asia

– Taipei, Taiwan Seoul, South Korea Shenzhen, PRC

– Shanghai, PRC Yokohama, Japan Bangalore, India


Wide Customer Acceptance

• Many major OEMs worldwide use Power Integrations’ ICs in their products.


Introducing DPA-SwitchThe Industry’s First Fully Integrated

220 V Monolithic Converter IC

Distributed Power Architectures

for


DPA-Switch Highlights

• Ideal for 24/48 V applications

• Wide input range: 16 VDC to 75 VDC

• Scalable: <1 W to 100 W

• Supports Forward, Flyback and Buck topologies

• Integrated 220 V, high-speed, power MOSFET + control circuitry

• Programmable loss-less current sensing and limiting

• Accurate input UV/OV detection

• Overload, open loop, and thermal fault protection

• Synchronous or diode rectification (300/400 kHz)

• Maximum 75% duty cycle – wide input range & high efficiency

• Integrated high-voltage startup current source

• Soft-start minimizes component stress and output overshoot


Shrinking the Footprint of Power

70 components 37 components

30 W discrete solution 30 W DPA-Switch solution

• On the left is a commercially available, single sided, one board, DC/DC converter

• Converters with double sided component placement and multiple PCBs may look smaller, but their component count remains very high

• The DPA-Switch based converter on the right is also a one board, single sided unit


DPA-Switch Applications

Industrial controls

Digital PABX/VoIPphones

DC-DC Converters

Servers

Automotive

Telecom andnetwork infrastructure/PoE

• DPA-Switch can cost effectively provide power solutions for a wide range of products and applications

Seminar_DPA_100102_screen_1021028-17

DPA-Switch Operation


Basics


CONTROL pin characteristic

IC

DPA-Switch supply

DPA-Switch Basics

• DPA-Switch is a current to duty-cycle converter– Current into the CONTROL pin reduces the PWM duty-cycle

• The CONTROL pin is a combined supply and feedback input. Once the supply current (grey area in the above graph) for the IC has been exceeded, the more the feedback current increases, the more the internal MOSFET duty cycle is reduced

• DPA-Switch is based on the proven TOPSwitch® technology

– Similar to the TOPSwitch-GX in function, the 220 V MOSFET is optimized for higher switching frequencies (300/400 kHz)

– Fixed-frequency, voltage-mode control (duty-cycle, not current-limit controlled)

– Voltage mode control allows >50% duty cycle without requiring slope compensation

– Maximum duty cycle can be reduced, as VIN increases, preventing transformer saturation at high line (see the Built-in Features section)


Start-up: Charging CONTROL Pin Capacitor

CONTROL pin capacitor(68 µF typical)

The CONTROL pin capacitor is charged to 5.8 V, by a high-voltage current source (from the DRAIN pin)

No external start-up resistor is required

• The charging current is only about 4 mA, and the di/dt is zero once 5.8 V is reached. Therefore, this charging current does not affect (raise) the output voltage


The CONTROL pin capacitor is recharged (during the MOSFET off times), by the high-voltage current source, to maintain 5.8 V during the soft-start period

Output voltage starts rising

Start-up: Drain Starts Switching

When the CONTROL pin reaches 5.8 V, MOSFET switching (soft)starts, with gradually increasing duty-cycle & current limit


Output Reaches Regulation

The DPA-Switch now receives current from the bias winding, and its internal high-voltage current source has been disabled.CONTROL pin current in excess of the supply current is used as feedback, to keep the output in regulation.

The opto turns on when the output voltage value reaches regulation, closing the feedback loop

IC


Start-up Control Pin Waveform

Charging the CONTROL pin

Output in regulation, DPA-Switchpowered from the bias winding

Soft-startoutput voltage rises

CONTROL & DRAIN pin start-up waveforms: normal load conditions

• At start-up, the internal high-voltage current source charges the CONTROL pin capacitor to 5.8 V

• At 5.8 V, MOSFET switching begins, in the soft-start mode

• The output voltage rises and reaches the regulation value and the opto turns on, driving current into the CONTROL pin

• The IC adjusts the duty cycle, based on the CONTROL pin current, maintaining output regulation

• The CONTROL pin voltage is set by an internal shunt regulator, making it a current driven input. Any in-circuit testing performed at incoming inspection must limit the current supplied to the CONTROL pin to the range specified in the device data sheet, which also has recommended test circuits.


Auto-restart: Overload/Open Loop Protection

If no feedback current is received before the CONTROL pin discharges to 4.8 V, an auto-restart sequence starts

Soft-start period

CONTROL & DRAIN pin start-up waveforms: overload/open loop fault conditions

• If the CONTROL pin receives no current from the opto, by the end of the soft-start period (when the internal high-voltage current source is disabled), the CONTROL pin capacitor begins to discharge

• When the CONTROL pin capacitor has discharged to 4.8 V, the MOSFET is disabled and the CONTROL pin capacitor is charged and allowed to discharge, for 7 cycles

• The MOSFET is again enabled, after the 7th charge/discharge cycle, and the IC initiates the soft-start function again

• If the CONTROL pin receives no current from the opto, by the end of the soft-start period, the entire sequence repeats again

• Overload/open loop protection is very well defined

– It does not rely on the loss of the bias winding supply voltage

– Any time output regulation is lost, the opto turns off, the CONTROL pin capacitor discharges to 4.8 V, and the auto-restart function is initiated


Built-in Features

• These features do not require external components


DPA-Switch Loss-less Current Sense

• No sense resistor is needed –(no extra I2R losses incurred)

• No expensive current sense transformer is needed

• Trimmed to ±7% accuracy

• Temperature compensated

– RREF tracks RDS(ON) temperature

• Built-in leading edge blanking– Filters turn-on spikes without

requiring external components– Allows very fast current limit

RDS(ON) is used as the current sense resistor

• The Leading Edge Blanking (LEB) feature (not shown) eliminates the need for low pass filter components on the input of the current limit comparator

• This allows very fast current limiting: turns off the MOSFET in about 100 ns

• The current limit comparator is only connected to the DRAIN when the MOSFET is on. When the MOSFET is off, the comparator is disconnected from the DRAIN


DPA-Switch vs Discrete Sense Resistor

• Effectively increases resistance by up to 150% (RDS(ON) + RSENSE) – Adds to conduction losses– Higher cost– Layout is more difficult– Additional components

* - Assumes 0.5 V ISENSE voltage Threshold

PARAMETER SENSERESISTOR DPA424

ILIMIT */Selected 2.0 A 2.0 A

RSENSE 0.25 Ω 0 Ω

RDS(ON) 0.75 Ω 0.75 Ω

EffectiveResistance 1.00 Ω 0.75 Ω

PI-3168-050803

• A discrete implementation requires a low pass noise filter, to keep the turn-on noise spike from prematurely tripping the comparator. This increases both the turn-off delay time and the minimum on-time of the MOSFET

• To match the equivalent effective resistance of the DPA-Switch (in the above example) the discrete MOSFET would need to have 33% lower RDS(ON)!


Additional current sense transformer components

DPA-Switch vs Current Sense Transformer

• Current sense transformer disadvantages

– Very high cost– Require more board space– Require many additional

components

• Current sense transformers are typically used in discrete converters of ≥ 25 watts

• DPA-Switch totally eliminates current sense transformers, at any power level


Discrete vs DPA-Switch Losses

• IRF640NS vs DPA425 – half the RDS(ON) but twice the switching losses, even at a lower switching frequency

• IRFR220 vs DPA424 – lower RDS(ON) but higher overall losses (due to lower duty cycle and higher rms currents than the DPA424)

• DPA425 – lowest overall loss, for a 30 W design

DEVICERDS(ON)

(Ω)

DMAX AT48 VDC

(%)

FREQ(kHz)

TURN ONLOSS (mW)

CONDUCTIONLOSS (mW)

TURN OFFLOSS (mW)

TOTAL LOSS(PON + PCOND +

POFF) (mW)

IRFR220 0.60 0.367 390 135 1115 170 1420

IRF640NS 0.15 0.508 277 88 365 787 1240

IRF634S 0.45 0.438 309 110 766 214 1090

DPA424 0.75 0.558 406 111 798 221 1130

DPA425 0.38 0.555 415 108 461 367 936

PI-3233-050803

• Three commercially available 30 W DC/DC converters were measured and compared to DPA-Switch performance, at the same power levels

• RDS(ON) alone is not a good measure of switching efficiency


0 1 2 3Time (µs)

0.00.51.01.52.02.53.03.54.04.55.0

0 1 2 3Time (µs)

The Goal is Efficiency not just low RDS(ON)

• PI MOSFET technology has extremely low switching losses, enabling higher efficiency designs even with > 4 times the RDS(ON) of a discrete

Turn off loss

Turn off loss

Conduction loss

Conduction loss

Turn on loss Turn on loss

IRF640NS Supply, 48 V, 30 W

Measured loss per switching cycle: DPA-Switch vs Discrete

RDS(ON) = 0.75 ΩRDS(ON) = 0.15 ΩE

ner

gy

Lo

ss (

µJ)

DPA424 Supply, 48 V, 30 W

• Measurements were made on an EP-21 (DPA424) and a commercially available IRF640NS based, 30 W DC/DC converter, at the same power rating

• The IRF640NS based converter had 600% higher turn off losses than the DPA-Switch converter. A direct comparison of conduction losses was not possible, since the solutions operate at different switching frequencies (400 kHz vs 277 kHz) and have different primary current waveforms


5 ms

Du

ty C

ycle

78%Loop closedNo soft-finish capacitor

Loop closedWith soft-finish capacitor

Internal DCMAX Limit

Final operatingDuty Cycle

Time

Fully Integrated 5 ms Soft-start Function

• Benefits

– Reduces start-up component stresses

– Helps avoid core saturation during start-up

– Minimizes start-up overshoot

• Duty cycle and DRAIN current limit are ramped up, during this period

– Soft-start is reinitiated after the removal of an overload or a thermal fault

• DCMAX: Maximum Duty-Cycle

• For an output voltage > 5 V, a soft-finish capacitor is usually not required. However, the effects of a soft-finish capacitor are described on the next slide


Soft-finish: Eliminates Output Overshoot

5 ms/div

1 V/div

• Soft-start improves but does not eliminate output overshoot

• Overshoot can be completely eliminated by using a soft-finish capacitor (C13)

• When output voltage rises to LED + diode drop, the soft-finish capacitor forces current through the opto, closing the loop

• Output rises in closed loop, preventing overshoot, from that point forward

• Modify value of C13 to adjust output voltage rise time

VOUT

• R7 discharges C13 at turn off, resetting the soft-finish function

• D3 isolates C13 from the main control loop, once it has been fully charged by R7, to prevent C13 from influencing the control loop response

• NOTE: The initial step in VOUT is due to a fixed, 2 ms, minimum duty cycle period, that must elapse before the soft-start circuit begins ramping up the duty cycle


Hysteretic Thermal Shutdown Protection

• On-chip MOSFET temperature sensing provides robust protection

• Protects the entire system: the IC, the PC board and the magnetic components

PARAMETER VALUE

Shutdown (tOFF) 137 °C ± 5%

Hysteresis 27 °C PI-3169-050903


• Capacitively coupled substrate current (ISUB) causes common mode EMI

• For DPA-Switch ISUB = 0, low common mode EMI

Source Connected Tab Improves EMI• Discrete

• DPA-Switch

• The Drain of discrete MOSFETs are connected to their package tabs, which makes them radiate switching noise

• The DPA-Switch package tab is connected to the Source of its MOSFET, leaving it electrically “quiet” (a fundamental advantage of the PI lateral, high-voltage process)


MIN TYP MAX

ILIMIT (DPA423) 1.16 1.25 1.34

-7% +7% PI-3160-090902

MIN TYP MAX

FREQUENCY 375 400 425

-7% +7% PI-3161-082002

Current Limit Frequency

Temperature Compensated Critical Parameters

Tolerance at 25°C Tolerance at 25°C

• All critical parameters are temperature compensated and trimmed during testing, for high accuracy

• Easier to design for high volume manufacturing


Cycle Skipping Operation

As load CONTROL pin current

Duty cycle

At light load, cycle skipping starts as the CONTROL pin current increases (beyond minimum duty cycle)

• Retains output regulation at light/no-load

• Reduces standby consumption (EcoSmart)

• Minimum duty cycle is typically 4%. Therefore, cycle skipping only occurs at very light loads

• A small output pre-load (typically < 0.5% of full load) can prevent cycle skipping


Built-in Features - Summary

FEATURE BENEFIT

Lossless current sense Lower conduction losses

High speed MOSFET Dramatically lower switching losses

Soft-start Prevents transformer saturation /reduces component stresses

Auto-restart Very well definedoverload/open-loop protection

Thermal shutdown Provides system level thermalprotection

High maximum dutycycle (75%)

High efficiency & wide input range withno slope compensation componentsrequired (voltage mode control)

PI-3170-050803

• Voltage-mode control-loop response: the output voltage typically settles < 200 µs of a step-load change - See Application Examples, section EP-21, load step response


Built-in Features - Summary

FEATURE BENEFIT

Internal high voltage start-up current source

Increased efficiency/lower power loss No external startup resistor

Tab connected to Source Low EMI

Tight tolerance over temperature on all critical parameters

Improved design margin for high volume production

Cycle skipping (EcoSmart) Energy efficient no-load regulation

Industrial temperature range Addresses all markets

Pin removed from package Wider creepage/clearance PI-3171-091602


User Configurable Features


Single Resistor (RIL) Sets Loss-less Current Limit

Note: RIL > 35 kΩ can trigger remote OFF

64% using 12 kΩ

86% using 8.25 kΩ

34% using 25 kΩ

• The DPA-Switch is a voltage-mode controlled device

– The current limit is typically set lower than the default, to limit overload power delivery

• The max & min limits shown include both device-to-device & temperature tolerances

• An externally programmed current limit is still loss-less

• Resistor values greater than 35 kΩ are not recommended


Overload = 8.5 A out

Max load = 6.0 A out

Overload = 7.0 A out

Max load = 6.0 A out

ILIMIT = 100 %RIL = 0 Ω

ILIMIT = 86 %RIL = 8.25 kΩ

RIL sets ILIMIT

RIL Sets Output Overload Power Limit

I DR

AIN

I DR

AIN

time

time

500 ns/div

500 ns/div

• In the example shown, the value of RIL chosen reduces overload current by 20%

– Allows lower cost rectifiers, chokes and capacitors to be used, without reducing reliability

• The above measurements were taken on the EP-21 unit

• Sensing and adjusting the current limit can take up to 6 external components, when implemented with discrete components

• Leading edge blanking prevents the initial current “spike” from triggering the current limit function


UV

LIN(UV)LS I

VVR

−=

( )VL = 2.35 VIUV = 50 µA

Single Resistor (RLS) Sets Input UV/OV

• UV hysteresis meet ETSI standard

• Fixed UV/OV ratio of 1 : 2.7 – Extra components allow independent adjustment– UV, OV or both can be disabled

• Line under-voltage (for the example shown in the slide)

– As the input voltage increases, the supply will turn on at about 33.4 V

– As the input voltage decreases, the supply will turn off at about 31.5 V

– As the input voltage decreases, if regulation is lost before 31.5 V, the input must increase back up to 33.4 V, for the supply to turn on again

• Line overvoltage (for the example shown in the slide)

– As the input voltage increases, the supply will turn off at about 86.0 V

– As the input voltage decreases, the supply will turn back on at about 83.5 V

• The Magnetics Design Spreadsheet assists in choosing a value of RLS, for a specified pair of UV/OV set-points (see Designing with DPA-Switch)

• RLS also actuates the DCMAX reduction function described on the next slide

• When the L pin current reaches 50 µA, operation is enabled. When it reaches 135 µA, operation is disabled. With a 619 kΩ resistor, this corresponds to input voltages of 33.4 V and 86 V respectively. There is hysteresis on both set-points

• As shown above, the supply would start operating before VIN reached 36 V


RLS Also Programs DCMAX Reduction

• As VIN (and L pin current) increases,maximum duty cycle is reduced

• Extends transformer reset time as VIN increases– Prevents forward converter transformer saturation

• The DCMAX reduction function was designed to correlate with the requirements that a typical Forward converter would have, for a given value of RLS and UV/OV set-points

• It is recommended that an RLS resistor be included in all Forward converter designs

• If RLS is not used, DCMAX stays at the maximum value, for all input voltages. This may be acceptable in low voltage applications (18 to 36 V), but transient load tests should be performed at max VIN, to verify that the transformer does not saturate

• Since the DPA-Switch is voltage-mode controlled, no slope compensation components are required to maintain loop stability at >50% duty cycle


Temperature Compensated UV/OV Thresholds

Undervoltage Threshold Overvoltage Threshold

Tolerance at 25°C Tolerance at 25°C MIN TYP MAX

IUV (ON to OFF) 48 50 52

IUV (OFF to ON) 44.5 47 49.5

-5.5% +5.5% PI-3157-082002

MIN TYP MAX

IOV (ON to OFF) 135 149

IOV (OFF to ON) 117 131

-11% +10% PI-3158-091602

• The UV threshold is more tightly specified than the OV threshold is, to meet ETSI requirements


Adjusting the UV/OV ratio

• The UV/OV ratio is fixed at 1 : 2.7

• The ratio can be modified by making the L pin current nonlinear with VIN

• Zener diode VZ modifies the linearity of the L pin current with VIN

• The data sheet shows many other L pin configurations, including ways to disable the UV or OV functions individually

• RLS sets VIN(UV) (Vz > VIN(UV))

• VZ, R1 and RLS set VIN(OV)


400 kHz 300 kHz

Note: The F pin should not be left open

Selecting Switching Frequency

• Smallest magnetics

• Optimum for diode rectification

• Lower switching losses

• More reset time for transformer

• Optimum for sync. rectification

• In a discrete design, adjusting frequency can take 3 or more external components


Remote ON/OFF Configurations

(1) Active ON (2) Active OFF

• The data sheet shows many other configurations

INPUT VOLTAGE 36 V 48 V 72 V

Remote OFF Input Power 36 mW 48 mW 72 mW PI-3172-081502

• In a discrete design, equivalent functionality can take up to 7 components


Synchronization: Non-Isolated Free Running

• When the L-pin goes above 1 V, the oscillator stops at the end of the cycle– If the L pin is left floating, the internal 170 µA pull-up to 1.5 V stops the oscillator

• When the L-pin is pulled below 1 V, the oscillator restarts a new cycle

• R2 turns Q1 on at start-up, allowing the DPA-Switch to free run– The R2-C1 time constant should be much greater than the maximum sync off time

• C1 couples the sync pulse to the gate of Q1

• The oscillator can only be synchronized to lower frequencies

– The oscillator stops and starts according to the sync pulses, therefore only frequencies below that of the internal oscillator frequency can be synchronized to

• When the L pin is used for synchronization, it cannot also be used for UV/OV

• D1 clamps the Q1-gate, ensuring that the falling edge of the sync pulse turns Q1 off

– The maximum turn-on delay, following the sync signal, is 250 ns

• If free running start-up is not required, R2 can be eliminated. Then Q1 will be off until the sync pulses arrive. D1 should then be connected with its anode to the source of Q1 and its cathode to the gate of Q1, to reset C1 every time the sync pulse goes low

• The internal L pin, pull-up current source (170 µA) is disabled at approximately 1.5 V, to avoid pulling the L pin up into its UV/OV threshold operating range


Synchronization: Isolated Free Running

• Note: opto-couplers are too slow for synchronization

Pulse transformer

• Isolation is provided by the pulse transformer

• Again, R2 provides free running operation, if the sync pulses are not present

• Again, how D1 is connected depends on whether free running operation is desired or not


Synchronization Considerations

• DCMAX can effectively limit the maximum power capability of a solution, if its switching is synchronized at a lower frequency

– DCMAX is defined at full frequency; lower frequencies add dead-time

– Therefore, lower switching frequencies effectively reduce the DCMAX

– DCMAX(EFF) = 0.75 × fSYNC/fOSC

• The UV/OV function is not available when externally synchronized– When slaved to a master DPA-Switch, the UV/OV on the master can be used

SWITCH FREQUENCY PRACTICAL SYNC RANGE

300 kHz 300 kHz to 180 kHz

400 kHz 400 kHz to 300 kHz PI-3173-091602

• To take advantage of the maximize power capability of the DPA-Switch, use the lowest internal oscillator frequency that can be synchronized to, to obtain the highest DCMAX possible (the DCMAX at 300 kHz > the DCMAX at 400 kHz)


Synchronization Timing Requirements

• ton(sync) must be >120 ns to ensure it is recognized as an ON command

• toff(sync) >7700 ns can be interpreted as a remote off condition, triggering soft-start when re-enabled


Other X-pin and L-pin Configurations

Many other configurations possibleSee DPA-Switch data sheet


User Configurable Features Summary

DESCRIPTION PIN BENEFITS

Programmablelossless current limit X-pin Replaces/eliminates current

transformer or power resistor

Accurate UV/OV L-pin Single resistor programming

DCMAX reduction L-pin Prevents transformer saturation

Selectable switchingfrequency F-pin 300 kHz for sync rectification

400 kHz for diode rectification

Remote ON/OFF L-pin/X-pin Low parts count and lowstandby power

Synchronization L-pin Allows sync to lower frequency PI-3174-050803

• Three DPA-Switch pins have user configurable functions associated with them:

– The X pin allows the drain current limit to be programmed lower than the default value

– The L pin sets the UV/OV thresholds and reduces the maximum duty cycle as VIN increases

– The L pin also allows external synchronization to a lower frequency

– Either the L pin or the X pin can be used for remote ON/OFF control


Three terminal operation

Disabling User Configurable Features

• Features on user configurable pins can be disabled by connecting those pins to SOURCE

• Built-in features work even when used in three terminal mode

• The built-in features only require the three standard DPA-Switch terminals, DRAIN, SOURCE, and CONTROL, and no external components

• The functions on the other pins are disabled by connecting the pin to SOURCE


Accurate programmable loss-less current limit Internal soft-start

No external componentsSwitched, high-voltage, Startup Current Source

Accurate OV/UV line sense

Accurate 300/400 kHz clock

Auto-restart for short circuit protection

High Speed 220 V MOSFET

Loss-less current sense

Cycle skipping, for no load regulation(EcoSmart)

Thermal shutdown

DPA-Switch Block Diagram

1V threshold for ext. sync.

• This diagram shows the various functional blocks within the DPA-Switch, which were covered in detail, in the Built-in and User Configurable Features sections

• The DPA-Switch provides the highest level of integration by incorporating practically all primary side functions within a single monolithic device


DPA-Switch Features Reduce Component Count

Discrete DC-DC supplyColor coded functional blocks

DPA-Switch DC-DC supply Color coded functional blocks



DESCRIPTION # OF PARTSREDUCED COMMENT

Accurate OV/UV up to 11 Temperature stableSingle resistor

Thermal protection up to 4Directly senses MOSFETtemperatureHysteretic/self-resetting

Current sense usingRDS(ON)

up to 6

No sense power resistor, no currentsense transformerTight tolerance & temperaturecompensation

Fixed accurateswitch frequency up to 3 Tight tolerance & temperature stable

Selectable 300 kHz or 400 kHz

High voltage start-up up to 4 Integrated high voltage start-upIntegrated soft-start

PI-3175-050803

• These component savings were observed from comparisons with commercially available DC/DC converters



DESCRIPTION # OF PARTSREDUCED COMMENT

Source connected tab -Heatsink connected to source(tab)Reduced EMI

Voltage mode control up to 5 Allows >50% duty cycle withoutslope compensation

Remote off (primary side) up to 7 DPA-Switch implements withtransistor and two resistors

Controller and discretecomponents up to 6 Integrated DPA-Switch features

save external components

MOSFET & drivecomponents up to 4 Integrated DPA-Switch MOSFET

TOTAL COMPONENTSAVING WITH DPA-Switch up to 50

PI-3176-050803

• These component savings were observed from comparisons with commercially available DC/DC converters

• Component placement and assembly cost savings should also be considered in a full cost comparison


Designing with DPA-Switch


Flyback vs Forward

• Flyback– Lowest cost solution for output currents < ~ 6 Amps– Advantages: simple circuit - no output energy storage choke required– Disadvantages: higher output ripple current - higher output capacitor costs

• Forward – Lowest cost solution for output currents > ~ 6 Amps– Advantages: low output ripple - lower cost output capacitors– Disadvantages: more complex circuit - output energy storage choke required

• Although a Flyback converter may also use an output choke, it is being used to filter high frequency noise, not store significant energy. Therefore, the output chokes used in Flybacks are very low inductance


Flyback basics

• When switch is on, primary current ramps up storing energy in transformer

• When switch is off, the stored energy is transferred to the output

• The clamp circuit limits the transformer leakage inductance spike


Flyback Design Process

• Use the Step by step Flyback design methodology in AN-32– AN-32 was written to support AC/DC designs with TOPSwitch-GX

• The DPA-Switch Flyback procedure is identical, other than:– No input storage capacitance calculation– Lower VOR choice, typically 30 to 40 Volts– Clamp chosen appropriate to 220 V BVDSS - a single 130 V Zener from drain to

source is adequate for most designs (see DI-29) – Use VDS of 2.5 V: lower RDS(ON) and current limit threshold voltage– Transformer manufacturer’s core data for 300/400 kHz operation– Output capacitors: use tantalums for lowest impedance at high frequency– Select feedback components according to the DI-29 reference circuit

• Use the DPA-Switch Flyback spreadsheet in PI-Expert, to design the transformer

• Since Flyback design is similar to previous PI products, it will not be covered in detail here. Forward converter design is covered in detail, later in the presentation

• A full Flyback design methodology is available in AN-32 (with the differences listed above). However, the spreadsheet provided in PI-Expert automates this process, incorporating all of the above noted changes


• The DPA-Switch Flyback Design Spreadsheet is part of PI Expert

* Database contains parameters for popular DC/DC core types: – EFD, RM, PQ, EPC, PR, ER and ELP (planar)

USER INPUTS SPREADSHEET OUTPUTS

Specifications: VIN range Output Voltage(s) Total POUT Core Choice*

Design Variables: DPA-Switch Reflected Voltage Secondary turns

Primary inductance and primary/bias turns

L and X pin resistor recommended values

Core flux density

– recommends different core if necessary

Output ripple current

– for output capacitor choice

Output current/max reverse voltage

– for output diode choice PI-3344b-092302

Flyback Transformer Design Using Spreadsheet


Quick Design Checklist for Flyback

• Maximum drain voltage– Verify that peak drain voltage <80 - 90% BVDSS, under the worst case conditions

(typically high line and output overload)

• Drain current at maximum input voltage, load and ambient temperature– Check for transformer saturation at start-up and under steady state conditions– Leading edge current spikes must be within DPA-Switch current limit envelope

• Thermal– Verify that key component temperatures are within limits at maximum load,

maximum ambient temperature and minimum input voltage

– DPA-Switch, transformer, output diodes and output capacitors

– The recommended maximum DPA-Switch source pin/tab temperature is 110 °C

– See manufacturer specifications for the temperature limits of other components

• Typically, 25 V of additional drain-voltage margin is recommended, to allow for the unit-to-unit tolerances of other components

• Maximum overload power will be demanded from the converter, when the output is loaded to just before auto-restart occurs (when output regulation is lost)

• At a minimum, a design must pass these three tests, before it can be considered “production worthy”


Leading edgecurrent spike

100 ns Designs with core saturationnot recommended

After leading edge blanking time (tLEB=100 ns) drain current should be below current limit envelope characteristic

• Check that the current waveform is within the recommended limits

tLEB

Quick Design Checklist - Drain Current Waveform


OI I

IK

∆=∆

Forward Basics: Energy Delivery

(a) Switch ON: IL ramps up, delivering energy to inductor L and output

(b) Switch OFF: IL ramps down continuing energy delivery to output

• Energy delivered during on and off time - more efficient than flyback

t

• K∆I is a term used in PI Expert, which is defined as the quotient of inductor ripple current divided by the DC output current - typical values are between 0.15 to 0.20


Forward Basics: Transfer Function

• Forward converter is a step down transformer followed by a buck converter which averages the transformer output voltage waveform

DNN

VVP

SINO ××=

D = DPA-Switch duty cycle

Step down

Average

NP: NS


Forward Basics: Transformer Reset

• The practical transformer has finite magnetizing inductance– Flux builds up in the magnetizing inductance when the switch is on– Flux is reset each cycle, by the reset circuit, to prevent core saturation

• (VRESET × tOFF) ≥ (VIN × tON) to reset flux and prevent transformer saturation

• The magnetic flux, which is built up in one direction (VIN x tON), is reset by an equal and opposite Volt-second area (VRESET x tRESET)

• The transformer should also be designed to prevent excessive peak flux, within the on-time (tON) of each switch-cycle. Excessive peak flux can cause transformer saturation


1. Define the system requirements

2. Choose the DPA-Switch biasing technique

3. Magnetics design and DPA-Switch Selection

4. Clamp and reset circuit selection

5. Output capacitor selection

6. Feedback design

• See Application Note AN-31 for full details

Step by Step Forward Design Process


• Input voltage range– Define the UV/OV thresholds [33.5 V is the typical UVLO threshold,

for 36-72 VDC designs (assures 36 V start-up, including the L pin tolerances)]

• Output characteristics– Most regulation spec.s require a temperature compensated reference (TL431)– Define output ripple requirements: influences output inductor and capacitor choices

• Efficiency target– High efficiency designs (>85%) typically require synchronous rectification– Other designs can use Schottky diodes - lower cost– Choice of rectification technique influences the transformer design

• Operating Temperature range– Influences the choice of the output capacitors and of the DPA-Switch device,

plus the design and testing of the control loop

Step 1: Define System Requirements

• PI Expert calculates the L pin resistor value, for the desired input voltage range


Step 2: Choose DPA-Switch Biasing Technique

• Three techniques are available

BIAS TYPE INPUT VOLTAGE EFFICIENCY COMPLEXITY LIMITS OF USE

DC Input Derived 18 - 36 V Low Low Max bias limited by Opto/Zener dissipation

Forward Transformer bias winding Any Medium Medium

Max bias limited by Opto dissipation Bias voltage proportional to input voltage

Output coupled inductor Any High High May require minimum load

PI-3179-091602

• NOTE: Overload protection is not influenced by the bias technique. The DPA-Switchauto-restart function is activated when feedback current (not bias voltage) is lost

• The following slides describe each of the three bias techniques


DEVICE IC(SKIP)

DPA423 9 mA

DPA424 10 mA

DPA425 12 mA

DPA426 14 mA PI-3178-091602

Step 2: Bias Circuits: DC Input Derived

• Very Simple - no additional windings

• Limited by opto and zener losses

• Zener reduces dissipation in opto

• Minimum opto collector voltage for correct operation is 8 V

• Typically only for 18-36 VDC inputs

Maximum feedback current required (IC(SKIP)) depends on device

• IC(skip) is the highest DPA-Switch control current required. Therefore, it is the worst-case loss condition for both the opto-coupler and the Zener diode


)skip(CCBIASOPTO I)VV(P ×−= )skip(CCBIASOPTO I)VV(P ×−=

Step 2: Bias Circuits: Forward Winding

• Winding on transformer

• Lower dissipation than DC input derived

• Bias voltage of at least 8 V required at minimum DC input

• Bias voltage changes directly with input voltage

• Flyback winding not recommended

– Affects transformer reset

)skip(CCBIASOPTO I)VV(P ×−=

• With this technique, the bias voltage and opto dissipation vary with the input voltage

• If a Flyback winding were used, the large bias capacitor would clamp the drain voltage, limiting the reset voltage


Step 2: Bias Circuits: Coupled Inductor Winding

• A Flyback winding on the output inductor

• The most efficient, due to unvarying opto feed voltage

• A small preload may be required to keep bias in regulation at no-load (if no-load is required)

– Sufficient current through the output inductor is required to maintain bias for the DPA-Switch (see DI-24)


• Performed by PI Expert

The design database contains parameters for popular DC/DC core types: – EFD, RM, PQ, EPC, PR, ER and ELP (planar)

USER INPUTS SPREADSHEET OUTPUTS

Specifications: VIN range Output Voltage(s) Output Current(s)

Design Variables: DPA-Switch Switching Frequency Rectification Type (Sync/Diode)

Primary inductance and primary turns Output choke inductance/bias winding turns ratio DPA-Switch DMAX/IPEAK/IRMS L and X pin recommended resistor values Core flux density – recommends different core if necessary Output ripple current – for output capacitor choice Output Average current/max reverse voltage

– for choice of output rectifiers

PI-3345-112503

Step 3: Magnetics Design/DPA-Switch Selection

• PI Expert assumes that a coupled output inductor bias winding will be used. However, other bias techniques may be selected


OUTPUT POWER TABLE

48/60 V (36 – 75 VDC) INPUT RANGE

Total Device Dissipation

PRODUCT

0.5 W 1 W 2.5 W 4 W 6 W Max

Power Output

DPA423R 12 W 16 W - - - 18 W

DPA424R 16 W 23 W 35 W - - 35 W

DPA425R 23 W 32 W 50 W 62 W - 70 W

DPA426R 25 W 35 W 55 W 70 W 83 W 100 W PI-3206-082002

• Example: In a 23 W output design, the DPA424 will dissipate 1 W, worst-case, versus 0.5 W for the DPA425

• PI Expert chooses the smallest DPA-Switch for the peak power required

• The power table allows the efficiency of a larger device to be estimated

Step 3: Magnetics Design/DPA-Switch Selection

• PI Expert will choose the smallest DPA-Switch, that has sufficient power capability, for the lowest cost design. A device one size larger can be chosen, for higher efficiency (see Hints & Tips section)

• The data sheet provides the assumptions that were made, in generating the power table dissipation estimates

• The data sheet also provides power tables for other input voltage ranges (16-32 VDC and 24-48 VDC)

• The table above shows worst case dissipation for a 5 V Forward converter, with Schottky diode rectification (based on assumptions from the datasheet)

• The power capability depends on the allowable dissipation and/or the efficiency of the converter. The maximum power output is limited by the internal current limit


Step 4: Clamp and Reset Circuit for PO<40 W

See AN-31 page 6

CS is the main reset capacitor. It captures the magnetizing energy when the switch first turns off, then returns it to the core, as negative flux, during the “Relaxation Ring” part of the switching cycle (tRN). RS (typically 1 Ω) dampens oscillations.

A minimum value of CCP is used to clamp primary leakage inductance during normal operation.

Zener only clamps during transients and fault conditions.

Typical values shown

• The advantage of this reset scheme is that the energy in CS is recovered and transferred to the output during next switch-on cycle, increasing efficiency. The minimum value to guarantee worst-case reset should be selected (see next slide)

• In contrast, the energy in CCP is lost. Therefore, only a minimum value of CCPshould be used to clamp the leakage inductance spike

• CCP may not be required in low power designs

• CS may not be required in synchronous rectification designs, due to MOSFET gate capacitance performing the same function

• NOTE: AN-31 page numbers refer to the pages of the stand-alone document


Step 4: Selecting CS value using Drain Waveforms

Ts - switching periodton - MOSFET on timetRZ - reset of magnetizing flux to zerotRN - relaxation ring (negative flux)tVO - clamped by forward output diode

Insufficient reset time. Reset capacitor

(CS) too large

Acceptable Drain voltage waveformReset voltage beyond

recommended levels. Reset capacitor (CS) too small

V/div

• The reset voltage should be designed to be below VR1’s voltage rating

• If Cs is too large: The drain waveform does not flatten out, indicating that the magnetizing flux is still positive (the transformer has not been fully reset)

• Verify drain waveforms at both the lowest and the highest input voltages


Step 4: Resonant Reset Circuit for PO>40 W

• At high power levels, this technique allows re-circulation of both magnetizing and leakage energy

• Resonant L1/C1 period must be shorter than minimum DPA-Switch conduction time (1 to 1.5 µs, for one LC half-cycle)

• More complicated and expensive than the simple Zener/Capacitor scheme

See AN-31, page 7, for typical component values

• At DPA-Switch turn-off, any energy previously stored in C1 is delivered to output inductor

• When V1 exceeds VIN, D2 clamps to VIN, and C1 charges with energy from the leakage and magnetizing inductances

• During the remaining off time, the drain voltage will relax to VIN. C1 will retain its peak voltage value of VDS(PK) – VIN, unless VDS(PK) – VIN is > VIN, in which case D1 will conduct, clamping the voltage across C1 to VIN

• When the DPA-Switch turns on, V1 drops by a delta voltage equal to VIN and goes negative

• C1 recharges via the DPA-Switch MOSFET, diode D1 and inductor L1 and raises the voltage V1 to an equivalent positive voltage

• At the DPA-Switch turn-off, the voltage transition VDS causes D2 to conduct again, transferring the energy stored in C1 to the output inductor

• Resonant current through the DPA-Switch does increase the device losses. However, the clamp losses are recovered



Step 5: Output Capacitor Selection

• Select low enough ESR to meet output voltage ripple specifications– Tantalum type normally chosen (for low impedance at high frequencies)

• Select capacitance value to provide a 4-6 kHz pole with output inductor– See step 6: Feedback design

• Test control loop stability at extremes of specified temperature range – Capacitor parameters change with temperature, and can influence loop behavior

• See AN-31, page 9, for details



• The resonant frequency of the typical LC filter is between 4-6 kHz (f)– This range is typical of the values required for voltage and current ripple

• Use L2 value from Step 3: Magnetics Design

• Calculate the required amount of output capacitance

• See AN-31, page 10

Step 6: Feedback Design - Output LC Filter

C10+ C11= 1

L2× 2× π × f( )2

• 5 V output shown (4-6 kHz is typical of a 5 V output). The LC resonant frequency will typically be higher at lower output voltages



Step 6: Feedback DPA-Switch Compensation

• C6, R4 and CONTROL pin impedance introduce one pole and one zero in the converter frequency response

• C6: choose 47 µF to 100 µF – Low ESR recommended:

reduces effect of ESR change with temperature on the loop

• R4: Typically 1 Ω

• Locate high frequency bypass capacitor (C5) close to the CONTROL pin– 0.22 µF typical value (has negligible influence on loop response)

• Follow layout guidelines to keep switching noise out of the loop

• See AN-31, page 11, for details

• The CONTROL pin impedance is typically 15 Ω (see datasheet, ZC parameter)



Step 6: Feedback Design - Opto Compensation

• Low cost 100-200% CTR opto– Provides required CONTROL

pin drive and loop gain in most designs

• R6 must allow adequate CONTROL pin current

– Check maximum current required (IC(SKIP) in datasheet)

• The Phase boost zero (R12, C16) counters the LC output filter double pole– Choose values to provide a zero at 1 to 3 times the output LC resonant frequency


f = 12× π × R6+ R12( )× C16



Step 6: Feedback Design - TL431 Compensation

• Provides high loop gain at low frequencies

• Compensation network designed to optimize low frequency gain– Use 1 µF compensation capacitor (C14): establishes zero at <20 Hz – Series resistor R9 provides ~700 Hz zero, improving light load stability

• See AN-31 page 12 for details



Step 6: Feedback Design - Summary

• AN-31 provides typical component recommendations

• Application specifications can influence component values– Converter operating temperature range– Transient load response specifications – Circuit board material used: Aluminum substrate versus FR-4 PCB

• Component value choices should be made based on prototype tests

• Output voltage transient load response (peak deviation and settle time) provides a good first indication of control loop stability

– All tests should be performed at both input voltage extremes, load-step extremes and operating temperature extremes, to confirm acceptable performance


Quick Design Checklist for Forward• Maximum drain voltage

– Verify peak drain voltage < 80-90% of BVDSS under worst-case conditions (high line/overload)

• Transformer reset margin– Verify that the transformer resets at the highest VIN, with a 50–100% load step

(this test puts the greatest demand on the reset circuit)

• Drain current at maximum input voltage, load and ambient temperature– The transformer must not saturate at start-up, or various steady state conditions– The leading edge current spike must be within the device current limit envelope

(see the quick design checklist for Flyback design)

• Thermal– Verify that key component temperatures are within specified limits, at maximum

load, maximum ambient temperature and minimum input voltage

– The DPA-Switch, the transformer, output rectifiers and output capacitors

– The recommended maximum DPA-Switch source pin/tab temperature is 110 °C

• Worst-case loading (maximum overload) occurs just prior to auto-restart



Design Support Tools

• Application Note: AN-31– DC-DC Forward Converter Design

Guide

• Design Accelerator Kit: DAK-21– Includes tested EP-21 board– Engineering Report (EPR-21)– Datasheet and device samples– Blank PC Board

• Design Ideas– DI-24, 25, 29, 31, 32, 37 and 40

• PI Expert– PIXls forward design spreadsheet– PIXls flyback design spreadsheet

• All PI Design Ideas and Application Notes are available at www.powerint.com


Hints and Tips


DPA-Switch - Layout Considerations

• DPA-Switch is a precision, high frequency, high current power IC

• Layout is critical to achieve optimum performance

• The suggested guidelines should be followed as closely as possible


Primary Side Layout Suggestions

Only use SOURCE (PIN) as reference for small signals (low currents)

Minimize loop area from TAB (SOURCE) to input capacitors

Place decoupling capacitor right at CONTROL/SOURCE pins of device

Only use TAB (SOURCE) as return for high switching currents

Place L pin resistor close to device and keep L pin trace short to minimize noise on pin


Secondary Side Layout Suggestions

Minimize loop area (output diode, output inductor, transformer winding)

Connect common mode EMI capacitor to primary (VIN

+) positive input rail, not to SOURCE of DPA-Switch

Locate high frequency de-coupling capacitor right next to output pins of power supply


Efficiency Improvement Techniques

• Using larger DPA-Switch reduces MOSFET conduction losses

– Optimum selection is typically one device size larger than minimum required for power delivery

– Further increases in device size may decrease efficiency due to increase in switching loss

– Programmable ILIMIT allows same current limit with larger devices

• Larger magnetics can reduce copper/core losses

• Synchronous rectification reduces rectification losses

• See DI-24 vs DI-25 for example of these improvements

PARAMETER EFFICIENCY CHANGE

Larger vs Minimum required DPA-Switch +1% to 2%

Larger vs Minimum required Magnetics +1% to 2%

Synchronous vs Diode Rectification +3% to 8%

PI-3180-091702

• The externally programmable current limit allows a larger device to be used, without increasing the overload power or requiring magnetics design changes


Basic Synchronous Rectification Circuitry

• Self driven synchronous rectification (SDSR)

• Auto-restart prevents D3 from failing during short circuit

• Accurate DPA-SwitchOV/UV keeps Q1/Q2 gate drive within safe limits (2.5 V to 25 V)

• 300 kHz minimizes crossover losses

• See DI-25 and DI-40 for examples

OUTPUT VOLTAGE EFFICIENCY GAIN OVER DIODE RECTIFICATION

5 V +3%

3.3 V +6%

2.5 V +8% PI-3177-081602

• Q2 is turned on as the DPA-Switch turns on

– R1 limits the gate drive current and voltage spike during this hard switch event

• Q1 turns on with the primary reset voltage waveform

– Parallel diode D3 conducts when the primary reset is complete and Q1 gate drive has been lost (this prevents the Q1 body diode from conducting any substantial current)


Magnetics Construction• Core gapping: Forward Converters

– Start with the transformer core un-gapped - minimizes magnetizing energy– For some designs, a gap may be necessary, to reduce the reset time – Higher magnetizing energy forces a higher reset voltage and shorter reset time

• Core gapping: Flyback Converters– Always gap transformer cores according to PI Expert recommendations

• Flux density– AC-flux 1000 < BM < 1500 Gauss (for Forward) [100 < BM < 150 mT]– Peak-flux BP < 3000 Gauss (for Flyback) [BP < 300 mT]

• Windings– Use a split primary winding to reduce the leakage inductance– Use multi-strand wire to minimize Skin Effect - up to 4 strands can (typically)

be terminated, per pin– Consider using foil, if more than 4 strands are required

• A small core gap may be necessary. For example, if there is significant secondary capacitance, such as synchronous rectifier MOSFET gate capacitance, a small gap can help ensure complete core reset.

• The gap should be created using thin plastic film, between all legs of the core, since consistent center leg gapping can be difficult and problematic.


Hints for Low Output Voltage DC-DC Converters

• With <3.3 V outputs, a boost supply is required to drive feedback current– An additional transformer winding will be required to supply the TL431 and

opto-coupler (or, a low voltage (1.25 V) TLV431 could be used)

• With <2.5 V output, a higher voltage winding will be required to drive the synchronous rectifier MOSFET gates

• For low voltage outputs, remote sense is often required to compensate for the voltage drop in the output connections and the path to the load

– The anticipated voltage drop should be factored into the initial design specs

• Printed circuit traces should be short and wide to minimize voltage drops

• A secondary, high frequency LC post filter may be required to reduce switching frequency ripple and noise

• DI-40 is an example of a design with an output under 3.3 V


Hints for High Power DC-DC Converter Design

• Use aluminum-clad circuit board to optimize heatsinking

• Use resonant primary snubber/clamp to recycle energy (see DI-31)

• Secondary capacitance from synchronous rectifiers/snubber may require transformer gapping to reduce reset time

• Synchronous rectifiers: use gate resistors (1-10 Ω) to filter voltage spikes– Place secondary catch diode close to transformer to reduce secondary leakage spikes

• Use foil secondary windings or planar magnetics to reduce copper loss

• Use wide secondary traces or remote sensing to minimize voltage drops

• An example circuit for remote sensing is shown on the following slide


Example Remote Sense Circuit using TL431

R4 provides return for TL431 current when sense line is not connected. Choose lowest value possible but still much greater than Cable/Trace impedance

R2/R3 divider sets LOAD regulation voltage

C1 and C2 provide local AC feedback: they are only required if cable/trace impedance includes circuitry introducing significant phase shift e.g. local LC filter at remote LOAD

Provides local feedback if remote sense line not connected: typically chosen to be < 1% of R2 value

TL431 current path when sense line is disconnected

• A remote sense circuit ensures that regulation is maintained at the load

• The estimated, full-load cable and/or trace impedance related voltage drops should be taken into account, in the converter specifications: e.g. 5 V at the remote load may require 5.2 V at the converter output, increasing the rated power requirement by 4%

Seminar_DPA_100102_screen_1021028-98

DPA-SwitchApplication Examples


Application Examples

• 30 W Forward with diode rectification (EP-21/DI-24)– 5 V/6 A output, 36 V to 75 V input

• 30 W Forward with synchronous rectification (DI-25)– 5 V/6 A output, 36 V to 75 V input

• 20 W Forward with synchronous rectification (DI-40)– 2.5 V/8 A output, 36 V to 75 V input

• 70 W Forward with synchronous rectification (DI-31)– 5 V/14 A output, 36 V to 75 V input

• 15 W Multi output Forward with diode rectification (DI-32)– 5 V, 7 V, 20 V outputs, 36 V to 75 V input

• 25 W Flyback with diode rectification (DI-29)– 7 V/3.6 A output, 36 V to 75 V input

DI: Design Idea EP: Engineering Prototype Board

8-100 DPA Seminar 11252003

Specification (DI-24)

• Optimized for low cost– Smallest possible DPA-Switch– Diode output rectification– 400 kHz frequency to reduce

magnetics size

• Features used– Lossless current limit - no current

sense components– UV/OV and DCMAX reduction– No-load regulation– Thermal/overload protection

PARAMETER SPECIFICATION

Input Voltage 36 – 75 V

Output Voltage 5 V ± 5%

Output Current 6 A

Output Power 30 W

Efficiency 85%

Ambient TempRange

-40 °C to 65 °C withno heatsink

-40 °C to 85 °C withheatsink

Dimensions 58 × 44 × 11 mm(2.28 × 1.73 × 0.43″)

PI-3398-050803

8-101 DPA Seminar 11252003

Schematic (DI-24)

Zener clamps DRAIN voltage under transient & overload conditions

Reset capacitor Coupled choke bias winding for +1% efficiency improvement

ILIMIT program resistor Only 11 primary

components

Soft finish capacitor removes startup overshoot

Sets UV/OV & DCMAXreduction

Capacitor limits DRAIN voltage under normal load conditions

8-102 DPA Seminar 11252003

PC Board (DI-24)

• Provided in DAK-21 with full engineering report (EPR-21)

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36 VDC IN/5 V 6 A OUT 72 VDC IN/5 V 6 A OUT

96 V134 V

Drain Current and Voltage Waveforms

• Resets fully with comfortable margin at all line voltages (36 V to 72 V)

• Drain Voltage well within minimum device specifications

500 ns/div 500 ns/div

50 V/div

1 A/div

50 V/div

1 A/div

8-104 DPA Seminar 11252003

Thermal Derating Curve

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50% to 75 %, 100 mA/µs Step Load

Output Ripple and Transient Response (DI-24)

Output Switching Ripple - full load

100 µs/div

50 mV/div

2 A/div

1µs/div

20 mV/div

Ripple p-p = 34 mV Peak Deviation < 3%

Settling time < 200 µs

15 µs

1.5 A

• Measurements made at 48 V input

8-106 DPA Seminar 11252003

Summary (DI-24)

• Only 11 primary side components

• 85% efficiency with diode rectification– 90% efficiency possible with synchronous rectification (see DI-25)

• 400 kHz operation

• Accurate input UV/OV - meets ETSI standards

• Maintains regulation at no-load

• No current sense components

• Thermal/overload fault protection with automatic recovery

8-107 DPA Seminar 11252003

30 W Forward with sync. rectification (DI-25)

• Optimized for high efficiency– One size larger DPA-Switch than

DI-24 (identical output power)– synchronous rectification– 300 kHz frequency


sense components– UV/OV and DCMAX reduction– No-load regulation– Thermal/overload protection




Output Current 6 A

Output Power 30 W

Efficiency 90%

Ambient TempRange

-40 °C to 65 °Cwith no heatsink-40 °C to 85 °Cwith heatsink

Dimensions 58 × 44 × 11 mmPI-3236-050803

8-108 DPA Seminar 11252003

30 W 5V/6A Forward with sync. rectification (DI-25)

Only 10 primary side components!

Simple SDSR circuit - DPA-SwitchUV/OV features limit gate drivevoltage range

• SDSR – Self-Driven Synchronous Rectification

8-109 DPA Seminar 11252003

Comparison: Diode vs Synchronous Rectification

• Note approximately 5% efficiency improvement with synchronous rectification, one size larger DPA-Switch and optimized magnetics

Diode rectification

(DI-24)

Sync. rectification

(DI-25)Efficiency of Diode Rectification vs Sync Rectification

85%

90%

8-110 DPA Seminar 11252003

20 W 2.5 V/ 8 A Forward with sync. rectification (DI-40)

• High efficiency for low voltage output (86%)

– Optimized magnetics– Synchronous rectification– 300 kHz frequency


sense components– UV/OV– No-load regulation– Thermal/overload protection



Output Voltage 2.5 V ± 5%

Output Current 8 A

Output Power 20 W

Efficiency 86%

Ambient TempRange

-40 °C to 65 °Cwith no heatsink-40 °C to 85 °Cwith heatsink

PI-3182-050903

• This design uses the smallest DPA-Switch for the power required. One size larger could also be considered if higher efficiency is required.

8-111 DPA Seminar 11252003

20 W 2.5 V/8 A DC to DC Converter Circuit (DI-40)Low output voltage requires boost winding from output choke to supply opto/TL431

Forward bias winding taken from main transformer for DPA-Switchsupply


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20 W 2.5 V/8 A Converter Efficiency Results

8-113 DPA Seminar 11252003


• Optimized for efficiency– Largest DPA-Switch used – Synchronous rectification– 300 kHz frequency– 90% efficiency achieved


sense components even at 70 watts!– UV/OV and DCMAX reduction– No-load regulation– Thermal/overload protection




Output Current 14 A

Output Power 70 W

Efficiency 87%

Ambient TempRange

-40 °C to 85 °Cwith heatsink

PI-3124-050803

8-114 DPA Seminar 11252003



Even at 70 Watts, no current transformer required. Reduces system cost significantly

Only primary circuitry shown for clarity. For full

schematic see DI-31

Resonant clamp used to recycle magnetizing and leakage energy

Simple DPA-Switchcompensation components identical to lower power designs

• High power requires a resonant clamp circuit but otherwise primary circuitry is unchanged from lower power DPA-Switch designs - easily scalable solution

8-115 DPA Seminar 11252003

15 W Multi-output (DI-32)

• Excellent cross regulation on 3 outputs

• High efficiency: 88%

• Sync. rectification at 400 kHz minimizes magnetics size


sense components – UV/OV and DCMAX reduction– No-load regulation– Thermal/overload protection


Input Voltage 36 – 75 VDC

Output V1 V2 V3

5 V ± 5%

7.5 V ± 5% 20 V ± 15%

Output I1 I2 I3

2.4 A 0.4 A

0.01 A

Output Power 15 W

Efficiency 90% PI-3183-050803

8-116 DPA Seminar 11252003

15 W Multi-output (DI-32)


• Lower power design did not require primary leakage clamp capacitor

• Secondary reset capacitor is not required as Q1 has sufficient gate capacitance to perform this function

• DI-32 was not optimized until after print

– The Schematic shows working design however secondary feedback can be simplified per previous example circuits

• Please see DI-32 for corrected version

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Cross Regulation Performance (DI-32)

Cross Regulation (%) Output Voltage

Voltage Range (VDC)

Load Range

-6 -5 -4 -3 -2 -1 0 1 2 3 4 5 10 15

5 V 36 - 72 20 – 100%

7.5 V 36 - 72 0 – 100%

20 V 36 - 72 100% PI-3184-091602

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25 W Flyback (DI-29)

• 400 kHz to minimize magnetics size

• 87% efficiency at full load 48 V without synchronous rectification


sense components– UV/OV– No-load regulation– Thermal/overload protection


Input Voltage 36 – 75 VDC

Output Voltage 5 V, 7.5 V, 20 V

Output Current 2.4 A, 0.4 A, 10 mA

Output Power 15 W

Efficiency 88%

Ambient Temp Range -40 °C to 65 °C

PI-3185-101003

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25 W, 400 kHz Flyback Example (DI-29)


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Cost Savings

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designing dc to dc converters with dpa-switchtm dc to dc converters with dpa-switchtm • covers...

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