designing advanced asic’s with synopsys design tool suite · 2019-11-19 · predictable success...

Predictable Success

Radiation Hardened Electronics Technology (RHET)

Oct 25th, 2007 Clearwater, Florida

Designing Advanced ASIC’s with Synopsys Design Tool Suite

Synopsys Professional Services Synopsys Inc.

Rick Hayden

© 2007 Synopsys, Inc. (2)

Predictable Success

Agenda

• Today’s Program Management challenges

• Today’s Technical design challenges

• Synopsys Tool Suites

• Synopsys Professional Services

ReusableStandard Hardware

Low PowerConsumption

Operating System

DriversSoftware applications

DigitalHardware Design

AnalogCircuit Design

HW & SWCo-development

Predictable Success

Today’s Program Management challenges


Predictable Success

PM’s Role: Case Study

Sound familiar?


Predictable Success

Uncertainty in Effort Estimates

• Early in the project you can have firm cost and schedule targets or a

firm feature set, but not both.

• Cone of Uncertainty implies that it is not only difficult to estimate

projects accurately in the early stages but theoretically impossible.

Prod Refined Spec RTL Gates GDSIIDefn Defn

100%

75%

50%

25%

0%

-25%

-50%

-75%

Number of unknowns and corresponding

uncertainty in effort estimates through project life

Prod Refined Spec RTL Gates GDSIIDefn Defn

100%

75%

50%

25%

0%

-25%

-50%

-75%

Cone of Uncertainty


Predictable Success

Managing Design Complexity

• Due to the nature of ASICs, nearly every design:

� Complete systems on a single die (SoC)

� Often requires 3rd party IP

� Mixed signal designs are becoming prevalent• SERDES, USB, PCIe, etc.

� Verification is more complex

� Requires leading edge silicon technology

On-Chip Peripheral Bus

Bridge

Micro-processor

DSP

UART GPIO

WiUSB

WiUSB PHY

PCIe

PCIe PHY

SATA

SATA PHY

MemoryController

10GE

XAUI PHY

USB

USB PHY

I2C

10/100/1GE

Micro-processor

DSP

InterruptController

RTC

RAM ROM FLASH

On-Chip High Speed Bus

Arbitration+ Decode+ Control

RTC InterruptController

IP

Bridge

UART GPIO

WiUSB

WiUSB PHY

PCIe

PCIe PHY

SATA

SATA PHY

DDR3/2PHY

MemoryController

10GE

XAUI PHY

USB

USB PHY

I2C

10/100/1GE

AMBA™ AHB/ AMBA 3 AXI

Arbitration+ Decode+ Control

AMBA APB

Micro-processor

DSP

VIPVIP VIP

VIP VIP VIPVIP VIP

VIP

VIP

• Accurate schedule and effort estimation is difficult to make in early

stages of design:

� Design specification may not be solidified

� Unknowns in design flows, libraries, processes

� Integration of 3rd party IP can be underestimated

Predictable Success

Today’s Technical design challenges


Predictable Success

MEMs…

EM

SW

AreaSpeed

Power

Test

DFM

Sign. Int.

More and More Moore’s Law

Ga

tes

Tech. Nodes

Scale

Co

mp

lexit

y

Systemic Complexity

Analog Digital

45nm

65nm

90nm

130nm

180nm

32nm

250nm


Predictable Success

• Interconnect delay, delay due to crosstalk, and delay due to IR drop are more dominant in smaller technologies.

• Post-layout analysis with parasitics is required for accurate modeling.

Design Performance Trends

0%

20%

40%

60%

80%

100%

250nm 180nm 130nm 90nm 65nm

IR Drop

Coupling Capacitance

RC delay

Cell Delay

Impact on Impact on

total delaytotal delay


Predictable Success

Leakage Power Trends

0

50

100

150

200

250

250nm 180nm 130nm 90nm

Po

wer

(Watt

s)

0

25

50

75

100

2P

ow

er

Den

sit

y (

W/c

m)

Leakage Power

Active Power

Power Density

65nm

• Leakage power becomes more dominant at smaller technologies.• Multi-Vth libraries are used to provide balance between

performance and leakage.


Predictable Success

Design for Manufacturability & Yield

8 Reliability: long term current damages your chip

– Electromigration

8 Manufacturability : charge effects results in reducing yield

– Process Antenna Effect

Charge Build Up

Damaged Gate

In sub-micron Wire-to-Wire Cap

Dominates (CW >> CS)

CS

CW

8 Signal Integrity: problems in design that affect your timing

– Crosstalk / Static Noise

– Voltage (IR) drop

Predictable Success

Synopsys Tool Suite


Predictable Success

Syste

mV

eri

log

/ S

ys

tem

CS

yste

mV

eri

log

/ S

ys

tem

C

Veri

ficati

on

IP

(Desig

nW

are

)V

eri

ficati

on

IP

(Desig

nW

are

)

VCS

VMM

LEDA

Formality

VCS

VMM

LEDA

Formality

System StudioSaber

System StudioSaber

NanoSimHSPICENanoSimHSPICE

Discovery™ Verification Platform

Synopsys Design Platforms

ICCPC/Astro

ICCPC/Astro

JupiterXTJupiterXT

Star-RCXTStar-RCXT

HerculesHercules

Po

wer

Co

mp

iler

Po

wer

Co

mp

iler

DF

T

Co

mp

iler

DF

T

Co

mp

iler

DC

TD

CT

Design CompilerDesign Compiler

Des

ign

-W

are

Des

ign

-W

are

Milk

yw

ay

Milk

yw

ay

Galaxy™ Design Platform

Pri

meT

ime S

IP

rim

eT

ime S

I

Design ServicesDesign Services

Predictable Success

DiscoveryDiscovery™™ Verification Verification

PlatformPlatform

Syste

mV

eri

log

/ S

ys

tem

CS

yste

mV

eri

log

/ S

ys

tem

C

Veri

ficati

on

IP

(Desig

nW

are

)V

eri

ficati

on

IP

(Desig

nW

are

)

VCS

VMM

LEDA

Formality

VCS

VMM

LEDA

Formality

System StudioSaber

System StudioSaber

NanoSimHSPICENanoSimHSPICE


Predictable Success

Verification Challenge Fueling Growth

“Validation is the biggest challenge going forward, limiting

our ability to do more complex designs”

Intel

“Over 50% of our chip design resources are now committed

to Verification”

Texas Instruments


Predictable Success

Language Fragmentation

1-2µµµµm .13µµµµm

De

sig

n S

ize

GapGap PropertyProperty

AssertionAssertion

TestbenchTestbench

CoverageCoverage

C++C++

?

?MixedMixed--HDLHDL

VHDLVHDL

VerilogVerilog


Predictable Success

Standardization Opens DFV Age

1-2µµµµm .13µµµµm

De

sig

n S

ize

GapGap PropertyProperty

AssertionAssertion

TestbenchTestbench

CoverageCoverage

C++C++

MixedMixed--HDLHDL

VHDLVHDL

VerilogVerilog

Verification (Simulation)

Design for Verification

Verification (Simulation)

Design for Verification

SystemVerilogSystemVerilog


Predictable Success

Benefits of SystemVerilog for Design

• Easy communication between System Architects, Design Engineers and Verification Engineers

• Enables higher level of abstraction

• Provides code compaction

• Has specific language constructs that reduce mismatches between simulation, synthesis and formal verification tools

• Better Description of Hardware Specific Procedures

• Enhanced Readability

Predictable Success

GalaxyGalaxy™™ Design PlatformDesign Platform

ICCPC/Astro

ICCPC/Astro

JupiterXTJupiterXT

Star-RCXTStar-RCXT

HerculesHercules

Po

wer

Co

mp

iler

Po

wer

Co

mp

iler

DF

T

Co

mp

iler

DF

T

Co

mp

iler

DC

TD

CT

Design CompilerDesign Compiler

Des

ign

-W

are

Des

ign

-W

are

Milk

yw

ay

Milk

yw

ay

Pri

meT

ime S

IP

rim

eT

ime S

I


Predictable Success

Predictable SynthesisTopographical (Physically Aware) Technology

PowerTiming & Area

Enables fastest TTR and Better Start Point for P&REnables fastest TTR and Better Start Point for P&R

• No need for WLMs

• Correlates to post-layout results

• Reduces iterations

• Easily adaptable into existing design flows

MilkywayMilkyway

Sig

noff

Sig

noff

Design Compiler

Design

Compiler

IC

Compiler

IC

Compiler

GalaxyGalaxy


Predictable Success

Next-Generation Place and Route SolutionIC Compiler

Netlist

GDSII

Milkyway

TCL GUI

ConcurrentOptimization

Physical

Power

Physical

Power

PhysicalDFT

PhysicalDFT

Floor

Planning

Floor

Planning

Yield Opt

Yield Opt

SignoffDriven

SignoffDriven

P&RP&R

SI Aware Routing

Traditional Routing

Predictable Success

Synopsys Professional Services


Predictable Success

Global Technical Solutions

Pilot provides a mature, modular

environment and flow to help maximize repeatability, efficiency, and productivity

Functional

Verification

Input QA

Flow Automation

Data Structure

Configuration GUI

Technology

Preparation

Metrics

Reporting

SynthesisDesign For

Test

Design

Planning

Place & Route

Optimization

Chip

Finishing

Pilot Design EnvironmentPilot Design Environment

RTL

GDSII

Remote DesignCenters

Customers, Partners, Consultants

DesignSphere compute infrastructure helps

ensure worldwide team execution

Major DesignCenters

Corporate / CentralData Center

Quality checks and reviews ensure successful executionof projects according to plans

Step 1 Step 2 Step n… Tapeout

Incoming Gates

Outgoing Gates


Predictable Success

Pilot Design Environment Overview

• Open, ready-to-use, VDSM tested

design system

� Configurable for customer-

specific environment

� New utilities for IP & lib-QA,

technology file preparation &

metrics reporting

� GUI for ease of flow setup

• Deployed to customers & used by Professional Services, WW

� Enable consistent multi-site,

multi-project IC development

• Updated & supported by Synopsys Professional Services

Functional

Verification

Input QA

Flow Automation

Data Structure

Configuration GUI

Technology

Preparation

Metrics

Reporting

SynthesisDesign For

Test

Design

Planning

Place & Route

Optimization

Chip

Finishing

Pilot Design EnvironmentPilot Design Environment

RTL

GDSII


Predictable Success

Solutions to Reduce Program Risk

EDA Tool License Shortages

Program Risk SolutionsSolutionsSolutions

��EDA Tool Access by Program

��Scalable Compute Platforms

��Scalable Design Services (ITAR Compliant Resources)

�� Robust, Proven IP Portfolio

Compute ResourceLimitations

Engineering Skills &Resources Shortages

Procurement of Reliable IP


Predictable Success

Typical Responsibilities

Customer Synopsys-Foundry Pilot Flow Honeywell

Honeywell/Synopsys Design Flow

Chip

Specification

Development

SynthesisSynthesis

RTL Design

RTL Refinementand Optimization

Verification

FloorplanFloorplan

PhysicalPhysical

SynthesisSynthesis

ASIC ASIC

FabricationFabrication

PackagePackage

RequirementsRequirements

TestTest

RequirementsRequirements

PackagePackage

DevelopmentDevelopment

TestTest

DevelopmentDevelopment

AssemblyAssembly

TestTest

Screening

Place and Place and

RouteRoute

System

Specification

Development

Design FlowExit

Design FlowEntry DFTDFT

Honeywell-Synopsys Design Flow

1

2

3

Typical Entry Points:1 – Specification2 – RTL3 – Gate-Level Netlist


Predictable Success

Design Collaboration EnvironmentScalable Infrastructure

Synopsys DesignSynopsys Design

CenterCenterCustomerCustomer

Honeywell DesignHoneywell Design

CenterCenter

• Scalable data center

� Server farm with 100’s of CPU’s

� LSF based job launching for parallel computing

� Regular back-ups

� Physically secured and monitored 24x7x365

Same Same

Desktop Desktop

ViewView

CustomerDesign Centers

• Collaborative design infrastructure

• Enables customer, Honeywell and Synopsys engineers to act as single design center

� Use a common Pilot flow

� On-demand availability of tool licenses

� ITAR Compliant

Secureinternet

link

designing advanced asic’s with synopsys design tool suite · 2019-11-19 · predictable success...

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