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19-Oct-2005
Design Trends in deep-submicron CMOS with example of GPS-Receiver
Dr. Srinivasan VenkatramanTexas Instruments Inc., Dallas, Tx.
19-Oct-2005
• In the late 1950s, a new aircraft carrier had 350,000 electronic components, requiring millions of hand-soldered connections – "tyranny of numbers" (Jack Kilby)
- Transforming Nature- Michael E. Gorman, University of Virginia
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Today…
•Shrinking geometries enable more than 10-Million devices per die.–New problems and issues.–New Opportunities for innovation
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Deep-Submicron CMOS-Opportunities
• Shrinking geometries ? more transistors.• Smaller devices ? Higher ft & faster
transistors.• More transistors ? Complex digital
processing and more digital content.• More integration ? The economic drive
of lowering the cost of electronics.
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Deep-Submicron CMOS - Issues• Smaller geometry ? Lower supply voltage.• Smaller devices ? More 1/f noise.• Smaller devices ? More leakage.• Higher digital gate density ? Larger portion
of silicon is taken by analog circuits (Need to shrink, to gain economic edge).
• More integration ? Isolation issues between various sub-modules of the system.
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System-on-chip - Examples• Network processors• Graphics Processors• Bluetooth tranceivers• WLAN transceivers• GPS receivers• GSM transceivers
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System design –Changing paradigms
• What works in regular system design may-not work for SoC.
• The building blocks available are slightly different –– Eg: Transmission lines & stubs are not available easily
on an IC.– Using SAW filters is an expensive option, mainly due to
off-chip interface, pins & board space.
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GPS Receiver architecture
LNA
mixer
Jammerrejectfilter
polyphase
VGA SigmadeltaADC
Digital IFfilter & AGC
LO-I
LO-Q
Chipinput
SYNTH DIV DIVVCO
256MHz 16MHzOSCTCXO
OSC
Antenna
Ceramicfilter
Matchingnetwork
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Front-end
BIAS
RF_in
LO-IM
MIXER_I
MIXER_Q
I-IF-out
Q-IF-out
LNA
Biasing not shown
LO-IP LO-IM
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IF chain signal processing• Deep-submicron process not suitable
for accurate analog filtering
20dBSNR
coarse or nogain step
wider filter Excess noise and variable power level
higherSNR
fine gain stepAccurate filter Fixed power levelVariable signal Level at IF input
Accurate analog processing
Relaxed analog processing
Variable signal Level at IF input
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Jammer reject filter
bias
inp inm
op
bias
bias
om
bias
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PolyPhase Filter
IP
IM
QM
QP
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Passive continuous time delta-sigma ADC
refp
inmou
t
quantizerinp
refm re
fm
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Digital filter architecture
Delta Sigma Modulator
4rth
order Comb
11 tap Half Band
48 tap FIR
261.888M samples/s
65.472 M samples/s
32.736 M samples/s13 tap FIR 16.368 M
samples/s
4 2 2
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Synthesizer architecture
Num. ofPrescaler cycles in one compare
multiplication (M)
F-compare
? -acc
?
?
-
+
DIV 4/5
Main digital divider (M) DIV 5 timer
Midpoint offset
Varacter
DIV 2
Digital tuning loop
Main dividers
Loopfilter
PFDCharge pump
Type-II analog loop
VCO
Capacitor array
• Type-II analog integer-N PLL• Type-I digital tuning loop for PVT calibration of VCO Freq.
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VCO
digital tune
vtune
bias
• LC tank with metal-spiral and MOS varactor
• Switched capacitor (MIM) array to augment the tuning range
• Cross-coupled MOS gain stage for negative resistance
• Self-tracking bias to minimize supply pull on VCO frequency
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Challenges• Low Supply Voltage (1.4 volts). • SoC integration of RF + Base-band.• Achieve high-linearity of RF front-end.• Choice of pin-out to minimize package coupling.• Floor-plan to minimize influence of digital noise on RF
circuits.• Isolation of supplies and grounds (power supply coupling).• IR drop analysis and isolation of high-activity regions.• Minimize power-supply spikes and use de-coupling
capacitors to provide switching current.• Judicious use of guard rings to isolate noise.
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Receiver response
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De-sense with out-of-band jammers
2.05
2.10
2.15
2.20
2.25
2.30
2.35
2.40
2.45
1850 1860 1870 1880 1890 1900 1910
Blocker Frequency [MHz]
NF
[dB
]
WCDMA/CDMA1900
Blocker OFF
• Noise figure without any jammer is 2.05 dB • With -31dBm jammer at 1850MHz the Noise figure goes up to 2.3 dB• With stronger LO drive (elevated supply) the desense is < 0.1dB
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Phase noise at LO/4
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Measured Performance
1.8 dBNoise Figure38 dBGain
5dBmIIP3 (@ 1576MHz and 1576.5MHz)
38dBDynamic RangeADC
0.1dBPCS band jammerdesense
-11 dBS11
LNA + IRM
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Performance Continued…
12.8 mm2Die Area
100msLock Time
2 degIntegrated rms Phase error
-113dBc/HzPhase noise at 1MHz-88dBc/HzPhase noise at 100KHz
60mA @ 1.4VPower18dBImage rejection
FULL RECEIVER-60dBcReference Spur
SYNTHESIZER
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Single-Tone Response of Receiver
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Spot Noise-Figure of Receiver
2.823.683.543.062.26NF at ADC output (dB)
1.51
8.87
500
1.51
2.63
250
1.51
2.59
0
1.51
2.49
-250
1.51Front-end NF (dB)
8.43
-500
NF (dB) at Baseband
Basebandfreq.(kHz)
• NF at ADC output is degraded due to high speed digital output• NF from base-band is better as digital test buffers are off• NF within the narrow bandwidth of base-band filter is good• Indicates substrate coupling does not degrade the RF performance
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ADC
IF
VCOPLL
LNAMixer
LDO
Base-bandCore
Memory
Memory
ARM
digitalfilter
GPS Receiver –Texas Instruments13 mm2 –0.09 µM CMOS (2005)
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Single-chip GPS receiver ST-Microelectronics23 mm2 – 0.18 µM CMOS (2004)
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Single-chip GPS Receiver - Sony Corporation40 mm2 - 0.18 µM CMOS (2004)
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Conclusion
• It is possible to get high-performance SoC for complex functions.
• Effective isolation methods are necessary before such SoC products can be widely used.
• Shifting analog gain and processing into digital domain is still necessary for SoCs.
• Regular 90nm CMOS process can still be used, provided design innovations address the shortcomings.
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Open Problems• Power dissipation and power-density is high.• Thermal issues – too much heat generation.• Isolation issues – Getting enough isolation is still a
black-magic art. Modeling & design methods need to improve, so that it can be routinely achieved.
• New architectures that use wider bandwidth (faster transistors, but lower capacitance and area are needed).
• Driving interfaces takes power – be it air-interface or off-chip interfaces. RF power amplification needs to be effectively addressed.
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References• A 23mm2 Single-Chip 0.180µm CMOS GPS Receiver with
28mW- 4.1 mm2 Radio and CPU/DSP/RAM/ROM• G.Gramegna, M.Losi, P.Mattos, S.Das, M.Franciotta,
N.G.Bellantone, M.Vaiana, V.Mandara, M.Paparo.• IEEE CICC 2004,
• A Complete Single-Chip GPS Receiver With 1.6-V 24-mW Radio in 0.18-m CMOS
• Takahide Kadoyama, Norihito Suzuki, Member, IEEE, Noboru Sasho, Hiroshi Iizuka, Ikuho Nagase, Hideaki Usukubo, and Masayuki Katakura, Member, IEEE
• IEEE JSSC, VOL. 39, NO. 4, APRIL 2004