design of power correction circuit using tda4862 - infineon

Power Management & SupplyPower Management & SupplyPower Management & SupplyPower Management & Supply

Version 1.0 , September 2001

Design Note

DN-SMPS Singlestage

CoolSET

Design of 30W Off-Line SMPS using CoolSET ICE2B265

Authors: Yew Ming Lik

Junyang Luo

Meng Kiat Jeoh

Published by Infineon Technologies AGhttp://www.infineon.com

N e v e r s t o p t h i n k i n g


of 22 DN-SMPS Singlestage

Contents:

1. INTRODUCTION .................................................................................................................................3

2. BLOCK DIAGRAM..............................................................................................................................3

3. POWER MANAGEMENT......................................................................................................................4

4. START-UP DELAY ..............................................................................................................................4

5. IMPROVED CURRENT MODE..............................................................................................................5

6. SOFT-START .....................................................................................................................................6

7. OSCILLATOR AND FREQUENCY REDUCTION......................................................................................7

8. CURRENT LIMITING ..........................................................................................................................8

9. LEADING EDGE BLANKING ...............................................................................................................8

10. PROPAGATION DELAY COMPENSATION .......................................................................................8

11. PROTECTION UNIT ..........................................................................................................................9

12. OVERLOAD + OPEN LOOP WITH NORMAL LOAD AND AUTO RESTART MODE.............................9

13. OVERVOLTAGE DUE TO OPEN LOOP WITH NO LOAD....................................................................10

14. 30W DEMO POWER SUPPLY BOARD .........................................................................................11

15. DESIGN OF THE POWER SUPPLY ....................................................................................................12

15.1. Determine input capacitor C3 and minimum DC input voltage V1MIN ..................................12

15.2 Transformer Calculation.......................................................................................................12

15.3 Current Sense Resistor ..........................................................................................................15

15.4 Soft-start capacitor C7...........................................................................................................15

15.5 Capacitor at VCC C6...............................................................................................................15

15.6 Start-up Resistor R2 and R3 ...................................................................................................16

15.6 Control Loop Design .............................................................................................................16

16. SUMMARY.....................................................................................................................................18

REFERENCES.......................................................................................................................................20




Yew ming lik, Junyang Luo and Meng Kiat Jeoh

Infineon Technologies Asia Pacific Pte. Ltd.168 Kallang Way,Singapore 349253

Email: [email protected], [email protected],[email protected]

1. Introduction

The CoolSET ICE2B265 is an integrated pulse width modulator with built in CoolMOS. It is aninexpensive controller combined with the CoolMOS power switch with which designers canobtain all the stringent requirements imposed on the present modern Switched Mode PowerSupply (SMPS) like very low standby power, few external components count and minimizedPCB size. This application note provides beside functional description of the ICE2B265, itpresents also the design of simple low cost and high efficient 30W Flyback SMPS circuit.

2. Block Diagram

Fig.1. Block diagram of ICE2B265P

The control section of the CoolSETprovides several special enhancements tosatisfy the needs for low power standbyand protection features. It consists of 5main units, the Power Management, the

Softstart, the Improved Current Mode, theCurrent Limiting, the Standby and theProtection Unit. The Standby Unit enablesthe frequency reduction to lower the powerconsumption in standby mode. The

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mailto:[email protected]



frequency reduction is limited to 21kHz toavoid audible noise. In case of failuremodes like open loop, overvoltage oroverload due to short circuit the deviceswitches into Auto Restart Mode, which iscontrol by the Protection Unit. With thepatented Propagation DelayCompensation circuit integrated in theCurrent Limiting Unit, the peak currentlimitation can be controlled precisely. Itleads to more cost efficient dimension ofthe transformer and the secondary diode.

3. Power Management

Fig.2. Power Management Unit

Fig.2 shows the Power Management Unitof the IC. The external supply voltage VCCis monitored by the Undervoltage Lockout.The external capacitor CVCC is charged upby the current through the RSTART-UP, whenthe SMPS is plugged to the main line. TheIC remains inactive before VVCC reachesthe on-threshold VCCON=13.5V. The currentconsumption of the IC at this moment ismax. 55uA. When the on-threshold isexceeded, the IC is activated:

The internal bandgap generates areference voltage VREF=6.5V to supplythe internal circuit.

The internal Error-latch in theprotection unit is reset by the PowerUp Reset. The Error-latch flip-flop is

then ready to shut down the gate driveif the Protection Unit is activated.

The soft-start transistor switch T1 isreleased by the Power-Down Reset.The current through RSOFT-START startsto charge the external soft-startcapacitor CSOFT-START. The soft-start isthen activated.

To avoid uncontrolled ringing at switch-ona hystersis at the Undervoltage Lockout isimplemented which means that switch-offis only after active mode when VCC fallsbelow 8.5V.

When VCC falls below the off-thresholdVCCOFF=8.5V the internal reference isswitched off and the Power Down Resetlet the transistor switch T1 to dischargethe soft-start capacitor CSOFT-START. Thus itis ensured that the soft-start is alwaysactivated at every switch-on.

4. Start-up delay

During startup, CVCC is charged by thecurrent through RSTART-UP. The IC isactivated only when the VCC reaches theon-threshold of VCCON=13.5V. Because ofthe very low IC current consumptionbefore activation, high value startupresistor can be used to minimize powerloss in start-up resistor. The value ofRSTART-UP and CVCC will effect the startupdelay time, which can be estimated byusing equation as follow:

1VCCUPSTART

IN1

CCONVCCdelay

IR

VVCt

−

×=

−

(1)

tdelay is the duration of the startup time fromthe moment the SMPS is plugged to themain line until the IC is activated. V1IN isthe rectified line input voltage and IVCC1 isthe current consumption of the IC beforeactivation. Fig.3 shows the tstart delay of theactual SMPS with RSTART-UP = 2 x 470kΩ,CVCC=47µF and V1IN =380V. (1) indicatesthat the start-up delay time depends notonly on the main input voltage but alsomainly on the value of RSTART-UP and CVCC.The tdelay can be shorten by reducing theRSTART-UP value. However, the loss atRSTART-UP will increase. It has to becompromised between shorter startupdelay time and loss at startup resistor.



Startup circuit with transistor switch can beimplemented to achieve startup withoutlosses and constant shorter delay time.

RSTART-UP = 1.5MCVCC = 47uF

V1IN = 380V

VCC

13.5V

tdelay = 3s

Fig.3. Start-up delay time.

5. Improved Current Mode

In Current Mode the primary current issensed by the sense resistor RCS (Fig. 4).The sense voltage VCS is amplified 3.65times for comparison with FB signal by thePWM Comparator. The current flow isterminated by resetting the PWM-Latch,when the sense voltage reaches the levelof the FB signal, which is the programlevel of the output control loop.

Fig.4. Current Mode Control

Thus, the turn-on time of the powerMOSFET as well as the peak primarycurrent is well defined by the level of theFB signal. For flyback converter withdiscontinuous current operation the powerstored in the primary inductor isrepresented by the equation

2PifL

21P ×××= (2)

Where P is the power stored in the primaryinductor, L is the primary inductor, f is theswiching frequency and IP is the peakprimary current.

As can be seen, the line-input voltagedoes not appear in (2). One of theadvantages of the Current Mode is that theline variation does not influence theregulation of the output voltage. However,the Current Mode is extremely susceptibleto noise on the sense voltage. A noisespike is generated each time the powerMosfet switch is turned on which mightturn off the driver immediately especiallywhen the power is small and the FB signalis low.

To improve the Current Mode during lightload, a voltage ramp is implemented in theIC.

Fig.5. Improved Current Mode

The amplified current sense voltage vCS issuperimposed on the voltage ramp, whichis built by the switch T2, the voltage sourceV1 and 1st order low pass filter composedof R1 and C1 (see Fig.5).

Fig.6. Normal Load Condition

Rcs

CoolMOS

L1

Vcs

Ip

R

S Q

Q

GateDriver

PWMComparator

To Soft-Start Comparator

FB

x 3.65

PWMLatch

V1in

R110k 0.8V

V1

C120pFT2

C50.3V

Osci

2

5

3Isense

Drain

Rcs

CoolMOS

L1

Vcs

Ip

R

S Q

Q

GateDriver

PWMComparator

To Soft-Start Comparator

FB

x 3.65

PWMLatch

V1in

C50.3V

2

5

3Isense

Drain



Fig.6 shows the effect of the VoltageRamp in normal load condition. The switchT2 is opened at the falling slope of theoscillator. It enables the Voltage Ramp torise. The Gate Driver turns on the powerMOSFET when the Voltage Ramp reaches0.3V. The primary current starts to flowand is sensed by RCS. The current sensevoltage VCS is amplified 3.65 times by thePWM OP, which is then superimposed onthe Voltage Ramp. The current flow isterminated when the amplified sensevoltage on the Voltage Ramp reaches theFB voltage level.

In case of light load (see Fig.7) or no load,the current sense voltage VCS is so smallthat only the Voltage Ramp remains as awell defined signal for the comparison withthe FB-signal.

Fig.7. Light Load Conditions

The slope of the Voltage Ramp thencontrols the turn-on time of the Gate

Driver. The Gate Driver is turned on onlywhen the Voltage Ramp exceeds 0.3Vdue to the Comparator C5. The turn-ontime can then be continuously reduced tozero by decreasing VFB below thatthreshold.

6. Soft-Start

Fig.8. Soft-Start

The Soft-Start voltage VSOFTS is generatedby charging the external capacitor CSOFTSthrough the internal pullup resistor RSOFTS(see Fig.8). The Soft-Start comparatorcompares the Soft-Start voltage VSOFTS atthe negative input with the ramp voltage ofthe superimposed Voltage Ramp at thepositive input. In Soft-Start phase VSOFTS isalways smaller than the Feedback VoltageVFB. In this case VSOFTS defines the pulsewidth of the Gate Driver through the Soft-Start Comparator by resetting the PWM-Latch. The Soft-Start phase is completedwhen VSOFTS reaches 5.3V (Fig.9). TheSoft-Start time is then defined by

SOFTSSOFTSSTARTSOFT CR69.1T ××=− (3)

The transistor switch T1 at Soft-Start iscontrolled by the Power Down Reset. It isto ensure that the Soft-Start is alwaysactivated at the restart of the IC afterpower down or in Auto Restart mode.

0.8V

0.3V

FB

Amplified Vcson voltage ramp

Voltage ramp

Gate Driver

T = 10usVosc

ton

tonmax

0.8V

0.3VFB

Voltage ramp

Gate Driver

T = 50usVosc

ton

tonmax

Rcs

CoolMOS

L1

Vcs

Ip

R

S

Q

Q GateDriver

PWMComparator

PWMLatch

V1inSoft-StartComparatorRsofts

6.5V

T15.6V

FromPower DownReset

FB Voltage RampandAmplified Vcs

Csofts

Drain

IsenseIsense3

5

1

2

SoftS Vsofts



Fig.9. Soft-Start Phase

The Soft-Start voltage VSOFTS is used notonly for minimization of current andvoltage stresses on the external powerMOSFET switch during start-up, it is alsoused for activation of the Protection Unit(Fig.10).

Fig.10. Activation of Protection Unit

When the Soft-Start phase is over (VSOFTS> 5.3V), the Error Latch will be activatedby Comparator C4 if the feedback voltageVFB does not drop below 4.8V, whichmeans that the output voltage VOUT at thesecondary side of the SMPS does notreaches its nominal level. To ensureproper start-up of the SMPS, the durationof the Soft-Start phase has to be longenough to enable VOUT to rise to itsnominal value. This will cause the control

loop to pull down the level of the feedbacksignal VFB below 4.8V (see Fig.11).

Fig.11. Start-up Phase

7. Oscillator and FrequencyReductionThe oscillator, which generates theswitching frequency F=67kHz, isintegrated in the IC. The oscillator isadjusted so that the Gate driver pulse canreach a maximum duty cycle of DMAX =0.72.The frequency of the oscillator can beinfluenced by the feedback voltage VFB asshown in Fig.12. This feature allows aSMPS to operate at lower frequency atlight loads thus lowering the switchinglosses while maintaining good crossregulation performance and low outputripple. The power consumption of thewhole SMPS can be reduced veryeffectively at light load. The minimalreachable frequency is limited to 20kHz toavoid audible noise in any case. f

VFB

Fig.12. Frequency Reduction vs VFB

Gate Driver

5.3V5.6V

Vsofts

Tsoft-startt

t

Rcs

MOSFET

L1

Vcs

IpR

S Q

Q

GateDriver

PWMLatch

V1in

Rsofts6.5V

5.6V

FB

Csofts

Rfb

6.5V

R

S

Q

Q

C4

5.3V

G2

Power UpReset

4.8V

C3

Clock

Error Latch

2

1

3

5

SoftS

Drain

Isense



8. Current Limiting

Fig.13. Current Limiting

The cycle by cycle current limiting isperformed by the Current LimitComparator (see Fig.13). The primarycurrent IP is converted into a sense voltageVCS by an external sense resistor RCS. Thesense voltage VCS goes through the 200nsLeading Edge Blanking before reachingthe Current Limit Comparator. When VCSexceeds the internal threshold voltageVCSTH, the Current Limit Comparatorimmediately turns off the Gate Driver viathe PWM Latch. A Propagation DelayCompensation is added to the CurrentLimiting circuit to avoid excessiveovershoot of the primary current,especially at the high line voltage (refer tochapter 10 Propagation DelayCompensation).

9. Leading Edge Blanking

Fig.14. Leading Edge Blanking

Each time when the CoolMOS is switchedon a leading spike is generated due to the

primary-side capacitance and secondary-side rectifier reverse recovery time (Fig.14). This spike causes a premature turn-off of the Gate Driver if it exceeds thethreshold voltage VCSTH. To avoid it, thespike is blanked out with a time constantof tLEB = 220ns. During the blanking timethe Gate Driver can not be switched off bythe Current Limit Comparator.

10. Propagation DelayCompensation

In case of overcurrent detection, that iswhen the sense voltage VCS reaches thethreshold voltage of the Current LimitComparator VCSTH, the shut down of theinternal CoolMOS is delayed due to thepropagation delay of the circuit betweenthe current sense input ISENSE and the GateDriver output. This delay causes anovershoot of the peak primary currentIPPEAK. The overshoot is seriousparticularly at high input line voltage.Fig.15 shows an example of differentcurrent overshoots at two different linevoltages. The example assumes that theprimary inductance is 500µH, the currentsense resistor RSENSE=1Ω, the propagationdelay time tPROP DELAY=200ns and the inputline voltages after rectification are V1IN1=100V and V1IN2 =370V.

Fig.15. Current overshoot

The result of the example obviously showsthat if the current sense threshold VCSTH isset at a constant level VCSTH = 1V, thecurrent overshoot IOVERSHOOT2 at high lineinput voltage of VIN2 = 375V and at tDELAY =200ns is 15% higher than the actualcurrent limit IPLIMIT.

1us 5us

Vcs, Ip

0.2V

1V

10us 15us

V IPLIMITCSTH =

IOVERSHOOT1OVERSHOOT2I

L = 500uH, Rcs = 1 OhmV1IN1 = 100V dI1p/dt = V1N1/L = 0.2A/usV1IN2 = 375V dI1p/dt = V1N2/L = 0.75A/us

dI1p/dt = 0.2A/us dI1p/dt = 0.75A/us

1A1.04A 1.15A

tdelaytdelay

Rcs

CoolMOS

L1

Vcs

Ip

GateDriver

V1in

10k

D1Leading EdgeBlanking200ns

Vcsth

Current LimitComparator

PropagationDelayCompensation

R Q

QS

Clock PWM LatchPWMComparator

Isense

Drain

3

5



The Propagation Delay Compensationwhich is done by means of a dynamicvolatge threhold VCSTH as shown in Fig.16is integrated in the IC to minimize theovershoot.

Fig.16. Dynamic Voltage Threshold VCSTH

At high line input voltage, when the slopeof the current sense voltage VCS issteeper, the Gate Driver is switched offearlier due to the lower VCSTH. The effect ofthe overshoot is then compensated.

The Propagation Delay Compensation inthe IC is designed so that the tolerance ofthe internal current limiting is at +/- 5%.The propagation delay time iscompensated over temperature within arange of at least

dtdV1

dtdIR0 CSP

CS ≤×≤ (4)

In this way, the IC is able to accuratelylimit the overcurrent (see Fig.17).

Fig.17. Overcurrent Shutdown

11. Protection Unit

An overload, open loop, overvoltagedetection and a thermal shutdown areintegrated within the Protection Unit (seeFig.1, Block Diagram). If the ProtectionUnit is activated, the Error Latch is set thatdisables the external power MOSFET aftera blanking time of 5µs. The blanking isused to avoid mistriggering of the ErrorLatch by voltage spikes during normaloperation mode.

12. Overload + Open Loop withnormal load and Auto RestartMode

Fig.18. Auto Restart Mode

Fig.18 shows the Auto Restart Mode incase of overload or open loop with normalload. The detection of open loop oroverload is provided by the ComparatorC3, C4 and the AND-gate G2 (see Fig.19).

During operation at normal load the supplyvoltage of the IC VCC is in the range of

1us 5us

Vcs, Ip

0.2V

1V, 1A

10us 15us

V IPLIMITCSTH =dI1p/dt = 0.2A/us dI1p/dt = 0.75A/us

tdelaytdelay

VCSTHdynamic

VOSC

ton

ton,max

Tsw

VCS

0.95V0.9V

1V1.05V

1.1V

1.2V

1.3V

dVcs/dt[ V/us ]0.2 0.6 1.0 1.4 1.8

Without compensationWith compensation

+/- 5%Tolerance


of 22

8.5V and 13.5V, the Soft-Start voltageVSOFTS is above 5.3V and the

Fig.19. FB-Detection

feedback voltage VFB stays lower than4.8V. At this time the Comparator C4 hasreleased one of the input of the AND-gateG2. The comparator C3 is now able to setthe Error-Latch in case of open loop oroverload, which leads the feedbackvoltage VFB to rise above 4.8V. 5µs afterthe VFB reaches the threshold voltage of4.8V, the Gate Driver is terminated. TheSMPS stops to operate which causes thesupply voltage of the IC VCC to drop. TheIC is turned off when VCC falls to VCCoff =8.5V. At this time the external soft-startcapacitor CSOFTS is discharged by theinternal switch T1 due to the Power DownReset and the consumption current of theIC is reduced to maximum 55µA. TheSMPS then goes into Auto Restart Mode.The VCC increases again by charging thecapacitor CVCC through the Start-upResistor RSTART-UP during the IC is inactive.When it reaches the turn-on thresholdVCCon =13.5V, the IC is turned on again.The Error Latch is then reset by the PowerUp Reset and the internal pull-up resistorRSOFTS starts to charge the external Soft-Start capacitor CSOFTS to start the Soft-Start Phase. During Soft-Start Phase thedetection of overload and open loop by C3and G2 is disabled by the Comparator C4..The Soft-Start Phase ends with the Soft-Start voltage VSOFTS ≥ 5.3V. If the overloador open loop failure is not removed after

the Soft-Start Phase, the Error Latch isactivated and the SMPS goes into AutoRestart Mode again.

13. Overvoltage due to open loopwith no load

Fig.

Fig.20 showsopen loop anof this failurevoltage as wAdditional coAND-gate G1this failure mo

Fig.21

Rcs

CoolMOS

L1

VcsIp

R

S Q

QGateDriver

PWMLatch

V1in

Rsofts

6.5V

5.6V

FB

Csofts

Rfb

6.5V

Vsofts

R

S

Q

Q

C4

5.3V

G2

Power UpReset

4.8V

C3

Clock

Error Latch

T1

23

5

1SoftS

Drain

Isense

Rsofts

6.5V

5.6V

Vcc

Csofts

Vsofts

16.5V

C1

T1

7

1SoftS

16.5

DN-SMPS Singlestage

20. Auto Restart Mode

the Auto Restart Mode ford no load condition. In case mode the SMPS outputell as the VCC increases.

mparators C1, C2 and the are implemented to detectde (see Fig.21).

. Overvoltage Detection

Rcs

CoolMOS

L1

VcsIpR

S Q

QGateDriver

PWMLatch

V1in

R

S

Q

Q

C4

5.3V

G2

Power UpReset

Clock

Error Latch

3

5

Drain

Isense



The overvotage detection is provided byComparator C1 only when the Soft-Startvoltage VSOFTS is below the threshold ofthe Comparator C2 at 4.0V and the voltageat pin FB is above 4.8V. During thisovervoltage detection phase ComparatorC1 can set the Error Latch and terminatesthe Burst Phase earlier during AutoRestart Mode when VCC exceeds 16.5V.Once the Soft-Start phase is over, whichmeans that the VSOFTS is above 4.0V, theovervoltage detection by C1 is disabled.This will enable the VCC to vary in therange of 8.5V to 21V caused by outputload changes at normal operating mode.

14. 30W Demo Power SupplyBoard

Fig.22 shows a very simple and low cost30W switching power supply circuitryutilizing the ICE2B265P. It is designed forused as the power supply of a DigitalPhoto Printer.

The specification of the circuits:

Input voltage range

85 – 265 VAC 50/60Hz

Output

18V/1.67A

Maximum output power

POMAX =30W

Input power at standby mode

PIN ≤≤≤≤ 0.5W at PO = 0W and VIN = 240Vac

Efficiency

ηηηη ≥≥≥≥ 80%

F12A

VAR1

C10.1u/275V

C20.1u/275V

EMI1EV28-3.0

RT1NTC

BR1RS406

C368uF/400V

R168k/2W

D2UF4001

C410nF

R2470k/0.5W

IC1SFH617-2

R140.47

R422C7

1uF

C647u/25V

C80.1u

C52.2nF

D31N4148

R510

CY12.2nF/250V

R61k

IC2TL431

C9120pF

R8220k

C1047nF

R924k

R113.9k

18V/1.67A

N1L2

C11220pF/1kV

85V - 265V

TR1EF25/N67

GND

Vo1

D1MUR520

C121000uF

L11.5uH

C14220uF

25V

C131000uF

25V

25V

ICE2B265

FB

VCC

GND

1

2 3

4

8

ISENSE

SOFTST

7

DRAIN

NC

6

5IC3

R3470k/0.5W

Fig.22. 30W SMPS Demoboard using CoolSET ICE2B265011005 - M.K.Jeoh



15. Design of the Power Supply

15.1. Determine input capacitor C3 andminimum DC input voltage V1MIN

To choose the value of the inputcapacitor C5 the following rule of thumbis applied:

C5 = 2 to 3 µF per W for 100/115VAC oruniversal input.

C5 = 1µF per Watt for 230VAC.

C5 = 68uF is selected for this design. Theminimum DC input voltage V1MIN (seeFig.24) at the lowest line voltage of 85V isa very important parameter for thecalculation of the transformer. It can beobtained with good approximation by thefollowing equations:

5

IN2PK,ACMINMIN1 C

W2VV ×−= (5)

VACMIN,PK is the minimum peak inputvoltage, whereas WIN is the energy whichis discharged out of C5.

2VV ACMINPK,ACMIN ×= (6)

The discharged energy WIN is equivalentto the required peak output power POPK forthe duration of the discharge time TL/2 –tC.

)t2T(PW C

LOPKIN −×=

ηηηη (7)

Fig.23 Input Voltage Ripple

Assuming that the conduction time of thebridge rectifier diodes is about 3 ms andsubstitute the specified values in (5), (6)and (7), we obtain:

V1202V85V PK,ACMIN =×= (8)

Ws26.0W

)ms32ms20(

8.0W30W

IN

IN

=

−×= (9)

V82VuF68

Ws26.02)V120(V

MIN1

2MIN1

=

×−= (10)

Taking the voltage drop at the bridgerectifier into consideration, the V1MIN shouldthen be:

V1MIN = 80V.

15.2 Transformer Calculation

15.2.1. Maximum Duty Cycle

The transformer is designed so that theSMPS is operated in discontinuous currentmode for the whole operating range.

The maximum duty cycle dMAX at minimuminput voltage V1MIN is chosen as

dMAX = 0.5 (11)

15.2.2 Reflected Output Voltage

The reflected output voltage VR is thereflected value of the secondary voltageacross the primary winding. It can beobtained by the equation

( )DSMIN1MAX

MAXR VV

d1dV −×−

= (12)

The Drain-Source voltage VDS of theinternal CoolMOS is negligible due to thesmaller RDSON. VR is then:

V80V805.01

5.0VR =×−

= (13)

VACMIN,PK

1MINV

tC

L

L

T

1/TL = FL = AC Line FrequencytC = Conduction Angle of the Bridge DiodePo = Output Powern = efficiency



15.2.3 Maximum Primary Peak and RMS Current

The maximum primary peak current I1PKMAXis propotional to the maximum outputpower. It can be derived as follow:

MAXMIN1

OMAXPKMAX1 dV

P2I××

×=ηηηη

(14)

Substitute the known values of POMAX,V1MIN, dMAX and the efficiency η into (14),I1PK becomes:

A875.15.0V808.0

W302I PKMAX1 =××

×= (15)

The maximum primary RMS current canbe calculated from I1PK,MAX and dMAX:

3dII MAX

MAX,PK1MAX,RMS1 = (16)

A77.035.0A875.1I MAX,RMS1 == (17)

15.2.4 Primary Inductance L1

Primary inductance can be determined bythe energy equation of the flybacktransformer defined below:

fIP2L 2

MAX,PK1

OMAX1

ηηηη= (18)

f is the switching frequency of the SMPSwhich is around 67kHz.

H320kHz67A875.18.0

W302L 21 µµµµ≈××

×= (19)

15.2.5 Number of Primary turns

For this design, core size of EF25 isrecommended due to its low cost and easyavailability. For 67kHz operation, EpcosN67 material is a good choice.

In the discontinuous current modeoperation, at switching frequency of67kHz, the maximum flux density in thecore BMAX is usually limited by the coreloss. To keep the loss in the core atacceptable level (see Epcos datasheet,

N67 Core loss vs frequency), BMAX = 0.2Tis chosen for the calculation of the numberof primary turns N1.

MINMAX

MAX,PK111 AB

ILN

××

= (20)

AMIN is the minimum cross sectional areaof the core. For EF25, AMIN = 51.5mm2.

605.512.0

2320N1 ≈×

×= (21)

The required core gap LGAP to achieve theprimary inductance L1 with the number ofprimary turns N1 can be calculated byusing the equation given in Epcos databook for “Ferrites and Accessories”

2K1

21

1GAP 1KN

LL

×= (22)

K1 and K2 are the core-specific constants.For EF25, K1=90, K2=-0.731 are specifiedin the datasheet. In the calculation L1/N1

2

has to be in the dimension of nH. Theneeded core air gap is then

mm02.1L

mm906010320L

GAP

731.01

2

3GAP

=

××=

− (23)

15.2.6 Number of Secondary Turn

The number of turn for the secondaryoutput can be derived from the reflectedoutput voltage VR in (13) and the numberof primary turns N1. During the flybacktime all windings will have the same voltper turn VT:

turnV33.1

turns60V80

NVV

1

RT === (24)

The number of turns NO1 for 18V-outputVO1 is then:

T

D1O1O V

VVN += (25)



VD is the output diode forward voltagedrop, which is typically about 1V.

1433.1

118N 1O ≈+= (26)

The bias voltage for the VCC should bearound 15V. The number of turn for thebias winding is then:

1233.1

16V

VVNT

DBIASBIAS ≈=+= (27)

15.2.7 Output Rectifier Diodes

To select the proper output rectifier diode,the maximum peak inverse voltage acrossthe diode VD1,PK has to be defined. VD1,PKcan be obtained by the equation definedbelow:

×+= MAX1

1

1O1OPK,1D V

NNVV (28)

whereas V1MAX is the maximum DC inputvoltage. The calculation result is:

V5.105V

)V3756014(V18V

PK,1D

PK,1D

=

×+=

The reverse voltage rating of the selecteddiode VDR should be greater than 1.25xVDPK and the rated DC current has to be atleast 3 times the maximum output current.MUR520 is chosen for used in this design.

15.2.8 Maximum Secondary Peak and RMS Current

The maximum secondary peak and RMScurrents are propotional to the maximumDC output current as follows:

MAX

OMAXMAX,OPK d1

I2I−

= (29)

3d1II MAX

MAX,OPKMAX,ORMS−

×= (30)

IOMAX is the maximum DC output current,IOPK,MAX is the maximum peak outputcurrent and IORMS,MAX is the maximum RMS

output current. The results of thecalculation is listed in Table 1.

SecondaryOutput

Max. PeakCurrent

Max. RMSCurrent

18V/1.67A IO1PK,MAX =6.68A

IO1RMS,MAX =2.73A

Table 1. Max. Peak and RMS Output Current

15.2.9. Output Capacitors

Output capacitor selection is dominated bythe RESR (equivalent series resistance) andthe ripple current rating of the capacitor.The ripple current, which flows through theoutput capacitor, can be calculated asfollows:

2OMAX

2MAX,ORMSRIPPLE,O III −= (31)

The ripple current in the output capacitorof the 18V/1.67A will then be:

A16.2IA67.173.2I

RIPPLE,01

22RIPPLE,1O

=

−= (32)

The Epcos datasheet of her B41858-series aluminum electrolytic capacitorshows that the rms current rating of a1000µF/25V capacitor at 100kHz switchingfrequency and 105OC ambient is 1.69A. 2pieces of this capactors (Fig.22) have tobe used to accommodate the requiredripple current of VO1. The RESR of thesecapacitors are specified as 0.034Ω. Theoutput ripple voltage caused by theparallel of these two RESR, which is RESRTOT= 0.017Ω, is then:

V11.0017.0A68.6VRIV

RP,1O

ESRTOTMAX,PK1ORP,1O

=×=

×=

ΩΩΩΩ (36)

This switching ripple voltage is furtherreduced by the additional L-C filter (L3 andC14 in Fig.22). The 220µF/25V with RESR =0.12Ω is chosen for C14. To eliminate thepole in the control loop caused by the L1-C14 filter, L1 has to be around 1.5µH. Withthis L1-C14 values combination, VO1,RP isreduced to:



mV18

V12.0105.1672

12.011.0

RLf2RVV

3

ESR4

ESRRP,1O

'RP,1O

≈+××

×=

+×=

−ππππ

ππππ

(34)

The switching ripple voltage V’O1,RPappears at the output terminal has beenattenuated to around 18mV.

15.3 Current Sense Resistor

The current sense resistor (R14 in Fig.22)is defined by the maximum primary peakcurrent and the minimum threshold voltageof the Current Limiting VCSTHMIN.

ΩΩΩΩ45.0A2

V95.0IVR

MAX,PK1

CSTHMIN14 ≈== (35)

Since the maximum loss occurred in R14can be:

W26.0W45.0765.0P

RIP2

MAX14R

142

MAX,RMS1MAX14R

=×=

= (36)

a 1W low inductance resistor isrecommended.

15.4 Soft-start capacitor C7

As mentioned in chapter 6 “Soft-Start” onpage 4 and 5, the duration of the soft-startphase TSOFT-START has to be long enough toensure proper start-up of the SMPS. Thatmeans VO1 has to be at 18V before VSOFTSreaches 5.3V (see Fig.11 on page 5, TSOFT-

START > TSTART-UP).

To estimate the TSTART-UP, the availablepower during the soft-start phase, whichcharges the output capacitors, has to bedefined. The total value of all capacitors atthe output is:

F2220CCCC 141312'

1O µµµµ=++= (37)

In case of hard-start (if soft-start does notexists), the power which will charge C’O1is:

2

14

CSTHMIN1

'1O R

VfL21P

××××= ηηηη (38)

W45.095.01067320

218.0P

23'

1O

×××××= −

P’O1 = 38.2W

Assuming that the charge-up power to theC’O1 rises linearly during the soft-startphase, the charge power is then only halfof 38.2W. TSTART-UP, which is needed toraise the voltage VO1 to 18V, can then beestimated:

'1O

'1O

21O

UPSTART P5.0CVx

21T ×=−

(39)

ms8.18s2.38

222018T2

UPSTART ≈×=− µµµµ

In the application circuit of Fig.22, theexternal soft-start capacitor C7 = 1µF isrecommended. The internal soft-startresistor RSOFTS = 50kΩ is specified on thedatasheet of the IC. The soft-start timeTSOFT-START can then be calculated using(3):

ms5.84ms15069.1T STARTSOFT =××=− (40)

In this case, TSOFT-START >TSTART-UP and thestart-up of the SMPS is secured.

15.5 Capacitor at VCC C6

The VCC capacitor C6 (CVCC in Fig.22)needs to ensure the power supply of theIC until the power can be provided by theauxiliary bias winding. Regardless thecurrent transfer from the start-up resistorR1 and the auxiliary winding during start-up time TSTART-UP, the capacitance valueC6 can be estimated as below:

CCHY

UPSTART3VCC6 V

TIC −= (41)

IVCC3 is the IC supply current with activegate-drive. Its maximum value is 8mA asspecified on the datasheet. VCCHY = 5V isthe turn-on/off hysteresis of the IC supplyvoltage VCC. Based on the estimated valueof TSTART-UP in (39), C6 should then be:

F30V5

ms8.18mA8C6 µµµµ≈×= (42)



C6 = 47µF is selected to sustain the Vcc.

15.6 Start-up Resistor R2 and R3

The start-up resistor RSTART-UP consists ofR2 and R3, which is connected in series asshown in Fig.22. By using (1) on page 2,the longest start-up delay time, whichhappens at the lowest lineinput voltageVACMIN = 85V can be estimated:

1VCCUPSTART

ACMIN

CCON6DELAYSTART

IR

2VVCt

−=

−

− (43)

s7.8A55

k47022V85

V5.13F47t DELAYSTART ≈−

×

×=−

µµµµΩΩΩΩ

µµµµ

In worst case, the IC is turned on only in8.7s after the SMPS is plugged to themain line. The maximum loss occurs inRSTART-UP is roughly:

( )UPSTART

2ACMAX

LOSSST R2VP

−− ≈ (44)

( ) W15.0k47022V265P

2

LOSSST ≈×

=− ΩΩΩΩ

15.6 Control Loop Design

15.6.1 Power Stage Transfer Function

Fig. 24 shows the essential elements ofthe control loop.

Following equations are used to define theDC or low frequency gain of the feedbackloop of the power stage (from the controlvoltage νFB at the feedback-input pin2 tothe output voltage node νO):

ηηηη××××= fLI21P 1

21O (45)

O

2O

O RP νννν= (46)

νννννννν ARVI14

CSTH

FB

1×

= (47)

Substitute PO and I1 in (45) with (46) and(47) and rearrange the equation in term ofνO/νFB, we obtain

2fRL

ARVG O1

14

CSTH

FB

OPS

ηηηηνννννννν

νννν×

×== (48)

Aν is the PWM-OP gain, which is equal to3.65 as specified in the datasheet ofICE2B265. Equation (48) shows that theDC or low frequency gain GPS of the powerstage is proportional to the square root ofthe output load RO and independent of theinput voltage variation due to the currentmode control. For ROMIN = 10.8Ω (at POMAX= 30W), the minimum gain is

6.5MIN,PSG2

310678.103208.065.345.0

95.0MIN,PSG

=

−×××××

×=

GPS,MIN = 14.9 dB. (49)

In case of POMIN = 0.5W, the output loadwill be ROMAX = 648Ω, the maximum powerstage gain will then be

43MAX,PSG2

310676483208.065.345.0

95.0MAX,PSG

=

−××××××

=

GPS,MAX = 32.7 dB (50)

The small signal transfer function of thepower stage with its pole and ESR-zero isshown below:

( )

+

+×=O

OOESR

PSPSC

2Rs1

CsR1GsG (51)

EA + Opto

Co

Resr

L1

C14

R14esrRo

R9

Vref

C10

R8

C9ICE2B265

FB

VCC

GND

1

2 3

4

8

ISENSE

SOFTST

7

DRAIN

NC

6

5

R14

V1 Vo

VFB

I1

Fig.24 The closed Feedback Loop



Co consists of C12 and C13 ( see Fig.22)with the total value of 2000µF and RESR isthe ESR values (see page 12) of bothcapacitor in parallel, Thus RESR = 0.017Ω.The poles and zero at minimum and atmaximun power are listed in Table 2below:

Output Power PolesFp = 1/ππππROCO

ZerosFZ = 1/2ππππRESRCo

POMAX = 30WRO = 10.8ΩΩΩΩ FPH = 14.7Hz FZ = 4.68kHz

POMIN = 0.5WRO = 648ΩΩΩΩ FPL = 0.24Hz FZ = 4.68kHz

Table 2. Poles and zero

The transfer function of the output filter L1-C14 can be expressed as follows:

−+

+=

ESR14142

ESR14

1

ESR1414LC

RC1

RLs1

RsC11

G

ωωωω

(52)

C14 and L1 have to be selected so that thepole of the filter FPLC is located far a wayfrom the crossover frequency FCO to avoidits influence in the control loop. Thecontrol loop bandwidth can only be kepthigh with high FPLC, which is desirable. TheL-C filter has a –2 gain slope with rapidchanges of phase shift, which couldinduce instability in the control loop. Toprevent it, the pole has to be compensatedby the zero as mentioned on page 12.Based on this consideration, Epcos Al-capacitor B41858-series of C14 =220µF/35V with R14ESR = 0.084Ω isselected. The zero frequency is then at:

kHz6.8CR2

1F14ESR14

14Z ==ππππ

(53)

Set the pole equal to zero and solve forthe inductance L1:

kHz6.8CL2

1

141=

ππππ (54)

L1 = 1.55µµµµH

With this combination of L1 and C14, theinfluence of the filter on the contol loopcan thus be neglected; the small signaltransfer function of the power stage is thendominated only by (51).

The open loop gain and phase responsesof the transfer function for the minimumand maximum output power are shown inFig.26 and in Fig.27.

To close the loop, the feedback loopcircuitry as shown in Fig.25 is added. Itconsists of a compensation network(TL431, R6 – R11, C9 and C10) and theoptocoupler IC2.

Fig.25 Feedback Loop Circuitry

The transfer function of the feedbackloop is

)8R9sC1(9R10sC8R)10C9C(s1

6RFBRCG

)s(O)s(FB)s(FBG

+++

⋅==νννν

νννν (55)

, where GC is the current transfer ratio ofthe optocoupler. For SFH617-3, GC =100%. The internal pull-up resistor at FB(pin2) is specified as RFB = 3.7kΩ.

R6=1kΩ is chosen to limit the maximumcurrent that flows into TL431. In order toachieve larger bandwidth and at the sametime to get the overall gain response with–1 slope, the crossover frequency FC =3kHz is selected. The gain of the powerstage at FC and at full load can then bederived from (51)

2

PH

C

2

Z

C

PSMINPSH

FF1

FF1

G)s(G

+

+

×= (56)

R9

C10

R8

C9

R11IC2TL431

IC2SFH617-3

R6

vo

RFB

2Vfb

6.5V



03.0

Hz7.14kHz31

kHz68.4kHz31

2.5)s(G 2

2

PSH =

+

+×=

dB4.30)F(G CPSH −=

The feedback loop gain with TL431 has tobe 30.4dB at FC and must have zero slopresponse. For further calculation, R9 has tobe defined first. R11 determines the biascurrent of the resistor divider R9 – R11. IfR11 = 3.9kΩ is selected, R9 can becalculated by

−= 1

VVRRREF

O119 (57)

ΩΩΩΩΩΩΩΩ k2415.2

18k9.3R9 =

−×= .

VREF is the reference voltage of TL431. Tocalculate the feedback loop gain at FC,(55) can be simplified as below:

9

8

6

FBCCFB R

RRRG)F(G = (58)

Since [GFB(FC)] = 30.4dB,

ΩΩΩΩk200RG

R10RRFBC

6204.30

98 ≈××= (59)

C9 is obtained by placing the pole at FPFB =2 x FC.

pF133FR2

1CPFB8

9 ==ππππ

(60)

In order to have sufficient phase margin,especially at light load, the zero is placedat FZFB = 20Hz. The value of C10 is then

nH39CFR2

1C 9ZFB8

10 =−=ππππ

(61)

Based on above calculation, the values ofthe feedback network components areselected as follows:

R8 = 220kΩΩΩΩ

R9 = 24kΩΩΩΩ

C9 = 120pF

C10 = 47nF

FZFB = 15.4Hz, FPFB = 6kHz

Fig.26 and Fig.28 also illustrate theresponses of the feedback loop circuitryand the total open loop, whereas Fig.27and Fig.29 show its respective phaseresponses.

16. Summary

This application note introduced briefly thefeatures and functions of the CoolSETTM,the new integrated product that includesPWM control IC and the CoolMOSTM, thenew generation Power MOSFET. A lowcost 30W SMPS demo-board circuit isdeveloped and its operation is analyzed isdetail. The detail explanation of the boardand the experiment results are describedin the application note “30W Off-lineSMPS Demoboard using CoolSETTM

ICE2B265”.



Gpsh f( )

Gfb f( )

G f( )

f1 10 100 1 10 3 1 10 4 1 10 560

40

20

0

20

40

60

Fig.26 Gain response atPOMAX

Power stage

Feedback loop

Overall open loop

qpsh f( )

qfb f( )

qtotal f( )

f1 10 100 1 10 3 1 10 4 1 10 590

45

0

45

90

Fig.27 Phaseresponse at POMAX

Power stage

Overall open loop

Feedback loop

Gpsl f( )

Gfb f( )

G f( )

f1 10 100 1 10 3 1 10 4 1 10 560

40

20

0

20

40

60

Fig.28 Gain response atPOMIN

Power stage

Overall open loop

Feedback loop

qpsl f( )

qfb f( )

qtotal f( )

f1 10 100 1 10 3 1 10 4 1 10 590

45

0

45

90

Fig.29 Phase response at POMIN Power stage

Overall open loop

Feedback loop



References

1. Harald Zoellinger and Rainer Kling, “CoolSETTM ICE2AXXX for Off-line Switch ModePower Supply”, Infineon Technologies Application Note, AN-SMPS-ICE2AXXX-1,version 1.0, January 2001.

2. Infineon Technologies, “CoolSETTM-II Off-Line SMPS Current Mode Controller with650V/800V CoolMOSTM on Board, Infineon Technologies Datasheet, version 2.2,February 2001.

Revision HistoryApplication Note AN-SMPS-ICE2B265-1Actual Release: V1.0 Date: 25.09.2001 Previous Release: V1.0Page ofactualRel.

Page ofprev.Rel.

Subjects changed since last release

22 ---------- First Issue



For questions on technology, delivery and prices please contact the Infineon TechnologiesOffices in Germany or the Infineon Technologies Companies and Representatives worldwide:see the address list on the last page or our webpage at

http://www.infineon.com

CoolMOS and CoolSET are trademarks of Infineon Technologies AG.

Edition 2001-03-01Published by Infineon Technologies AG,St.-Martin-Strasse 53,D-81541 München

© Infineon Technologies AG 2000.All Rights Reserved.

Attention please!The information herein is given to describe certain components and shall not be considered as warranted characteristics.Terms of delivery and rights to technical change reserved.We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits,descriptions and charts stated herein.Infineon Technologies is an approved CECC manufacturer.

InformationFor further information on technology, delivery terms and conditions and prices please contact your nearest InfineonTechnologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list).

WarningsDue to technical requirements components may contain dangerous substances. For information on the types in questionplease contact your nearest Infineon Technologies Office.Infineon Technologies Components may only be used in life-support devices or systems with the express written approvalof Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-supportdevice or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems areintended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail,it is reasonable to assume that the health of the user or other persons may be endangered.

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design of power correction circuit using tda4862 - infineon

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