esd infineon

RF and Protect ion Devices

AN 210

Effective ESD Protection Design at System Level

Using VF-TLP Characterization Methodology

Application NoteRevision: 1.1 - May 11, 2010

Edition 2009.11.16 Published by Infineon Technologies AG 81726 Munich, Germany © 2010 Infineon Technologies AG All Rights Reserved.

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Application Note No. 210

CONTENTS

Contents

1 Introduction 51.1 Definition of Electrostatic Discharge and Electrical Overstress . . . . . . . . . . . . . . . . . . . . . . . 51.2 The IEC61000-4-2 ESD Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.3 The IEC 61000-4-5 Surge Immunity Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.3.1 Surge Test Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.4 Comparison of Component Level and System Level ESD . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Characterization of ESD Protection Devices and Circuits with a Transmission Line Pulse System 102.1 What is a Transmission-Line Pulse Measurement Equipment? . . . . . . . . . . . . . . . . . . . . . . . 102.2 What can be Measured with a TLP Measurement Equipment? . . . . . . . . . . . . . . . . . . . . . . 112.3 TLP Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.1 Wafer Level TLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.3.2 PCB and Package Level TLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.3.3 Very Fast TLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.3.4 SOA and Charge Recovery Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142.3.5 System Level ESD Test (HMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.4 Typical TLP Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.5 Typical TLP Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.5.1 DC Sweep and Spot Leakage Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.5.2 TLP Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.5.3 Definition of the Dynamic Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.5.4 Transient Overshoot and Clamping Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.6 How TLP fits to IEC61000-4-2 ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.7 Why DC Measurement Is Not A Good Approach For ESD Characterization . . . . . . . . . . . . . . . 17

3 Comparison of ESD Protection Technologies: TVS versus MLV 183.1 DC Sweep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183.2 Dynamic On-Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193.3 Transient Overshoot and Clamping Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203.4 Spot Leakage Drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.5 Breakdown Voltage Drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.6 Degradation due to Multi-Pulse Stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.6.1 Spot Leakage Drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.6.2 Breakdown Voltage Drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

References 24

Application Note of 25 Rev. 1.1 - May 11, 2010


CONTENTS

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1 Introduction

In today’s highly competitive markets, efficient ESD protection has became an integral part of IC/ASIC design forsystem reliability. Field failures due to ESD will be perceived as poor quality by disappointed customers and willincrease the number of warranty returns. Overlooking the ESD problem can seriously impact company’s image andits profitability.

Reliable circuit protection following IEC61000-4-2 industry’s standard is usually accomplished by the implemen-tation of ESD protection devices at critical pins. However, some traditional approaches still rely on trial-and errorpractices to design for ESD protection. This can require several re-design loops until the ESD problem is finallysolved, for instance during compliance testing, practice that increases costs and delay the time-to market of newelectronic products.

The introduction of Very-Fast Transmission Line Pulse (vf-TLP) as support method is of utmost importance in theselection of appropriate ESD protection devices and makes the trial and error practices not longer justified. The VeryFast Transmission Line Pulse employs high current testing to determine the behaviour of devices and circuits in thecurrent and time domain of ESD events. This strategy implemented at an early circuit design stage delivers a faster,precise and least costly approach to improve ESD robustness at system level while responding to today’s marketdynamics.

The purpose of this application note is to provide the guidelines for optimized selection of protection deviceswith the support of vf-TLP. Chapter 1 provides an introduction to electrostatic discharge standards typically used inthe industry. Chapter 2 describes the characteristics of TLP equipment as well as measurement set up and testingcapabilities. Section 2.5.2 explains the typical I/V characteristic curves of unidirectional and bidirectional protectiondevices. Chapter 3 displays a benchmark comparison of ESD protection devices based on different technologies,namely Multilayer Varistor (ceramic technology) and TVS diode (silicon based technology).

1.1 Definition of Electrostatic Discharge and Electrical Overstress

Electrostatic Discharge (ESD) is known as transfer of electrostatic charge between bodies or surfaces at differentelectrostatic potential. ESD can happen due to sudden discharge of a charged body, tribo-electric and inducedcharging. ESD is a high current event in the typical range of 0.1 to 30 Apeak in a very short period of time from1 ns to 200 ns.

Electrical Overstress (EOS) is considered as the exposure of a device or an integrated circuit (IC) to a currentor voltage beyond its absolute maximum ratings. EOS can occur due to voltage overshoots resulting in highdestructive currents.

ESD is considered as a subset of EOS. But EOS may caused also by a wrong application of the IC beyond its absolutemaximum voltage or current ratings. In this case the damage of the IC may not happened due to an ESD event.

The International Electrotechnical Commission (IEC) has developed transient immunity standards which havebecome minimum requirements for original equipment manufacturers. The basic standards for immunity testing areknown as the IEC 61000-4-X standards. Three of the IEC standards deal with transient immunity:

• IEC 61000-4-2 : Electrostatic Discharge (ESD)

• IEC 61000-4-4 : Electrical Fast Transient/Burst (EFT)

• IEC 61000-4-5 : Surge Immunity

IEC 61000-4-2 is related to ESD immunity [1]. IEC 61000-4-4 and IEC 61000-4-5 are related to transient immunity[2, 3].

1.2 The IEC61000-4-2 ESD Standard

The IEC 61000-4-2 standard [1] addresses ESD transients in electronic systems. It defines immunity requirementsfor ESD which can be coupled into the equipment, systems or system boards directly or through radiation (air dis-charge). Direct coupling includes any user accessible entry points such as connectors, I/O ports, switches, computerkeyboards, panel displays, touch screens and equipment housings.

Radiated coupling results from the spark discharge between two bodies which are external to the system. Be-cause the human body is one of the most common ESD generators, the IEC standard defines a test set up whichsimulates an ESD event from a human body.



1.2 The IEC61000-4-2 ESD Standard

−50 0 50 100 150 2000

1

2

3

4

5

6

7

8

9

Time (ns)E

SD

−Cur

rent

(A)

First Peak Current

0.7

ns -

1 ns

Ris

etim

e

10 %

90 %

I at 30 ns

I at 60 ns

Figure 1: 2 kV ESD current pulse waveform according IEC61000-4-2 (R=330Ω, C=150 pF) [1].

The Human Body Model is considered as a valid rep-resentation of worst case ESD stress. Discharge intoequipment may be through direct contact (contact dis-charge method) or just prior to contact (air dischargemethod). Contact discharge is the usually preferred testmethod, but air discharge is used where contact dis-charge cannot be applied.

The ESD threat is divided into four threat levels de-pending on material and ambient humidity, as shown inTab. 1. Threat level 1 is considered the least severewhile threat level 4 is the most severe. Levels 1 & 2 arereserved for equipment which is installed in a controlledenvironment and in the presence of antistatic materials.Level 3 is used for equipment which is sparsely but notcontinuously handled. Level 4 is required for any equip-ment which is continuously handled.Fig. 1 shows a 2 kV ESD current pulse waveform ac-cording IEC 61000-4-2 with a R=330Ω and C=150 pFdischarge circuitry. The ESD current waveform at a cer-tain indicated discharge voltage is specified with 4 pa-rameters:

1. rise time 0.7 - 1 ns

2. first peak current of discharge (±10 %)

3. Current at 30 ns (±30 %)

4. Current at 60 ns (±30 %)

Table 1: IEC 61000-4-2 severity levels and test voltages.

Relative Antistatic Synthetic Maximum Test Voltage Test VoltageClass Humidity Material Material Charge (Contact- (Air-

(as low as) Voltage Discharge) Discharge)1 35 % x 2 kV 2 kV 2 kV2 10 % x 4 kV 4 kV 4 kV3 50 % x 8 kV 6 kV 8 kV4 10 % x 15 kV 8 kV 15 kV

Table 2: IEC 61000-4-2 ESD current waveform parameters.

Indicated First Peak Current Risetime Current CurrentLevel Voltage of Discharge with Discharge at 30 ns at 60 ns

(±10 %) Switch (±30 %) (±30 %)1 2 kV 7.5 A 0.7 ns to 1 ns 4 A 2 A2 4 kV 15 A 0.7 ns to 1 ns 8 A 4 A3 6 kV 22.5 A 0.7 ns to 1 ns 12 A 6 A4 8 kV 30 A 0.7 ns to 1 ns 16 A 8 A



1.3 The IEC 61000-4-5 Surge Immunity Standard


IEC 61000-4-5 addresses the most severe transient conditions on both power and data lines. These are transientcaused by lightning strikes and switching. Switching transients may be the result of power system switching, loadchanges in power distribution systems, or short circuit fault conditions. Lightning transients may result from a directstrike or induced voltages and currents due to an indirect strike.

The IEC 61000-4-5 standard defines a transient entry point and a set of installation conditions. The transient isdefined in terms of a generator producing a given waveform and having a specified open circuit voltage and sourceimpedance. Two surge waveforms are specified: the 1.2 x 50 µs open-circuit voltage waveform and the 8 x 20 µsshort-circuit current waveform (Fig. 2 and Fig. 3).

1.0

0.9

0.5

0.3

0.1

T1

T t

V

T2

30% max.

T1 = 1.67 x T = 1.2 µs +/-30 %T2 = 50 µs +/-20 %

Figure 2: IEC 61000-4-5 1.2 µs / 50 µs voltage impulse.

1.0

0.9

0.5

0.1

T1

T t

I

IPP

T2

30% max.

T1 = 1.25 x T = 8 µs +/-20 %T2 = 20 µs +/-20 %

Figure 3: IEC 61000-4-5 8 µs / 20 µs current impulse.

Transient stress levels for each entry point into the system are defined by installation class. The six classes aredefined as:

Class 0: well protected environment

Class 1: partially protected environment

Class 2: well separated cables

Class 3: cables run in parallel

Class 4: multi - wire cables for both electronic and electrical circuits

Class 5: connection to telecommunications cables and overhead power lines (low density populated areas)

A class 0 environment is considered the lowest threat level a has no transient stress requirements. The class 5environment is the most severe and requires the highest transient stress level testing.

Tab. 3 summarizes threat levels as a function of installation class. Values of voltage stress using the 1.2 x 50 µswaveform are given. Corresponding current values are calculated by dividing the open-circuit voltages by the sourceimpedances. The short-circuit current values are more useful in choosing a suppression element. The short cir-cuit current stress levels are defined with the 8 x 20 µs waveform for power supply applications with a 2 Ω sourceimpedance. For data lines requiring a 42 Ω source impedance, the short-circuit current waveform is defined as8 x 20 µs. For telecommunications applications, the open-circuit voltage is defined as 10 x 700 µs and the short-circuit current is a 5 x 300 µs waveform. The source impedance is given as 40 Ω. The type of suppression elementneeded for IEC 61000-4-5 class surges depends upon the threat level and installation class. For power supply ap-plications high power devices are required. A discrete device or an assembly may be required depending on theapplication. TVS diodes are the best choice for data line applications and secondary board level protection becauseof their superior clamping voltage characteristics and fast response time.




Table 3: IEC 61000-4-5 Severity Levels.

Power Supply Unsym. Lines Sym. Lines Data Bus(Long Distance Bus) (Short Distance)

Class Coupling Mode Coupling Mode Coupling Mode Coupling ModeLine-Line Line-GND Line-Line Line-GND Line-GND Line-GNDZs= 2 Ω Zs=12 Ω Zs=42 Ω Zs=42 Ω Zs=42 Ω 42 Ω

voltage No Requirement0 current

voltage (n/a) 0.5 kV (n/a) 0.5 kV 1 kV (n/a)1 current 42 A 12 A 24 A

voltage 0.5 kV 1 kV 0.5 kV 1 kV 1 kV 0.5 kV2 current 250 A 83 A 12 A 24 A 24 A 12 A

voltage 1 kV 2 kV 1 kV 2 kV 2 kV (n/a)3 current 500 A 167 A 24 A 48 A 48 A

voltage 2 kV 4 kV 2 kV 4 kV (n/a) (n/a)4 current 1000 A 333 A 48 A 95 A

voltage Note1 Note1 2 kV 4 kV 4 kV5 current 48 A 95 A 95 A

Wave- voltage 1.2 x 50 µs 1.2 x 50 µs 1.2 x 50 µs 1.2 x 50 µs 1.2 x 50 µs 1.2 x 50 µsforms current 8 x 20 µs 8 x 20 µs 8 x 20 µs 8 x 20 µs 8 x 20 µs 8 x 20 µs

1.3.1 Surge Test Measurement Setup

Figure 4: 8/20 µs surge test measurement setup.

Fig. 4 shows the measurement setup for the 8/20 µs surge test of TVS diodes. The amplitude of the pulse generatoris adjusted for typical peak current (Fig. 3) of IPP=1 A and IPP=3 A, respectively for TVS products. The peak clampingvoltage at e.g. IPP1=1 A and IPP2=3 A is measured and presented in the data sheet. The dynamic resistance can becalculated as follows:

Rdyn =VCL2 − VCL1

IPP2 − IPP1(1)

1Depends on class of local power supply system.



1.4 Comparison of Component Level and System Level ESD

1.4 Comparison of Component Level and System Level ESD

Component level ESD stress occurs in wafer- or component-fabrication areas caused by static charge generation andduring product lifetime due to human handling electrostatic discharge [4], [5]. Normally, IC’s are designed to meet 1 kVto 2 kV HBM ESD robustness according the JEDEC Standard JESD22-A114E [6]. Recent investigations have shownthat a level of >500 V HBM (JESD22-A114E) ESD robustness is sufficient for state-of-the-art fabrication technologies[7]. The recommendations therein are intended for component level safe ESD requirements and will have little or noeffect on system level ESD results. Systems and system boards should continue to be designed to meet appropriateESD threats regardless of the components in the systems that are meeting the new recommendations [7], and that allproper system reliability must be assessed through the IEC test method [1]. Tab. 4 shows a comparison of componentand system level ESD test procedure for product qualification.

Table 4: Comparison of Component and System Level ESD Test

Parameter Component Level ESD Test System Level ESD TestStressed pin group All pin combinations Few special pinsSupply Unpowered Powered & unpoweredTest methodology Standardized Application specificTest set-up Commercial tester & sockets Application specificTypical qualification goal 1 . . . 2 kV JEDEC HBM

(JESD22-A114E, [6])8 kV Contact (IEC 61000-4-2, [1])15 kV Air (IEC 61000-4-2, [1])

Corresponding peak current 0.65 . . . 1.3 A >20 AJunction/ambient temperature 27 C Application specificFailure signature Destructive Functional or destructive

Tab. 5 shows the typical JESD22-A114E and IEC 61000-4-2 ESD current waveform parameters.

Table 5: Comparison ESD current waveform parameters.

Standard R/C Network Rise-Time First PeakCurrent

Broad PeakCurrent

Decay Time

JESD22-A114E R = 1.5 kΩ, C = 100 pF 2-10 ns 0.67 A/kV - 130-170 nsIEC 61000-4-2 R = 330Ω, C = 150 pF 0.7-1 ns 3.75 A/kV 2 A/kV -

Fig. 5 compares the ESD current waveform for 1 kV component level ESD (JESD22-A114E) and 1 kV system levelESD (IEC 61000-4-2).

−50 0 50 100 150 2000

1

2

3

4

5

JESD22−A114E

IEC 61000−4−2

Time (ns)

ES

D−

Cur

rent

(A

)

Figure 5: Comparison of a 1 kV component-level ESD pulse according HBM JESD22-A114E (R=1.5 kΩ, C=100 pF)[6] and a 1 kV system-level ESD pulse according IEC 61000-4-2 (R=330Ω, C=150 pF) [1].



2 Characterization of ESD Protection Devices and Circuits with a Trans-mission Line Pulse System

A Transmission-Line Pulse (TLP) system is a valuable measurement equipment for circuit and device characterizationin pulsed operation mode in the high power time domain. TLP has been introduced for the characterization of ESD-devices by Maloney [8] in the middle eighties.

2.1 What is a Transmission-Line Pulse Measurement Equipment?

• A pulse generator which delivers rectangular pulses on a 50 Ω output. Typical pulse amplitude in the range of0. . .±1.5 kV into a 50 Ω load.

• The rectangular pulse is generated by a high-voltage charged 50 Ω transmission-line. Therefore called:Transmission-Line Pulse System. The rise time of the pulse is in the range from 100 ps to 10 ns.

• If the pulse width is ≤10 ns then the system is called Very-Fast Transmission-Line Pulse (VF-TLP) system. Ifthe pulse width is >10 ns it is called Standard TLP.

• TLP is basically well known for more than 30 years.

• In 1985 T. Maloney et al. introduced TLP for ESD characterization ([8] EOS/ESD Symposium 1985, p. 49).

Fig. 6 shows a simplified schematic diagram of a TLP generator.

50 ΩPulse Output

50 Ω

VPULSE

Figure 6: TLP generator simplified block diagram.

A TLP generator is able to generate single shot rectangular pulse waveforms in a 50 Ω transmission line. The typicalamplitude range of the output pulses is 0 . . .±1.5 kV into open load and 0 . . .±0.75 kV with 50 Ω load. The typicalwidth of the pulse is 1 ns to 1500 ns. The typical rise time of pulse can be programmed in the range of 100 ps to≥10 ns.

Because of the high voltage and current amplitudes state-of-the-art semiconductor or tube pulse generators arenot sufficient. Therefore a well-known concept based on transmission lines is used to generate high energy pulses.Fig. 7 shows a more detailed block diagram to explain the principle how the high energy pulses are generated.

50 Ω

Switch

50 ΩPulse Output

TL1

LS0

1

0

50 Ω

High VoltageDC Power SupplyVDC

TL2

Figure 7: TLP generator basic theory of operation.

Let us assume the following initial condition: the switch S0 is at the position 0 for the time t < 0. Therefore the 50 Ωtransmission line TL1 (so called ”charge line”), usually a 50 Ω coax RF cable, is charged with the high voltage VDCfrom the DC high voltage power supply. Note that TL1 is open on its back end. If the switch is switched to the position



2.2 What can be Measured with a TLP Measurement Equipment?

1 at the time t = 0 the voltage at the switch drops immediately down to VDC/2 because the electromagnetic wave faces50 Ω sources resistance of TL1 and 50 Ω load resistance of the output transmission line TL2 at that time, which formsbasically a voltage divider by 2. Therefore at t = 0 one step wavefront with amplitude VDC/2 is starting transmissionin the direction to the output and another step wavefront with amplitude VDC/2 is starting transmission in backwardsdirection to the open end of TL1. If this backend wavefront hits the open end of TL1 the amplitude develops two times−VDC/2 due to total reflection at the open end which leads to cancelation (destructive interference) of the TL1 chargevoltage at t = L/v, where L is the length of TL1 and v is the velocity of wave propagation in TL1. The cancelationwavefront starts again transmission from the open end of TL1 to the switch S0 and to the output respectively. Thisresults in a pulse width T of the rectangular waveform of

T =2 ·Lv

(2)

where again L is the length of TL1 and v is the velocity of wave propagation in TL1. Different pulse widthcan be obtained with different length of TL1. Different amplitude can be obtained with programmable VDC and/orprogrammable attenuators connected in series to the output transmission line TL2. The rise time of the pulse can beinfluenced by connection of rise-time filters in series to the output of the transmission line TL2.

2.2 What can be Measured with a TLP Measurement Equipment?

A TLP system offers advanced features intended for the characterization of circuits and semiconductor devices in thehigh power time domain. It includes high current I-V characteristics in pulsed operation mode, turn-on/off transientcharacteristics of the device, breakdown effects, charge recovery effects (e.g. reverse recovery), Safe-Operating-Area (SOA) and ESD measurements:

• High current I-V characteristics of devices and circuits in pulsed operation mode: the ”TLP-Characteristic”

• Turn-on/off transient characteristics of the device

• Breakdown effects

• Charge recovery effects

• Safe Operating Area (SOA) or Wunsch-Bell characteristic

• Gate oxide reliability

• Human-Metal-Model (HMM) ESD

2.3 TLP Measurement Setup

Fig. 8 shows the block diagram of the TLP measurement system. The high voltage pulse generator delivers rectangu-lar pulses with 50 Ω source impedance. The DUT is connected to the pulse generator using 50 Ω transmission lines.In a standard-TLP setup the the current is measured using a discrete current sensor with a bandwidth of several GHz.The voltage is measured using a high-frequency probe with a built-in voltage divider and a voltage transfer ratio of100:1. A single-shot sampling oscilloscope with minimum recommended 2.5 GHz bandwidth, 10-20 GS/s and 100 psrise-time is used to record the transient current and voltage waveform of the pulse. During a TLP measurement theamplitude of the rectangular pulse is increased subsequently from zero to a certain positive or negative level. Thecurrent and voltage waveform is recorded using a high speed sampling oscilloscope. A time window of about 20 %of the pulse width, in the second half of the pulse, is used to calculate the average value of the transient current andvoltage amplitude. The average values I and V are representing a data point in the IV-characteristic of the DUT. ThisIV-characteristic is known as TLP-characteristic with its TLP-voltage on x-axis and TLP-current on y-axis.

2.3.1 Wafer Level TLP

Fig. 9 shows the block diagram of a standard wafer-level TLP measurement setup. To eliminate the error from non-zero contact resistance, a four point Kelvin method is preferred to measures the differential voltage directly at thedevice pads. RF-probes of type e.g. Picoprobe R© model-10 (7 GHz) [9] or Cascade ACP-40 (40 GHz) [10] and otherscan used for high performance probing.




V(t)

I(t)t

t

TLP Voltage (V)

TLP

Cur

rent

(A)

I

V

I , V

DUTV(t)

I(t)50 Ω

High VoltagePulse Generator

I

V

Figure 8: Block diagram of a TLP measurement system.

LEAKAGETEST

DUT - Switch

Source MeterDUT Leakage Test

DIGITALSAMPLING

OSCILLOSCOPE

Switch Control

50 Ω Pulse Output

CH 3

TLP Generator

LeakageDUT

Pulse

TLP Pulse WidthExtender

ChargeLine OUT

Pulse WidthControl

ChargeLine IN

PC +

Mat

lab

Syst

em C

ontr

ol S

oftw

are

GPIB

GPIB

GPIB

50 Ω

DUT Pulse Force

DUT Pulse Sense

DUT

5 kΩ RF GS Probe

PAD PAD

50 Ω RF GS probe

5 kΩ50 Ω

50 Ω

Tektronix CT-1CURRENT SENSOR

50 Ω50 Ω

Current

A1CH 1

Pulse Sense

50 Ω

Figure 9: Wafer-level standard TLP setup.




2.3.2 PCB and Package Level TLP

For package and PCB-level TLP measurements a printed circuit board adapter is used to contact the DUT withshort interconnection wires. A pulse rise time of 10 ns is recommended in order to avoid ringing due to the parasiticinductance of the wires. Fig. 10 to Fig. 12 show three typical configurations.

50 Ω

DUT1.1 kΩ

5.1 kΩ

parasiticL

PCB Adapter

5.1 kΩ

DUTPulse

DUTGND

DUTPulseSense

DUTGNDSense

parasiticL

IDUT

IDUT

DirectPulseSense

PulseIN

PulseSense

GNDSense

50 Ω

50 Ω

50 Ω

Figure 10: Direct pulse sense configuration.

50 Ω

DUT1.1 kΩ

5.1 kΩ

parasiticL

PCB Adapter

5.1 kΩ

DUTPulse

DUTGND

DUTPulseSense

DUTGNDSense

parasiticL

parasiticL

IDUT

IDUT

DirectPulseSense

PulseIN

PulseSense

GNDSense

50 Ω

50 Ω

50 Ω

Figure 11: Pulse sense configuration.

50 Ω

DUT1.1 kΩ

5.1 kΩ

parasiticL

PCB Adapter

5.1 kΩ

DUTPulse

DUTGND

DUTPulseSense

DUTGNDSense

parasiticL

parasiticL

parasiticL

IDUT

IDUT

DirectPulseSense

PulseIN

PulseSense

GNDSense

50 Ω

50 Ω

50 Ω

Figure 12: Differential pulse sense with GND sense configuration.




2.3.3 Very Fast TLP

For VF-TLP measurements with pulse widths <10 ns, incident and reflected signals are recorded separately with awide-band pick-off tee in the pulse-force line (see Fig. 13). The transient device response is calculated by combiningthe incident and reflected pulse signals numerically (TDR-s method). The device voltage is preferably measureddirectly with a second probe with integrated voltage dividing resistor. This assures high bandwidth and minimizesthe voltage error due to parasitic contact resistance. It also eliminates the digital noise that is typical for voltagemeasurements of low-ohmic devices with the TDR-s method.

LEAKAGETEST

DIGITALSAMPLING

OSCILLOSCOPE

Switch Control

50 Ω Pulse Output

CH 3

LeakageDUT

Pulse

ChargeLine OUT

Pulse WidthControl

ChargeLine IN

PC +

Mat

lab

Syst

em C

ontr

ol S

oftw

are

GPIB

GPIB

GPIB

50 Ω

DUTPulse Sense

DUT

5 kΩ PicoprobeModel 10

PAD PAD

50 Ω PicoprobeModel 10

5 kΩ50 Ω

50 Ω

A1CH 1

Pulse Sense

50 Ω

Delay

PICKOFFTEE

A3Incident/ReflectedWave Signal

TLP Pulse WidthExtender

TLP Generator

Source MeterDUT Leakage Test

DUT - Switch

Figure 13: Wafer-level very-fast TLP setup (VF-TLP).

2.3.4 SOA and Charge Recovery Time

The Safe Operating Area (SOA) of active and passive devices can be easily measured using a TLP test system withvariable pulse widths in the full range from about 1 ns to 1 µs. In addition the test system offers a measurementsetup for charge recovery measurements like forward and reverse recovery time of diodes. The recovery times canbe measured extremely fast in the range from 200 ps to 1 µs. The DUT is mounted in a true 50 Ω test fixture.

2.3.5 System Level ESD Test (HMM)

State of the art TLP systems also offers a Human Metal Model (HMM) pulse waveform as an alternative test methodto IEC 61000-4-2 with significant improved reproducibility of the test results.



2.4 Typical TLP Parameter

2.4 Typical TLP Parameter

The following parameters are necessary to specify a TLP measurement:

TLP System Impedance: 50 Ω source impedance TLP systems are widely used. However, sometimes for specificsnapback measurements and evaluation of the holding voltage a higher source impedance is recommended.

Pulse Width: The standard TLP pulse width is 100 ns because the total pulse energy is similar to ESD pulsesaccording to the JESD22-A114E HBM. The variable pulse width of commercial TLP measurement systems isin the range from 1 ns up to 1000 ns.

Pulse Rise-Time: Standard TLP systems have a pulse rise-time of 10 ns. VF-TLP systems offer rise times down to100 ps to investigate turn-on characteristic of the DUT.

Spot Leakage and Curve Tracing: The test method for evaluation of the device failure must be defined. DC-presweep, spot leakage measurement and dc curve tracing are widely used.

2.5 Typical TLP Measurement Results

2.5.1 DC Sweep and Spot Leakage Measurement

The DUT ist characterized with a DC measuremenmt procedure before, during and after TLP measurement. DC I-Vcharacteristics or single spot measurements with forced currents or voltages can be used to monitor device dc driftsor damage during the TLP measurements.

2.5.2 TLP Characteristic

Fig. 14 illustrates typical TLP characteristics1 which are discussed in general ESD protection concepts [5].In Fig. 14(a) the protection device has a simple turn-on at a threshold point (Vt1, It1) with t1 being the triggering

time to form a low-impedance channel to discharge ESD transients. In the reverse direction the dynamic resistanceRdyn,rev can be observed. In the forward direction the device shows the forward dynamic resistance Rdyn,fwd. Fig. 14(b)shows a snapback device where it turned on at a triggering point (Vt1, It1, t1), then driven into a snapback region withlow holding (Vh, Ih) to create a low impedance discharge path. Again in the reverse direction the dynamic resistanceRdyn,rev can be observed. In the forward direction the device shows the forward on-resistance Rdyn,fwd. The secondbreakdown or irreversible destruction of the device can be observed at the point (Vt2, It2). Fig. 14(c) shows a uni-directional characteristic. For negative voltages the device shows a forward PN-junction. In Fig. 14(d) a bi-directionalcharacteristic is presented. The device has a symmetrical transfer characteristic.

2.5.3 Definition of the Dynamic Resistance

The dynamic resistance of a device is defined as the derivation dV/dI at a certain point on its I-V characteristic:

Rdyn(V, I) =dV

dI(3)

If the I-V characteristic is constant in a wide range, as shown in e.g. Fig. 14(a) in reverse mode between turn-on and2nd break down, then the dynamic resistance can be extracted with two points:

Rdyn,rev =Vt2 − Vt1

It2 − It1(4)

In general the dynamic resistance is dependent on:

• the location on the I-V characteristic of the device

• the pulse width

• the location and length of the averaging window to extract the mean of the voltage and current (Fig. 8)

For longer pulse width, like the 8 µs/20 µs surge immunity test, increased self heating of the device is expected. Thedynamic resistance can extracted as presented in Sect. 1.3.1.

1obtained from measurement setup shown in Fig. 8.



2.6 How TLP fits to IEC61000-4-2 ?

0

0

TLP Voltage (V)

TLP

Cur

rent

(A) ESD Protection Region

(Low-R Discharge)

Turn-On(Vt1, It1, t1)

R dyn,

fwd

dy

n,re

v

R

, I2nd Breakdown

(Vt2 t2),I

(a) Simple turn-on [5].

0

0

TLP Voltage (V)

TLP

Cur

rent

(A) ESD Protection Region

(Low-R Discharge)

Triggering(Vt1, It1, t1)

R dyn ,

rev

R dyn,

fwd

Holding(Vh, Ih)

2nd Breakdown(Vt2, It2)

(b) Snapback [5].

0

0

TLP Voltage (V)

TLP

Cur

rent

(A)

(c) Uni-directional I-V characteristic.

0

0

TLP Voltage (V)

TLP

Cur

rent

(A)

(d) Bi-directional I-V characteristic.

Figure 14: Typical TLP I-V characteristics used for ESD protection design.

2.5.4 Transient Overshoot and Clamping Voltage

The Mystery about ESD protection is gone. Advanced TLP tester show that the first nanosecond can determinewhether a chip will live or die. In essence sometimes chip manufacturers look at failure at voltages too late in theESD event. Investigation of transient turn on and overshoot in the picosecond range makes the difference betweenprotecting or not. In Sect. 3 two state of the art esd protection device technologies will be compared.

2.6 How TLP fits to IEC61000-4-2 ?

In general there is no correlation between standards and TLP measurement results allowed, because generation ofthe test signal is different and also the DUT sensitivity against waveform parameters (e.g. rise time) is most likelydifferent. TLP generates a rectangular voltage waveform with 50 Ω source resistance. IEC61000-4-2 generates adifferent waveform shown in Fig. 1 at different time variant source impedance. However, the big advantage of TLPis the well defined and exact controllability of the waveform parameters such as source impedance, pulse width, risetime, amplitude.In general the energy per pulse can be calculated as

Epulse =

∫ T

0

p(t) dt (5)

where p(t) is the instantaneous power of the DUT. If the ESD protection device has turned on and has a very lowresistance in order to shunt the ESD current the pulse energy of pulse waveforms according IEC 61000-4-2 (R=330Ω,C=150 pF) can be calculated as shown in Tab. 6.



2.7 Why DC Measurement Is Not A Good Approach For ESD Characterization

IEC 61000-4-2 (R=330Ω, C=150 pF) Level Pulse Energy1 kV 0.5 µJ2 kV 2.03 µJ4 kV 8.1 µJ8 kV 32.5 µJ

15 kV 114.5 µJ

Table 6: Pulse energy of ESD pulses according IEC 61000-4-2 (R=330Ω, C=150 pF).

Based on the broad peak currents shown in Tab. 5 a TLP impulse with 2 A amplitude, 63.4 ns pulse width, 300 ps risetime gives a pulse energy of 0.508 µJ which correlates very well to a 1 kV pulse according IEC 61000-4-2 (R=330Ω,C=150 pF). In general TVS diodes are not sensitive to the first peak of the IEC pulse. In most cases the pulse energyis the performance limiting parameter.

Recommendation

Using a TLP equipment to measure the dynamic resistance, turn-on characteristic and maximum fail current of TVSdiode the following TLP parameters are recommended (Tab. 7):

Parameter Value CommentTLP source impedance 50 ΩMaximum TLP current up to ±60 A 2 A/kV IEC broad peak valuePulse width 63.4 ns minimum 30 nsPulse rise time 300 ps correlates well with commercial IEC ESD tester

which are slightly faster than specified in IEC stan-dard

Table 7: Recommended TLP parameter for IEC 61000-4-2 (R=330Ω, C=150 pF) performance evaluation.

2.7 Why DC Measurement Is Not A Good Approach For ESD Characterization

The ESD event operates the protection device in the high current domain for a limited period of time in the 100 nsrange. DC measurements are used to evaluate the leakage performance in the nA to µA range. The ESD protectiondevice is not turned on in this normal operating condition. DC operation in the ESD protection region (Fig. 14) wouldresult in self-heating and destruction of the device due to electrical overstress (EOS).



3 Comparison of ESD Protection Technologies: TVS versus MLV

Fig. 15 shows a photograph of 3 devices for performance comparison. All devices have been measured with 400 µmpitch wafer-level RF-probes contacted directly at its pads. This is a significant advantage because no 50 Ω test fixtureand no deembedding is necessary. The transient waveforms are measured directly on the pads of the devices whichreflects exactly the application on the PCB.

(a) Infineon TVS ESD08V0R1B-02LS(0201).

(b) MLV-1 (0201). (c) MLV-2 (0201).

Figure 15: Comparison of ESD protection devices: Transient Voltage Suppressor diodes (TVS, silicon technology)and Multi-Layer Varistors (MLV, ceramic technology).

3.1 DC Sweep

In comparison to best-in-class 0201 MLV in ceramic technology the 0201 TVS diode in silicon technology has muchlower DC leakage current. This results in significant improvement in battery life time of mobile handsets using siliconTVS diodes. In Fig. 16 the leakage current of the TVS diode ESD8V0R1B-02LS is even lower than the measurementlimit of the equipment. Breakdown is well defined and sharp.

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

-20 -15 -10 -5 0 5 10 15 20

|DC

Lea

kage

Cur

rent

| (A

)

Voltage (V)

TVS ESD8V0R1B-02LSMLV-1MLV-2

Figure 16: DC characteristic comparison.



3.2 Dynamic On-Resistance

3.2 Dynamic On-Resistance

Fig. 17 presents the TLP characteristics of ceramic MLVs compared to silicon TVS. At 25 A the clamping voltage ofthe MLVs are 2.5 times and 5.5 times higher compared to the silicon TVS. The TVS has 0.77 Ω compared to 2 Ω and5 Ω of the MLVs, respectively. Fig. 18 gives a detailed view at lower current levels. The TVS shows lowest dynamicresistance and steepest turn-on characteristic.

0

5

10

15

20

25

30

0 50 100 150 200

TLP

Cur

rent

(A

)

TLP Voltage (V)


0.77Ω 2Ω 5Ω

Figure 17: I/V characteristic comparison. TLP-parameter: 50 Ω, 100 ns pulse width, 290 ps rise time.

0

1

2

3

4

5

0 10 20 30 40 50 60 70 80 90 100 110 120

TLP

Cur

rent

(A

)

TLP Voltage (V)

TVS ESD8V0R1B-02LSMLV -1MLV-2

Figure 18: I/V characteristic comparison: detail view.



3.3 Transient Overshoot and Clamping Voltage

3.3 Transient Overshoot and Clamping Voltage

In Fig. 19 the transient overshoot of MLV-2 is 250 V at 16 A TLP current, which relates to approximately 8 kV accordingIEC-61000-4-2. The overshoot of 250 V is too high for sensitive sub-100 nm CMOS technologies. The TVS dioderesults in only 60 V at same ESD current level. In general the TVS diode shows the lowest clamping voltage. Fig. 20shows the turn-on in detail at 25 ps sampling interval. The TVS has very low overshoot.

0

50

100

150

200

250

-10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140

Cla

mpi

ng V

olta

ge (

V)

Time (ns)


Figure 19: Clamping voltage comparison at 16 A TLP current. TLP-parameter: 50 Ω, 100 ns pulse width, 290 ps risetime. Scope: Tektronix TDS6124C, 12.5 GHz bandwidth, 40 GS/s sampling rate.

0

50

100

150

200

250

-0.5 0 0.5 1 1.5

Cla

mpi

ng V

olta

ge (

V)

Time (ns)


Figure 20: Turn-on comparison at 16 A TLP current. TLP-parameter: 50 Ω, 100 ns pulse width, 290 ps rise time.Scope: Tektronix TDS6124C, 12.5 GHz bandwidth, 40 GS/s sampling rate.



3.4 Spot Leakage Drift

3.4 Spot Leakage Drift

Fig. 21 shows the DC spot leakage drift at 5 V reverse working voltage during a single TLP sweep up to >25 A.MLV-1 and MLV-2 show significant drift in leakage current. The TVS diode has extremely low leakage and zero drift.

0

5

10

15

20

25

30

35

10-11 10-10 10-9 10-8 10-7

TLP

Cur

rent

(A

)

Spot Leakage Current (A)


Figure 21: DC spot leakage drift at 5 V reverse working voltage. TLP-parameter: 50 Ω, 100 ns pulse width, 290 psrise time.

3.5 Breakdown Voltage Drift

Fig. 22 shows the breakdown voltage drift at 1 mA force current during a single TLP sweep up to >25 A. MLV-2 hasslight drift. ML-1 has significant drift. TVS shows zero drift which means no pulse-to-pulse degradation.

0

5

10

15

20

25

30

35

10 15 20 25 30

TLP

Cur

rent

(A

)

Breakdown Voltage (V)


Figure 22: Breakdown voltage drift at 1 mA force current. TLP-parameter: 50 Ω, 100 ns pulse width, 290 ps rise time.



3.6 Degradation due to Multi-Pulse Stress


In this test the device is stressed with multiple pulses at a certain current level: 100 pulses at about 5 A, 100 pulsesat about 10 A, and so on, up to about 25 A to 30 A . The spot leakage drift is recorded for each stress pulse. In thefirst experiment the DC leakage current at 5 V reverse working voltage is recorded and in the second experiment thebreakdown voltage drift at 1 mA force current is recorded using a fresh device. Each group of dots is representing100 pulses. In total each device is stressed with about 500 to 600 pulses up to >25 A.

3.6.1 Spot Leakage Drift

Fig. 23 shows the multi-pulse DC spot leakage current drift at 5 V reverse working voltage. MLV-1 shows extremelyhigh drift and was destroyed at 25 A and about 100 pulses. MLV-2 shows significant multi-pulse drift. The TVS isextremely stable and shows no multi-pulse degradation. The variation is due to the measurement limits of the sourcemeter at low currents (noise).

0

5

10

15

20

25

30

35

10-11 10-10 10-9 10-8 10-7 10-6 10-5

TLP

Cur

rent

(A

)

Spot Leakage Current (A)


Figure 23: Multi-pulse DC spot leakage current drift at 5 V reverse working voltage. TLP-parameter: 50 Ω, 100 nspulse width, 1 ns rise time.




3.6.2 Breakdown Voltage Drift

Fig. 24 shows the multi-pulse breakdown voltage drift at 1 mA force current. MLV-1 and MLV-2 show significant multi-pulse degradation. The TVS has zero drift in breakdown voltage at each group of 100 stress pulses up to >25 A (total600 stress pulses).

0

5

10

15

20

25

30

35

10 15 20 25

TLP

Cur

rent

(A

)

Breakdown Voltage (V)


Figure 24: Multi-pulse breakdown voltage drift at 1 mA force current. TLP-parameter: 50 Ω, 100 ns pulse width, 1 nsrise time.



REFERENCES

References

[1] International Electrotechnical Commission, “Electromagnetic compatibility (EMC) - Part 4-2: Testing and mea-surement techniques - Electrostatic discharge immunity test”, 9th December 2008, ISBN 2-8318-1019-7,http://www.iec.ch/.

[2] International Electrotechnical Commission, “Electromagnetic compatibility (EMC) - Part 4-4: Testing and mea-surement techniques - Electrical fast transient/burst immunity test”, 8th July 2004, ISBN 2-8318-7567-6,http://www.iec.ch/.

[3] International Electrotechnical Commission, “Electromagnetic compatibility (EMC) - Electromagnetic compatibility(EMC) - Part 4-5: Testing and measurement techniques - Surge immunity test”, 29th November 2005, ISBN 2-8318-8371-7, http://www.iec.ch/.

[4] A. Amerasekera, C. Duvvury, W. Anderson, H. Gieser and S. Ramaswamy, ESD in Silicon, John Wiley & Sons,Ltd, Baffins Lane, Chichester, West Sussex PO 19 1UD, England, 2 Edition, 2002.

[5] Albert Z. H. Wang, On-Chip ESD Protection for Integrated Circuits - An IC Design Perspective, Kluwer AcademicPublishers, 2002.

[6] JEDEC Solid State Technology Association, “Electrostatic Discharge (ESD) Sensitivity Testing Human Body”,JEDEC Standard JESD22-A114E, January 2002, http://www.jedec.org.

[7] JEDEC Solid State Technology Association, “Recommended ESD Target Levels for HBM/MM Qualification”,JEDEC Publication JEP155, August 2008, http://www.jedec.org.

[8] T. Maloney and N. Khurana, “Transmission Line Pulsing for Circuit Modeling of ESD Phenomena”, in Proc. onEOS/ESD Symp., pp. 49–54, 1985.

[9] Inc. GGB Industries, 2010.

[10] Inc. Cascade Microtech, 2010.


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