design of digital test chip, 1.2 ghz pll and 2 ghz...
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DESIGN OF DIGITAL TEST CHIP, 1.2 GHz PLL and 2 GHz LNA
BY
ROVSHAN FIKRET RUSTAMOV, B.Tech
A dissertation submitted to the Graduate School
in partial fulfillment of the requirements
for the degree
Master of Sciences, Engineering
Specialization in: Electrical Engineering
New Mexico State University
Las Cruces, New Mexico
January 2014
“DESIGN OF DIGITAL TEST CHIP, 1.2 GHz PLL and 2 GHz LNA,” a disser-
tation prepared by ROVSHAN FIKRET RUSTAMOV in partial fulfillment of the
requirements for the degree, Master of Sciences has been approved and accepted
by the following:
Linda LaceyDean of the Graduate School
Chair of the Examining Committee
Date
Committee in charge:
Dr. Paul M. Furth, Associate Professor, Chair.
Dr. Wei Tang, Assistant Professor.
Dr. Ou Ma, Professor.
ii
DEDICATION
Thankfully dedicated to my parents for their belief in me and patience, as
well as to my teachers who gave me future.
iii
ACKNOWLEDGMENTS
I would like to thank my adviser Dr.Paul Furth for helping me with a huge
work related to my thesis. He also helped me to get the IBM 180nm technology
process up and running, without that, this thesis wouldn’t be done. He was also
the first person who actually taught me the basics of VLSI, starting from the
layout of the basic transistor. I have to admit, that everything related to VLSI
for me starts from Dr.Furth. Every time when I approached Dr.Furth with some
new circuit to know his opinion, he was giving a valuable and interesting advice.
He spent a lot of time outside of the class helping me out with different non trivial
technical issues and I appreciate that a lot. I also liked the way he teaches his
VLSI related classes, I liked his challenging exams and it was actually fun to go
through all that. I think that he is not only a great professor but a great IC
engineer with a rich experience!
I would like to thank Dr.Jeanine Cook who allowed me to be a part of
an interesting projects. While working on those projects I learned how to code
digital circuits for programmable logic devices, to model algorithms for further
implementation on an embedded systems, to design PCBs with high-speed digital
devices and many other important skills. I would not have learned all that if it
wasn’t Dr.Cook and challenging and interesting projects which were led by her. I
also highly appreciate her financial support to me as a student during a very long
iv
time. I learned a lot from Dr.Cook and I respect her as a hard working professor
and a strong personality.
I want to thank Dr.Muhammad Dawood for his help in RF lab and for the
time he spent giving valuable advices related to RF measurements. I appreciate
that he shared his knowledge and expertise in RF theory and measurements with
me.
I want to thank Dr.Jaime Ramirez for teaching me about op-amps and
transconductance amplifiers during an analog VLSI class. He is a great teacher
and always open to discuss interesting circuits and technical ideas related to analog
VLSI.
I also want to thank Dr.Steven Stochaj for teaching me a digital logic design
in a unique and interesting way and for discussing different technical projects I
was working on.
I want to thank my committee members Dr.Ou Ma and Dr.Wei Tang for
attending my defense. Dr.Ou Ma also provided me with an opportunity to work
on an electronic part of the project related to inertial property algorithm verifica-
tion. Dr.Wei Tang involved me into a system-on-chip smart sensor miniaturization
project.
And of course I would like to thank all members of NMSU ECE team whom
I used to come across with and who were nice to me.
v
ABSTRACT
DESIGN OF DIGITAL TEST CHIP, 1.2 GHz PLL and 2 GHz LNA
BY
ROVSHAN FIKRET RUSTAMOV, B.Tech
Master of Sciences, Engineering
Specialization in Electrical Engineering
New Mexico State University
Las Cruces, New Mexico, 2014
Dr. Paul M. Furth, Chair
The Phase-Locked Loop (PLL) and Low Noise Amplifier (LNA) are integral
parts of any modern on-chip RF system. The design of integrated PLL and LNA
circuits operating at high frequency is challenging, especially using the non-trivial
180nm technology process. This thesis covers the design of High-Speed Digital
Test Chip, 1.2 GHz PLL and 2 GHz Common-Source LNA using the IBM 180nm
CMOS 7RF process.
vi
TABLE OF CONTENTS
TABLE OF CONTENTS xi
LIST OF TABLES xi
LIST OF FIGURES xii
1 INTRODUCTION 1
1.1 Purpose of this work . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Organization of work . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 IC Design CAD Flow 4
2.1 Setup of Main IC Design Program - Virtuoso . . . . . . . . . . . . 4
2.1.1 Preparing the Operating System for Virtuoso Setup . . . . 4
2.1.2 Setup of Virtuoso . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 IBM 180nm CMRF7SF Design Kit integration into Virtuoso . . . 7
2.3 Design Verification Package - Assura . . . . . . . . . . . . . . . . 9
2.3.1 DRC Operation . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.2 LVS Operation . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.3 Layout Extraction . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Simulating Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.1 MMSIM operation . . . . . . . . . . . . . . . . . . . . . . 14
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2.4.2 GoldenGate Operation . . . . . . . . . . . . . . . . . . . . 16
3 Digital Test Chip 18
3.1 Ring Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1.1 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Digital Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.1 Unit inverter capacitance . . . . . . . . . . . . . . . . . . . 21
3.2.2 Design and optimization . . . . . . . . . . . . . . . . . . . 27
3.3 Voltage Level Converter . . . . . . . . . . . . . . . . . . . . . . . 31
3.3.1 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.4.1 ESD event types . . . . . . . . . . . . . . . . . . . . . . . 33
3.4.2 ESD Protection Methods . . . . . . . . . . . . . . . . . . . 34
3.4.3 ESD cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.4.4 Power Clamp . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.5 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.5.1 Simulation of inverter delay . . . . . . . . . . . . . . . . . 37
3.5.2 Simulation of Ring Oscillator with fixed 1.8V voltage . . . 38
3.5.3 Simulation of Ring Oscillator with variable voltage . . . . 39
3.5.4 Simulation of Digital Buffer . . . . . . . . . . . . . . . . . 41
3.6 Pad Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.7 Test PCB Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.7.1 Test PCB Schematics . . . . . . . . . . . . . . . . . . . . . 50
3.7.2 Test PCB Layout . . . . . . . . . . . . . . . . . . . . . . . 55
3.8 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.8.1 Measurements of Variable 31-Stage Ring Oscillator . . . . 61
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3.8.2 Measurements of Fixed 1.8V 31-Stage Ring Oscillator . . . 66
3.8.3 Measurement of the Digital Output Buffer Performance . . 69
3.9 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
3.10 Micrographs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4 1.2 GHz Fixed Frequency Multiplying DPLL 77
4.1 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.2 PFD Operation and Design . . . . . . . . . . . . . . . . . . . . . 78
4.3 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
4.4 Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4.5 Voltage Controlled Oscillator . . . . . . . . . . . . . . . . . . . . . 85
4.6 Divider Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.7 Clock Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.8 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.8.1 Simulation of the PFD and Charge Pump . . . . . . . . . 88
4.8.2 Simulation of VCO . . . . . . . . . . . . . . . . . . . . . . 91
4.8.3 Simulation of the complete DPLL . . . . . . . . . . . . . . 93
4.9 Test PCB Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.9.1 Test PCB Schematics . . . . . . . . . . . . . . . . . . . . . 97
4.9.2 Test PCB Layout . . . . . . . . . . . . . . . . . . . . . . . 100
4.10 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.10.1 General measurement . . . . . . . . . . . . . . . . . . . . . 105
4.10.2 Phase Noise measurement . . . . . . . . . . . . . . . . . . 106
4.10.3 Time Jitter Approximation . . . . . . . . . . . . . . . . . 112
4.11 Conclusion and Future Work . . . . . . . . . . . . . . . . . . . . . 113
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5 2 GHz Low Noise Amplifier 115
5.1 Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
5.1.1 Theoretical Analysis . . . . . . . . . . . . . . . . . . . . . 115
5.1.2 Practical Implementation . . . . . . . . . . . . . . . . . . . 120
5.2 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.3 Test PCB Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
5.3.1 Test PCB Schematics . . . . . . . . . . . . . . . . . . . . . 127
5.3.2 Test PCB Layout . . . . . . . . . . . . . . . . . . . . . . . 130
5.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.4.1 Measurement Results . . . . . . . . . . . . . . . . . . . . . 133
5.4.2 Investigation . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.5 Design Modification . . . . . . . . . . . . . . . . . . . . . . . . . . 149
5.6 Conclusions and Future Work . . . . . . . . . . . . . . . . . . . . 159
Appendices 161
APPENDIX A REFERENCES 162
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LIST OF TABLES
3.1 Transistor sizes for inverter . . . . . . . . . . . . . . . . . . . . . . 20
3.2 Typical capacitance values for generic 180nm CMOS process . . . 22
3.3 Buffer sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.4 Transistor sizes for voltage level shifter . . . . . . . . . . . . . . . 32
3.5 Digital Test Chip PCB Layers stackup . . . . . . . . . . . . . . . 55
3.6 Measurement results of Variable Ring Oscillator . . . . . . . . . . 61
4.1 Transistor sizes for the VCO . . . . . . . . . . . . . . . . . . . . . 87
4.2 Phase Noise of DPLL at the offset frequencies . . . . . . . . . . . 112
5.1 Measured output power given the input power at 2 GHz . . . . . 139
5.2 DC current under different supply and bias conditions . . . . . . . 149
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LIST OF FIGURES
3.1 Ring oscillator composed of 31 inverters. . . . . . . . . . . . . . . 19
3.2 Single inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 AC Test bench for computation of capacitor value . . . . . . . . . 24
3.4 Plot of the capacitance for the ideal test bench . . . . . . . . . . . 25
3.5 Testbench for input inverter capacitance measurement . . . . . . . 25
3.6 Capacitance plot for the inverter input. Red: vb = 0V, Green: vb= 0.9V, Blue: vb = 1.8V . . . . . . . . . . . . . . . . . . . . . . 26
3.7 Testbench for output inverter capacitance measurement . . . . . . 27
3.8 Capacitance plot for the inverter output. Red: vb = 0V, Green: vb= 0.9V, Blue: vb = 1.8V . . . . . . . . . . . . . . . . . . . . . . 27
3.9 Digital buffer schematic . . . . . . . . . . . . . . . . . . . . . . . 30
3.10 Voltage level shifter . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.11 ESD protection mechanizm . . . . . . . . . . . . . . . . . . . . . 35
3.12 ESD cell used on every I/O pad . . . . . . . . . . . . . . . . . . . 36
3.13 Power clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.14 Unit inverter delay . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.15 Transient simulation of 31 stage ring oscillator . . . . . . . . . . . 39
3.16 Simulation testbench for ring oscillator with variable voltage supply 39
3.17 Simulation plot for the variable ring oscillator . . . . . . . . . . . 40
3.18 Simulated output frequencies for variable supply ring oscillator . . 41
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3.19 Testbench for buffer delay simulation . . . . . . . . . . . . . . . . 41
3.20 Simulation plot of input and output signals for a digital buffer . . 42
3.21 Simulated delays of the buffer for different values of parasitic outputcapacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.22 Testbench for digital buffer with transmission line and parasitics . 44
3.23 Buffer simulation at 250 MHz . . . . . . . . . . . . . . . . . . . . 45
3.24 Buffer simulation at 1 GHz . . . . . . . . . . . . . . . . . . . . . . 45
3.25 Buffer simulation at 2 GHz . . . . . . . . . . . . . . . . . . . . . . 46
3.26 Buffer simulation at 3 GHz . . . . . . . . . . . . . . . . . . . . . . 46
3.27 Floorplan of the pad frame . . . . . . . . . . . . . . . . . . . . . . 48
3.28 Schematics of the Digital Test Chip PCB . . . . . . . . . . . . . . 51
3.29 Schematics of the Digital Test Chip PCB . . . . . . . . . . . . . . 52
3.30 Schematics of the Digital Test Chip PCB . . . . . . . . . . . . . . 53
3.31 Schematics of the Digital Test Chip PCB . . . . . . . . . . . . . . 54
3.32 Digital Test Chip top layer . . . . . . . . . . . . . . . . . . . . . . 56
3.33 Digital Test Chip internal layer 1 . . . . . . . . . . . . . . . . . . 57
3.34 Digital Test Chip internal layer 2 . . . . . . . . . . . . . . . . . . 58
3.35 Digital Test Chip bottom layer . . . . . . . . . . . . . . . . . . . 59
3.36 Digital Test Chip test board photo . . . . . . . . . . . . . . . . . 60
3.37 Measurement for 0.69V supply . . . . . . . . . . . . . . . . . . . . 63
3.38 Measurement for 0.79V supply . . . . . . . . . . . . . . . . . . . . 63
3.39 Measurement for 0.93V supply . . . . . . . . . . . . . . . . . . . . 64
3.40 Measurement for 1.15V supply . . . . . . . . . . . . . . . . . . . . 64
3.41 Simulated vs measured output frequencies for variable supply ringoscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.42 Scope snapshot of 404 MHz signal from signal generator . . . . . 66
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3.43 Spectrum analyzer snapshot of 404 MHz signal from signal generator 67
3.44 Frequency measurement of ring oscillator using scope . . . . . . . 68
3.45 Amplitude measurement of ring oscillator using scope . . . . . . . 69
3.46 Frequency measurement of ring oscillator using spectrum analyzer 70
3.47 Spectrum power measurement of buffer output at 500 MHz . . . . 71
3.48 Spectrum power measurement of buffer output at 1 GHz . . . . . 71
3.49 Spectrum power measurement of buffer output at 1.5 GHz . . . . 72
3.50 Spectrum power measurement of buffer output at 2 GHz . . . . . 72
3.51 Spectrum power measurement of buffer output at 2.5 GHz . . . . 73
3.52 Spectrum power measurement of buffer output at 2.7 GHz . . . . 73
4.1 Block diagram of DPLL . . . . . . . . . . . . . . . . . . . . . . . 78
4.2 Schematics of the Phase Frequency Detector . . . . . . . . . . . . 79
4.3 Schematics of the symmetric NAND2 gate . . . . . . . . . . . . . 80
4.4 Schematics of a basic charge pump . . . . . . . . . . . . . . . . . 81
4.5 Schematics of a charge pump with floating current source . . . . . 82
4.6 Schematics of the RC loop filter . . . . . . . . . . . . . . . . . . . 84
4.7 Schematics of the current-starved Voltage Controlled Oscillator . 86
4.8 Schematics of the divide-by-6 unit . . . . . . . . . . . . . . . . . . 87
4.9 Schematics of PFD and Charge Pump testbench . . . . . . . . . . 88
4.10 PFD simulation with clkb clock lagging by 1.5 ns . . . . . . . . . 89
4.11 PFD simulation with clka clock lagging by 1.5 ns . . . . . . . . . 89
4.12 PFD simulation with clka and clkb clocks perfectly aligned . . . . 90
4.13 PFD simulation with clka and clkb clocks perfectly aligned, zoomed 90
4.14 Kvco simulation plot for VCO . . . . . . . . . . . . . . . . . . . . 91
4.15 Kvco simulation plot for VCO, zoomed . . . . . . . . . . . . . . . 92
xiv
4.16 Phase Noise simulation of the VCO . . . . . . . . . . . . . . . . . 92
4.17 Testbench of DPLL . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.18 Simulation plot for 100 ns . . . . . . . . . . . . . . . . . . . . . . 94
4.19 Simulation plot for last 24 ns . . . . . . . . . . . . . . . . . . . . 96
4.20 Schematics of DPLL PCB testbench . . . . . . . . . . . . . . . . 98
4.21 Schematics of DPLL PCB testbench on-board power supply . . . 99
4.22 Testbench PCB, top layer . . . . . . . . . . . . . . . . . . . . . . 100
4.23 Testbench PCB, internal layer one . . . . . . . . . . . . . . . . . . 101
4.24 Testbench PCB, internal layer two . . . . . . . . . . . . . . . . . 102
4.25 Testbench PCB, bottom layer . . . . . . . . . . . . . . . . . . . . 103
4.26 Photo of the finished PCB containing manufactured DPLL chip . 104
4.27 3 GHz span snapshot from spectrum analyzer . . . . . . . . . . . 105
4.28 Signal power at 1 KHz offset . . . . . . . . . . . . . . . . . . . . . 107
4.29 Signal power at 10 kHz offset . . . . . . . . . . . . . . . . . . . . 108
4.30 Signal power at 100 kHz offset . . . . . . . . . . . . . . . . . . . . 108
4.31 Signal power at 1 MHz offset . . . . . . . . . . . . . . . . . . . . . 109
4.32 Signal power at 10 MHz offset . . . . . . . . . . . . . . . . . . . . 110
4.33 Signal power at 100 MHz offset . . . . . . . . . . . . . . . . . . . 111
5.1 Schematics of the common-source LNA . . . . . . . . . . . . . . . 116
5.2 Model of common-source LNA with inductive feedback . . . . . . 116
5.3 Testbench for the LNA . . . . . . . . . . . . . . . . . . . . . . . . 120
5.4 Two stage LNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.5 Simulated S11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
5.6 Simulated S21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
5.7 Simulated S12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
xv
5.8 Simulated S22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
5.9 Simulated S22, without feedback resistor at the second stage . . . 124
5.10 Simulated Noise Figure . . . . . . . . . . . . . . . . . . . . . . . . 125
5.11 Input referred 1dB compression plot . . . . . . . . . . . . . . . . . 126
5.12 LNA1 test PCB, chip under test . . . . . . . . . . . . . . . . . . . 128
5.13 LNA1 test PCB, on-board power supply . . . . . . . . . . . . . . 129
5.14 PCB Layout, Top layer . . . . . . . . . . . . . . . . . . . . . . . . 130
5.15 PCB Layout, First internal layer, Ground . . . . . . . . . . . . . . 130
5.16 PCB Layout, Second internal layer, Power . . . . . . . . . . . . . 131
5.17 PCB Layout, Bottom layer . . . . . . . . . . . . . . . . . . . . . . 131
5.18 Photo of the manufactured and assembled PCB for LNA . . . . . 132
5.19 Measurement of output signal power at 2 GHz, -30 dBm input signal134
5.20 Measured S11 with -5 dBm power . . . . . . . . . . . . . . . . . . 135
5.21 Measured S21 with -5 dBm power . . . . . . . . . . . . . . . . . . 136
5.22 Measured S11 with 0 dBm power . . . . . . . . . . . . . . . . . . 137
5.23 Measured S21 with 0 dBm power . . . . . . . . . . . . . . . . . . 138
5.24 Measured S21 at 3.6V supply . . . . . . . . . . . . . . . . . . . . 140
5.25 Ls inductor parameters in the left branch . . . . . . . . . . . . . . 142
5.26 Ls inductor parameters in the right branch . . . . . . . . . . . . . 143
5.27 Lo inductor parameters in the left branch . . . . . . . . . . . . . . 144
5.28 Lo inductor parameters in the right branch . . . . . . . . . . . . . 145
5.29 Lg inductor parameters in the left branch . . . . . . . . . . . . . . 146
5.30 Lg inductor parameters in the right branch . . . . . . . . . . . . . 147
5.31 LNA schematics with each inductor replaced by Momentum gener-ated model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
5.32 Schematics of the modified LNA . . . . . . . . . . . . . . . . . . . 150
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5.33 Lg inductor parameters for Modified LNA . . . . . . . . . . . . . 151
5.34 Ls inductor parameters for Modified LNA . . . . . . . . . . . . . 152
5.35 Lo inductor parameters for Modified LNA . . . . . . . . . . . . . 153
5.36 Testbench for the modified LNA . . . . . . . . . . . . . . . . . . . 154
5.37 S11 of Modified LNA . . . . . . . . . . . . . . . . . . . . . . . . . 155
5.38 S21 of Modified LNA . . . . . . . . . . . . . . . . . . . . . . . . . 155
5.39 S12 of Modified LNA . . . . . . . . . . . . . . . . . . . . . . . . . 156
5.40 S22 of Modified LNA . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.41 Noise Figure of Modified LNA . . . . . . . . . . . . . . . . . . . . 157
5.42 S11 and S22 of the modified LNA using Spectre models for Inductors158
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Chapter 1
INTRODUCTION
The development cycle for an Integrated Circuit (IC) is a complex and dif-
ficult process. It involves design parameters specification, CAD flow setup and
configuration, technology design kit integration with CAD flow, circuit design,
simulation, layout, layout extraction and post-layout simulation, pad frame inte-
gration with ESD, design rule versus schematic checks (DRC/LVS), bonding dia-
gram setup for manufacturing foundry, quality PCB design for high-speed digital
or RF IC’s and evaluation of IC with high-speed and RF measurement equipment.
This work covers the complete development cycle described above for dif-
ferent types of Integrated Circuits from Mixed-Signal, analog and RF areas. It
also covers the proper setup and configuration of IC CAD tools.
1.1 Purpose of this work
This work is intended to present the design and testing of (1) a Digital
Test Chip, (2) a 2 GHz Low Noise Amplifier (LNA) and (3) a 1.2 GHz Fixed
Frequency Digitally Controlled Phase Locked Loop (DPLL) integrated circuits.
Each integrated circuit covered in this work belongs to a separate field of IC
Design. Design and testing challenges for each chip are thoroughly described. This
work truly reflects the tough engineering hurdles which IC designers in industry
have to face in order to deliver a working product, which is a modern non-trivial
integrated circuit operating at high frequency. High operating frequency of the
chips, whether it is an RF chip or digital one, further increases the difficulty of
1
design as well as test procedures. This work describes how specific challenges and
technical issues were handled.
Another important aspect of IC design is mastering the CAD flow which is
the main tool used for design entry and layout submission to the manufacturing
foundry. Understanding the CAD flow and IC Design Kit integration with it is
crucial. A simple error made during the integration of the design process due to,
for example, device primitive misuse, could lead to a fatal design error not caught
by DRC or LVS procedures. The result could be fabrication of a faulty integrated
circuit which in its turn results in huge financial loss for a company. Although
most of the time the CAD flow setup and Design Kit integration processes are
rather similar for most of technologies, there are many details specific to each
foundry and technology process. This work is done on the 180nm IBM process
with the CMRF7SF Design Kit. It covers the complete Cadence IC Design CAD
flow setup and its configuration with the IBM CMRF7SF Design Kit and thus
can be used as a manual.
1.2 Organization of work
This document is organized as follows.
Chapter 2 gives a detailed description of IC CAD tools and the design flow
used in this work. Proper CAD tool configuration is described thoroughly, as well
as the setup procedures for the Design Kit installation and its integration with
the IC CAD flow.
Chapter 3 describes the complete development cycle for a Digital Test Chip
which is composed of Ring Oscillators, Voltage Level shifters, Digital Buffers, a
custom pad frame and ESD cells aligned in a pad frame. This chapter demon-
strates the design process, schematics entry, simulations, layout entry, test PCB
design, testing and results interpretation.
2
Chapter 4 details the development of a 1.2 GHz fixed frequency Digital
PLL. The design process of every building block of the PLL is described as well
as the fine tuning of schematics in order to meet requirements. Schematics and
simulations are discussed. Test PCB design and testing methods are covered as
well.
Chapter 5 describes the complete development cycle for a 2 GHz LNA.
It covers the design process and aspects of optimizing the circuit for a required
frequency response, fine tuning the LNA circuit, layout issues, simulation and test
RF PCB design and testing.
3
Chapter 2
IC Design CAD Flow
This chapter presents the CAD related material necessary for proper IC
design flow setup and configuration in order to successfully perform the IC design
entry with further simulation, layout, post-layout simulation and generation of
the GDS files suitable for the manufacturer of the chip. The purpose, operation
and proper configuration of each part of the Cadence IC Design CAD system are
described. The information regarding the configuration steps of IBM Design Kits
into the Cadence IC CAD environment is presented as well.
2.1 Setup of Main IC Design Program - Virtuoso
This section describes steps which have to be performed in order to properly
setup the main IC CAD program from Cadence which is called Virtuoso and
designed for the RHEL Linux Operating System.
2.1.1 Preparing the Operating System for Virtuoso Setup
Officially the Cadence IC Design flow is supported on RHEL and SUSE
Linux operating systems. In our case, however, we are using the free CentOS
operating system which is basically a clone of RHEL-like Linux OS. After the
installation of CentOS on a clean PC we first must make sure that all the neces-
sary libraries and packages which are used by the Cadence Installscape installer
program or Cadence IC Design flow tools are installed.
In RHEL-like Linux OS software packages can be installed using the yum
installer. That is why in order to start installation of all necessary libraries and
4
packages a user must log in as root and install each package one by one by entering
the following commands:
1. yum install gvim
2. yum install kernel-headers
3. yum install kernel-devel
4. yum install gcc
5. chkconfig kdump off (turn off kdump, by default it is enabled)
6. yum install glibc
7. yum install ld-linux.so.2
8. yum install libXt.so.6
9. yum install libXext.so.6
10. yum install libXp.so.6
11. yum install libXtst.so.6
12. yum install libXrender.so.1
13. yum install libstdc++.so.5
14. yum install libXrandr.so.2
15. yum install ksh
16. yum install libGL.so.1
17. yum install libGLU.so.1
5
18. yum install elfutils
19. yum install elfutils-libelf
20. yum install libelf.so.1
21. yum update (make sure it starts a full update and completes it)
Cadence IC design software uses specific X11 fonts. As a result those fonts
must be present in a system. In order to install them run the following command
as root:
yum list available | grep xorg-x11-font
This will list all the relevant fonts which have to be installed. To install
them, enter the following command as root:
yum install “name of font returned by previous command”
The above command must be repeated for every font type returned by a
previous command. At this stage the OS should have been properly configured
and we can go ahead with the installation of Cadence IC Design software.
2.1.2 Setup of Virtuoso
The main program which has to be installed as a first step is Cadence IC
X.XX, where X.XX is the version and sub-version of the IC CAD software. At
the time of installation the latest software version was IC 6.15.
Most of the Cadence software for IC design flow is installed using the
Installscape application and that is why this application has to be acquired from
Cadence and installed first. After installation and startup of the Installscape
program, we can see a list of available software packages from Cadence under the
current license. Every software package in that list can be downloaded to a local
folder and then installed. At this stage we first navigate to IC6.15 software and
6
proceed with its download and installation process. Upon clicking on it we see
different subversions of IC06.15 software. After the subversion number we notice
a dot with a subsequent .Hotfix or .Update words. .Hotfix is basically a patch and
it requires the base version of the software, whereas .Update is a software update
which includes both a patch and the base software.
After the installation of the latest program subversion of IC6.15, we need
to configure a host name. To do that:
1. Make sure that /etc/sysconfig/network file contains the following lines
NETWORKING=yes
HOSTNAME=“your hostname” (figure it out by typing hostname
in console)
2. Make sure that /etc/hosts file contains following lines:
127.0.0.1 “hostaname”
If not, then just add it.
At this stage, the main IC design program from Cadence should have been
installed. It includes Schematic entry, Layout and default DRC subprograms. It
is also important to add the library and executable directories of the installed
Cadence programs into the PATH environment variable. Usually it is easily done
just by adding it inside the .cshrc file (in case C shell is used). Any other envi-
ronmental variables which set specific Cadence design flow options can be added
in that file as well.
2.2 IBM 180nm CMRF7SF Design Kit integration into Virtuoso
By default the Cadence IC Design Virtuoso program is installed with the
standard elements such as resistors, capacitors, diodes, MOS transistors, different
types of dependent and independent current and voltage sources, and other ele-
7
ments which can be loaded with specific parameters from a file, or right inside a
schematic in its property fields. However, in order to be able to design and sim-
ulate projects for a specific technology process, a vendor kit has to be integrated
into the IC Design Flow environment.
Since we are using the 180nm technology process from IBM, the CMRF7SF
V2.0.0.1 Design Kit has to be integrated into the Cadence IC flow. Below are the
procedures which have to be followed in order to achieve that.
1. After the Base Kit for CMRF7SF 180nm IBM process is downloaded it has
to be unzipped. Inside that folder there is an automated “kit install.pl”
script which will be used for technology kit installation. After running a
script, a series of console questions about installation source, directory and
symbolic link creation appear. The kit needs to be installed in a separate
folder from which the user will be launching the Virtuoso IC design suite.
After the installation, the IBM PDK folder will be created and contains
folders with the specific kit installed, in this case CMRF7SF.
2. Copy the “display.drf” file from IBM PDK/cmrf7sf/relAM/cdslib/cmrf7sf
to the “cadence” folder which was created before the kit installation process.
This file is responsible for proper graphical representation of layout layers
of the design kit.
3. Copy .cdsenv, .cdsinit, .simrc and .cds.lib files from
IBM PDK/cmrf7sf/relAM/cdslib/examples
to the cadence folder as well. The first three files contain startup and work
configuration parameters for the Cadence Virtuoso suite. The last file con-
tains the component libraries list used by Virtuoso.
8
At this stage the Design Kit integration into the Cadence Virtuoso platform
is done. The Virtuoso program should be started from a directory called “cadence”
which contains the “IBM PDK” directory. After a successful launch of Virtuoso
and starting up the library manager, the CMRF7SF related libraries are displayed
in the list of available libraries. Any Design Kit specific primitives can now be
used within any newly created user library.
2.3 Design Verification Package - Assura
Two one of the most important operations which have to be done after
layout completion are Design Rule Check (DRC) and Layout Versus Schematic
(LVS). The first operation makes sure that none of the technology process related
rules are violated during layout. The second operation makes sure that the layout
properly corresponds to the schematic, i.e. the device primitives are layed out
and interconnected in a way that properly corresponds to the schematic. Thus
proper configuration and operation of the Assura verification package is necessary.
Another important operation for verification is extraction of parasitic elements of
the layout for a more realistic simulation. This operation is done using the Assura
QRC package.
The setup of the Assura package itself is rather trivial. It can be installed
through the Installscape program which was used before in order to install the
main Virtuoso program. After install then, the program library and executable
folders have to be appended to the “PATH” environment variable as well.
2.3.1 DRC Operation
The design rule check operation ensures that current layout follows the
process rules. It is generally recommended to run this operation often, especially
when one works on non trivial design kits, such as CMRF7SF from IBM. Once
the Assura package is properly inistalled and integrated with the main flow, after
9
running Virtuoso, the “Assura” Menu should appear on a top menu bar. After
opening a layout cell, and selecting “Assura→Run DRC”, a window with DRC
configuration parameters comes up. The user can define DRC parameters as well
as tell which directory should contain run files, define run name, etc.
The important fields here to enter are the “Rules file” and the “Switch
Names”. The “Rules File” field should contain the path to the rules file specific
to our process, CMRF7SF. In our case the path is:
“/IBM PDK/cmrf7sf/relAM/Assura/DRC/drc.rul”.
The “Switch Names” field contains specific check options for DRC. In our case,
for most of the time, we are going to use “GridCheck” option, which makes sure
that all layout elements are aligned within the allowed grid.
After the DRC operation with ”drc.rul” file is completed, it is mandatory
to check proper layer densities. Those checks are done using another set of rules
contained in the “local.rul” file. Once the Rules File field is changed to “local.rul”,
which is contained in the same directory as the “drc.rul” file, the “Switch Names”
field can be set to a specific check name which corresponds to a layer of interest.
It can be “CA DENSITY” check which checks the density of vias, or any other
check for active areas, or any metal density check. Most of the time density errors
arise in a situation when, for example, the design contains large planes for power
with many vias located close to each other. For a single relatively small cell, it
is usually not an issue, but once the design is assembled from many smaller cells
and gets much bigger and contains more area with dense vias, the density rules
may then be violated. That is why it is mandatory to perform the density checks
in the CMRF7SF process both for metals, vias and actuve areas. This type of
check is performed usually less often than the general design rule check with the
“drc.rul” file.
10
2.3.2 LVS Operation
Layout Versus Schematic operation makes sure that our layout properly
corresponds to the schematic. It is normally run after the cell has been com-
pletely layed out and DRC operation was successfully performed. Before the LVS
procedure the schematic information has to be exported in to a netlist file. In our
case, this is done in two steps:
1. Select “IBM PDK→Netlist→Create CDL Netlist” from the top menu. This
operation will create a netlist from the current schematic. The netlist file
will have “.netlist” extension.
2. Select “IBM PDK→Netlist→CDL Pre processor for LVS” from top menu.
This operation will convert the netlist created in the previous step into the
format suitable for the LVS procedure. The produced file will have the
“.netlist.lvs” extension.
Once the above two operations are done, the user can open the finalized
layout view of the cell and invoke the LVS operation. This can be done by selecting
“Assura→Run LVS”. After that is done, a window comes up with LVS parameters.
Parameters contain layer information and rule files as well as a reference to the
netlist produced from the schematic. The following parameters have to be entered:
1. Schematic Design Source field should be set to Netlist.
2. Netlist file(s) field has to be set to a path pointing to the file which will have
the same name as the schematic file but with “.netlist.lvs” extension. That
file is produced in step 2 of the netlist generation process described above.
3. Extract Rules field should be set to:
“/IBM PDK/cmrf7sf/relAM/Assura/LVS/extract6.rul”
11
4. Compare Rules field should be set to:
“/IBM PDK/cmrf7sf/relAM/Assura/LVS/compare.cdl”
5. Binding File(s) field should be set to:
“/IBM PDK/cmrf7sf/relAM/Assura/LVS/bind.cdl”
6. RSF Include field should be set to:
“/IBM PDK/cmrf7sf/relAM/Assura/LVS/LVSinclude.rsf”
At this stage, all parameters are set correctly, and the “OK” button can
be pressed to run the LVS procedure. If the layout matches the schematic and no
errors occure, another window pops up saying that netlists match, otherwise, a
debug window appears with LVS text output information pointing to the device
instantiation or connection error.
2.3.3 Layout Extraction
In order to simulate the design after layout is done including all the par-
asitic parameters the extraction operation has to be performed. In our case
the Cadence QRC package is used to perform the extraction operation of the
layout cells. Cadence QRC has to be properly integrated into the main Vir-
tuoso flow. In order to do that, first, after installation of the QRC package,
which installs into the “EXT” folder, executable and library folders within the
“EXT” folder have to be added into the PATH environment variable. Second, the
QRC ENABLE EXTRACTION environment variable has to be created with the
value “t”. After completion of the above steps, the “QRC” menu should appear
in the menubar when opening the layout cell with layout editor in Virtuoso.
At this stage, given the fact that DRC and LVS operations are successfully
completed, we can start the extraction operation. The following steps have to be
done:
12
1. Select “QRC→Setup” QRC from the top menu and setup the extraction
process according to your requirements. In our case the default output
format was chosen to be “Lvs Extracted View”. Desired extraction types
and options can be set in the “Extraction” tab. The technology should be
set to “av7rfLVS”.
2. Once settings are saved and applied, “QRC→Run Assura-QRC” should be
selected from the top menu. In the open window choose the run directory
in which the LVS process was performed and press “OK”. In the case of
the current IBM kit at this stage a message usually appears saying “No
technology directory found”, however, the extraction process runs properly,
so it is just safe to press the “Close” button on the current message window.
3. At this stage the “QRC (Assura) Parasitic Extraction Run Form” window
pops up. The “Setup Dir” field should point to:
“/IBM PDK/cmrf7sf/relAM/Assura/QRC/6LM”
The output should be set to “Lvs extracted View” and “Cell View Check”
should be marked. Now the “OK” button should be pressed. The extraction
process will start working. Its status will be indicated in a small window
on the low right area of the screen. Upon completion, a “QRC Run” win-
dow should pop up saying that the QRC run completed successfully and
point to the cell view named ”av extracted” located within the current cell
subdirectory.
It is possible to open the ”av extracted” cell with the layout editor and
observe the schematic symbol of substrate ground on the ground connections, as
well as some extraction parameters marked near different parts of the cell layout.
In order to perform simulation with the extracted view as the source the ”Switch
13
View List” inside the ”Environment” section of ADE should have ”av exctracted”
parameter appearing first.
2.4 Simulating Design
Two simulation packages are used in our case to simulate the designs,
one is MMSIM from Cadence another is GoldenGate from Agilent. The MMSIM
software is mainly used to simulate different types of mixed signal circuits working
on a relatively low to moderate frequencies, whereas GoldenGate simulator is used
to simulate mainly RF IC’s working on a high frequencies.
2.4.1 MMSIM operation
The setup of the MMSIM simulator from Cadence is rather trivial, just as it
is the case with many other addons which are supposed to be setup and integrated
with the main flow. The setup is performed by the Installscape Cadence software
installation program. As always, the environmental variables pointing to the
program executables within the MMSIM install folder must be declared in the
.cshrc configuration file.
Below are the required steps in order to simulate the schematics with MM-
SIM:
1. The first step in order to configure the design for simulation is to create the
simulation cell for the current design. This can be easily done by selecting
“Launch→ADE GXL” and selecting “Create a new view”.
2. Once the ADE GXL view is selected we can create a specific test. It is done
by selecting “ADE GXL→Create→Test” from the top menu. After that,
the data view window on the left side of the screen will display the newly
created test name.
14
3. At this stage, the model libraries corresponding to CMRF7SF IBM process
have to be pointed out for MMSIM. In order to do that, the test name on
the left data view window has to be clicked twice to bring up the ADE XL
Test Editor. In a new window, “Setup→Model Libraries” must be selected
to bring the Model Library Setup window. Here we need to point the three
main model libraries: allModels.scs, design.scs and wafer.scs. Next to the
allModels.scs file, the user can select the desired process corner to be used
during a simulation. Those libraries contain simulation information for all
device models, wafer parameters and the corners.
4. Define whether the simulation is done over the schematics or over the ex-
tracted layout information available within a cell. This is done by selecting
“Setup→Environment” menu selection from the ADE XL Test Editor win-
dow. The new window which pops up has a field called “Switch View List”.
If the first item appearing in that list is “spectre” and the “Stop View List”
is “spectre” as well, the simulation will be done over the schematics. If the
first item in the “Switch View List” is “av extracted”, the simulation will
be done using the extracted post-layout data.
5. The last step is to select and configure the proper type of simulation. Enter
the design variables and outputs to be plotted or saved.
At this stage the design is ready to be run with the MMSIM simulator
simply by pressing the “Run” button on a top menu. Results are shown in the
“adexl” tab of the main window. Plotting options for each result is available in
that tab window as well.
15
2.4.2 GoldenGate Operation
The GoldenGate RFIC simulator is an Agilent software package and it
needs to be setup and integrated with the Cadence environment for proper oper-
ation in our case. Below are the steps required to setup the GoldenGate package
and integrate it with the Cadence environment:
1. Setup the GoldenGate software package following the instructions.
2. Create the “XPEDION” environment variable pointing to the folder where
GoldenGate is installed.
3. Create the “XPEDION CADENCE VERSION” environment variable with
a value 615, this corresponds to the version of Virtuoso we are using.
4. Go to the installation folder of Virtuoso to locate the following file:
”/shared/cdssetup/setup.loc” and add the following line there:
$XPEDION/aa/$XPEDION CADENCE VERSION
5. Append the contents of /aa/.cdsinit home file to the .cdsinit file located in
your “cadence” folder from which Virtuoso is launched.
6. Convert the GoldenGate library primitives to the newer Open Access Ca-
dence format. The utility called ”cdb2oa” should be used for that procedure.
Once the library has been converted, point it to the Cadence environment by
adding an entry specifying its location in the “cds.lib” file within a cadence
folder.
At this stage the GoldenGate configuration and integration with Cadence
environment is complete. We can simulate any cell using the GoldenGate or MM-
SIM simulator now. In order to simulate the cell using the GoldenGate simulator:
16
1. Create an ADE GXL cell and a new test and add the model libraries.
2. In the ADE XL Test Editor select “Setup→Simulator” menu, then select
GoldenGate instead of Spectre.
3. Go to the “Setup→Environment” menu in the ADE XL Test Editor and
select “spectre” view for both the “Switch View” List and “Stop View” List
as a first entry. As a second entry select “schematic” or “av extracted” for
“Switch View” List and “GoldenGate” for Stop View List. As a third entry
select ”GoldenGate” for the “Switch View” List.
4. Set up the analysis type and variables necessary for the simulation.
At this stage if we run the simulation GoldenGate simulator will be used.
17
Chapter 3
Digital Test Chip
This chapter presents the design and implementation of a Digital Test Chip. One
of the main purposes of implementing a Digital Test Chip is to explore and test
the technology process as well as study the limits of digital devices available for
it. The implemented digital test chip includes ring oscillators, voltage level shifter
and digital buffer circuits. The chip will include ring oscillators powered with
constant a 1.8V voltage from the main power supply, as well as ones powered from
external pins in order to provide variable voltage to them. A voltage level shifter
is used to convert the output voltage levels from the adjustable ring oscillators to
1.8V suitable for the digital buffer. The digital buffers are used to drive a high
capacitive external load. The chip also includes instances of ESD cells at each pad
and power clamps integrated into the frame pad. The ESD cells on the pads and
power clamps are used to protect the devices inside the chip from electrostatic
discharge events.
3.1 Ring Oscillator
The ring oscillator is a device composed of inverters connected in series.
When the output of the last inverter is connected to the input of the first inverter
and the number of inverters is odd the ring oscillator starts oscillating. Each
inverter in the chain represents a delay for the inverting signal propagation, thus
by increasing the number of inverters in a chain we increase the delay and make
the output frequency of the ring oscillator smaller.
18
3.1.1 Design
In our case the ring oscillator is composed of 31 inverters connected in
series as shown on Fig. 3.1 The output of last inverter is connected to the input
of the first inverter.
Figure 3.1: Ring oscillator composed of 31 inverters.
Each inverter is composed of PMOS and NMOS transistors interconnected
with a common gate as shown in Fig. 3.2. The body of the PMOS is connected
to the power supply and the body of the NMOS is connected to the substrate
ground.
Figure 3.2: Single inverter
Transistor sizing for inverter is given in Table 3.1
19
Table 3.1: Transistor sizes for inverter
PMOS NMOS
Width 0.8 µm 0.4 µm
Length 0.18 µm 0.18 µm
Fingers 2 2
Since the ring oscillators are composed of unit inverters, each unit inverter
represents some delay. Utilizing the method of logical effort shown in Harris [1]
we see that the delay of each inverter can be computed as in Eq. (3.1)
d = g × h+ p (3.1)
Where d is the unitless delay, h is the electrical effort which has a value of 1
and p is the parasitic delay of an inverter with a value of 1 as well. With the
values given, the normalized delay of each stage turns out to be 2. Since the signal
propagates through the ring oscillator with N stages in circle, the total period of
the ring oscillator is two times 2N . Thus a frequency of the ring oscillator is:
fosc =1
2× 2×N ×Delay(3.2)
From the simulation of the unit inverter shown in Fig. 3.14 Delay is equal
to 12.88 ps. Using this value in Eq. (3.2) gives a frequency of oscillation of the
31-stage ring oscillator in the current process of 626 MHz.
20
3.2 Digital Buffer
Buffers in digital circuits are in general required when a source needs to
drive a load with a higher capacitance. If the source is an inverter it is generally
true that it can handle driving the inputs of another four inverters. Each inverter
or any other logic gate or transistor represents a capacitance at its gate. When
the capacitance load is too high, the inverter cannot handle driving it and a buffer
is required. Buffers usually consist of a series of an even number of inverters. The
first inverter generally has a unit size and subsequent inverters are increased in
size in such a way that a final stage inverter is big enough in order to be able to
drive a load of target capacitance.
In this design, the output of the ring oscillator is required to be connected to
a chip pad and a package pin in order to drive an external load such as electronic
measurement equipment. The load capacitance present at the chip pads and
package pins usually consists of the parasitic capacitance of the pad, the package
parasitic capacitance, the PCB trace capacitance, a parasitic capacitance of an
RF cable connected to the SMA connector on a PCB and the input capacitance of
the measurement equipment. In this case a parasitic capacitance can reach up to
several tens of picofarads or much more if longer SMA cables are used to connect
the output to measurement equipment. It is obvious that a unit sized inverter
at the last stage of a ring oscillator connected to a pad won’t be able to drive
the output. Thus, we need a properly designed digital buffer placed between last
stage of the ring oscillator and the chip output pad.
3.2.1 Unit inverter capacitance
In order to design and optimize our digital buffer, a method of logical effort
will be utilized as described by Harris [1]. The logical effort for any type of gate
is the ratio of its input gate capacitance to the input gate capacitance of a unit
21
inverter. That is why the first important step to complete before proceeding with
the logical effort method for digital buffer design is to figure out the capacitance
at the input and output of the unit inverter. Our unit inverter is composed of
PMOS and NMOS transistors with the sizing shown in Table 3.1. The unit gate
capacitance of our inverter will depend on the gate-drain, gate-source overlap
capacitances and oxide capacitance mainly, as well as the gate-body capacitance
of the transistors typical for common 180nm CMOS process shown in Table 3.2.
Table 3.2: Typical capacitance values for generic 180nm CMOS process
Capacitance Value
Cgso 0.745 fF/µm
Cgdo 0.745 fF/µm
Cox 8.42 fF/µm2
The Cox for this process was approximated from knowledge of the gate
thickness which is 4.1 nm and the relations in Eq. (3.3).
Cox =Eoxtox
, Eox = E0 × 3.9 (3.3)
Where E0 is the permittivity of free space which is 8.85 pF/m, 3.9 is the relative
permittivity of silicon dioxide and tox is the thickness of the gate.
For a crude approximation of an input gate capacitance of the inverter
we can ignore gate-body capacitance and calculate gate-drain and gate-source
capacitances of each transistor and them add all the values up. The gate-drain and
gate-source capacitances of each transistor can be approximated with Eq. (3.4).
22
Cgd = Cgs = W × Cgdo +1
2×W × L× Cox (3.4)
Where W is the width of the transistor, L is the length of the transistor,
Cgdo is gate-drain overlap capacitance, Cgso is gate-source overlap capacitance and
Cox is the oxide capacitance.
Using the Eq. (3.4) and utilizing information from Table 3.1 and Table 3.2
gate capacitance of the PMOS transistor for an inverter is 3.6 fF and the gate
capacitance of the NMOS transistor is 2.4 fF . In order to know more realistic
gate capacitance of the inverter we will have to utilize the design kit in simulation.
One of the two relatively common ways of determining the gate capacitance of
the inverter is to perform DC simulation and extract the operating point model
parameters or to perform an AC simulation and calculate the gate capacitance
based on the relationship of AC current flowing through the capacitance and the
voltage change.
We will use the method of AC simulation for inverter gate capacitance
estimation. In general, the current through the capacitor depends on the voltage
change and the capacitance value as shown in Eq. (3.5)
I = C × dV
dt(3.5)
In order to use the method of the AC simulation for the inverter gate
capacitance approximation we first build a simple testbench in order to validate
this method. The simple setup with ideal capacitor of known value of 3 fF is
shown on Fig. 3.3
The AC source has magnitude 1, the voltage change is observed on node
va, then using Eq. (3.5) the capacitor value is calculated. In order to perform
23
Figure 3.3: AC Test bench for computation of capacitor value
this operation in the MMSIM simulator the following expression for the output
parameter should be entered:
deriv((IF(”/I4/PLUS”) / VF(”/va”) / (2 * pi)))
As a result, after simulation, the capacance is plotted as shown on Fig. 3.4
where a constant 3 fF capacitance is observed over a wide frequency range.
In order to approximate the gate capacitance of the inverter, the ideal
capacitor should be changed to the properly powered inverter as shown on Fig. 3.5
24
Figure 3.4: Plot of the capacitance for the ideal test bench
Figure 3.5: Testbench for input inverter capacitance measurement
After the simulation the capacitance plot is obtained and shown on Fig. 3.6.
We have to note that the inverter will have different voltages at its in-
put during operation. Thus we need to take that fact into account and perform
simulation with three different bias points at the input, 0V, 0.9V and 1.8V. We
25
Figure 3.6: Capacitance plot for the inverter input. Red: vb = 0V, Green: vb =0.9V, Blue: vb = 1.8V
notice that the capacitance value is not constant over a frequency range of 10
GHz, although its variation is small.
Another method for inverter input gate capacitor approximation is simply
extraction of gate capacitance values from the DC operating model parameters.
This method however will give the approximate inverter gate input capacitance
at DC only.
At this stage it is safe to assume that the input gate capacitance is some-
where between of the values corresponding to the biasing of 0V and 1.8V which
is around 2.7 fF.
The next step is to figure out the output capacitance of the inverter. The
testbench is rearranged as shown in Fig. 3.7
The output capacitance plot is shown in Fig. 3.8.
Looking at plots shown in Fig. 3.6 and Fig. 3.8 we can see that approximate
ratio of output and input capacitances for the inverter when it is biased with 0V
or 1.8V is 1, which is supposed to be the logical effort of the unit inverter.
26
Figure 3.7: Testbench for output inverter capacitance measurement
Figure 3.8: Capacitance plot for the inverter output. Red: vb = 0V, Green: vb =0.9V, Blue: vb = 1.8V
3.2.2 Design and optimization
At this stage we can proceed with the method of logical effort for buffer
design and optimization. Our unit capacitance value will be designated as C and
its value assumed to be 2.7 fF . The logical effort of the unit inverter g is 1 due
to the fact that its input and output capacitances are roughly the same.
The buffer designed consists of an even number of inverters connected in
series and representing a path. The path logical effort is the product of logical
27
efforts of each of its elements and can be designated as G. In our case G = 1,
because each element of the path is an inverter with logical effort value of 1.
The path electrical effort H is the ratio of output and input capacitances
of the path. In our case we want to design the buffer with least delay when driving
a 5 pF load. The output capacitance of the path in that case is 5 pF. The input
capacitance of the path will be the capacitance at the input of its first stage,
which is a unit inverter with a known capacitance of 2.7 fF. Note that this does
not mean that the buffer will not be able to drive a load with a higher capacitance
values. By optimizing the design for 5 pF load capacitance we just make sure that
the buffer delay will be the smallest when the load capacitance is 5 pF.
The branching effort b is the ratio of total path capacitance on current
node to the capacitance of the current node and the path branching effort B is
the product of all the branching efforts within a path. In our case path branching
effort is one because every element which is an inverter connected to only one next
inverter.
Knowing the logical, electrical and branching efforts of the path, the total
path effort F can be calculated as shown in Eq. (3.6)
G = 1, B = 1, H =5 pF
2.7 fF= 1852, F = G×B ×H = 1852 (3.6)
Once a path effort is known we must identify the best number of stages for
the buffer. Utilizing the method described by Harris [1] we can approximate the
number of stages for the least delay of the buffer to be:
N = logρ F (3.7)
28
With ρ typically selected between values of 2.4 and 6. In our case we choose
it to be 4, then according to Eq. (3.7) N = 5.43. Taking an integer for a number
of stages we assume a buffer with 6 stages.
The next step is to properly size every stage of the buffer, it is obvious that
the last inverter of the buffer will be the biggest. Our calculation will be based
on the method of finding the best input gate capacitance based on the output
capacitance. This can be calculated as shown in Eq. (3.8):
Cin,i =Cout,i × gi
f(3.8)
Where Cout,i for the last stage has the value of 1852. The effort for the last
stage is f , and computed as:
f = F 1/N (3.9)
According to Eq. (3.9) f turns out to be 3.5. Using the Eq. (3.8), Eq. (3.9)
and logical effort g being 1 we first compute the Cin for the last stage which
turns out to be 529.14. Thus theoretically an inverter 529.14 times stronger than
unit inverter is necessary. We next use the value of 529.14 as Cout and compute
the Cin of the stage next to the last one. In this fashion we must complete the
computation of the input gate capacitance of every stage including the first one.
Once we reach the computation of the first stage, the value is close to 1, which
corresponds to the input gate capacitance of the unit inverter.
After simulating the designed buffer and looking at the edges of the output
signal a decision was made to slighly tweak some of the stages, i.e. using different
amount of unit inverters than was calculated above. The calculated sizes using
29
Eq. (3.8) for each stage with respect to a unit inverter and the actually used
inverter sizes are shown in Table 3.3.
Table 3.3: Buffer sizing
Stagenumber
Calculatedinverter size
Selectedinverter size
6 529.14 576
5 151.18 192
4 43.19 64
3 12.34 16
2 3.52 4
1 1 1
The buffer was constructed as shown in Fig. 3.9
Figure 3.9: Digital buffer schematic
The size of the last stage which is 576 times the size of the unit inverter
was achieved using 9 inverters which are 64 times the unit inverter. The stage 5
inverter is implemented with 3 inverters with size 64, and the stage 4 inverter is
implemented with 4 inverters of size 16.
30
3.3 Voltage Level Converter
The purpose of voltage level converter is to convert voltages from one level
to another. Our Digital Test Chip includes ring oscillators which are powered
with a variable voltage through external pins. As a result the voltage level at the
output of the ring oscillator correspond to the voltage level of the external power
supply. However, the output of any ring oscillator is passed through the digital
buffer before the output pin. All digital buffers integrated in the chip are powered
with main 1.8V supply distributed through the pad frame. As a result, the output
voltage levels of the adjustable ring oscillators must correspond to 1.8V. In order
to achieve that, a voltage level converter has been designed and integrated into
the chip. All of the adjustable ring oscillators powered through the external pin
are followed by a voltage level converter and then a buffer connected to the output
pin. Outputs from the fixed 1.8V ring oscillators are passed to the digital buffers
directly without utilizing the voltage level converter.
3.3.1 Design
A standard method of voltage level conversion utilizing a pair of PMOS
and NMOS transistor together with inverter was used. The schematic is shown
on Fig. 3.10. The rail vdd is 1.8V which appears at the output of the level
converter and the input of the digital buffer. The rail vdd1 is the voltage from
the external pin which powers the variable voltage ring oscillator. The ground rails
vss1 and vss can both be connected to a common substrate ground. Enabled
transmission gate composed of TP8 and TN10 is used to equalize the input
signal propagation delay to transistors TN0 and TN1 .
When the input a is LOW TN0 is OFF and TN1 is ON forcing node z
to LOW which turns ON TP0 . As a result the gate of TP1 is HIGH turning it
OFF.
31
Figure 3.10: Voltage level shifter
When the input a is HIGH, TN1 is OFF and TN0 is ON forcing the
gate voltage of TP1 to LOW and turning it ON. That forces node z to HIGH
and keeps TP0 OFF.
Transistor sizing for the voltage level shifter is given in Table 3.4
Table 3.4: Transistor sizes for voltage level shifter
TP0, TP1 TN0, TN1
Width 0.8 µm 0.4 µm
Length 0.72 µm 0.18 µm
Fingers 2 8
32
The size of the NMOS transistors should be significantly greater than the
size of the PMOS transistors in order to be able to switch from the lower voltages
since the bottom NMOS transistors have to be strong enough in order to pull
their drain voltages down. The ground nodes vss1 and vss are tied to a common
substrate ground.
3.4 ESD Protection
Electrostatic Discharge (ESD) is a high current pulse event which occurs
when a chip comes in contact with the environment. The pins of the chip might
get in cotact with the human body, different parts of machinery handling the
chip or any other entity capable of carrying an electric current. An ESD event
can easily destroy the chip by severely damaging its internal circuitry. An ESD
protection measures are crucial parts of nearly any type of chip made in industry.
Our design incorporates ESD protection circuitry as well. There are several types
of ESD events as well as protection circuits. The following sections will discuss
ESD protection circuitry in general as well as present the specific type of ESD
protection measures taken in this design. The ESD reference guide by IBM [2]
was actively used during the integration of ESD measures in this design.
3.4.1 ESD event types
There are three types of ESD events, with corresponding models developed
for them:
1. Human Body Model (HBM)
2. Machine Model (MM)
3. Charged Device Model (CDM)
The HBM describes an event which occurs during electrostatic discharge
from a human body across two pins of the chip. The human body event is consid-
33
ered the longest event with the lowest current. The HBM is represented typically
by a 1.5 kΩ resistor in series with 100 pF capacitor which is charged to a specific
voltage. The other ends of the capacitor and resistor are connected to the device
under test which represents two pins of the chip through a switch. Once the switch
is closed and capacitor is charged, the current starts flowing through the device
under test, discharging the capacitor.
The MM describes an event which occurs during the electrostatic discharge
from a machine across two pins of the chip. The MM event is shorter than HBM
event with a higher level of current. The MM is represented by a 0.5 µH inductor
connected in series with the 200 pF capacitor. The other ends of the inductor
and capacitor are connected to the device under test through a switch. Once the
capacitor is charged and the switch is closed, the current starts flowing in and out
of the device under test in an oscillating way.
The CDM describes an event which occurs during the electrostatic dis-
charge of a charged module across a single pin of the chip. The CDM event is
considered the shortest ESD event with the highest current. A typical CDM test
is done by placing a charged field surface near the chip and shorting one of the
pins with a probe to ground. After a test the chip is inspected for any possible
damage.
3.4.2 ESD Protection Methods
There are two main ESD strategies, self protecting and non-self protecting.
The self protecting strategy assumes that ESD current flows through the I/O
circuit and the device within the I/O circuit can handle that current. A non-
self protecting strategy assumes that ESD current is not flowing through the I/O
circuit and an appropriate ESD device is added before the I/O circuit and does
not let the current flow through it. Our design utilizes the non-self protecting
34
strategy by placing the ESD protection device at the input and output pads of
the chip. The I/O pad voltage will not exceed the supply voltage during normal
operation and the main supply will be powered before any signal is applied to a
pad. The typical protection mechanism is shown in Fig. 3.11
Figure 3.11: ESD protection mechanizm
When a positive pulse occurs with respect to the supply pin, current travels
through the top diode and exits the supply pin. When a positive pulse occurs with
respect to the ground pin, current again travels through the top diode all the way
to the ground pin through the voltage clamp. Similarly, during a negative pulse
with respect to supply pin current flows through the supply pin all the way to the
I/O pin through the power clamp and bottom diode. During a negative pulse with
respect to the ground pin, the current flows from the ground pin to the I/O pin
through the bottom diode. This way the excess current during the ESD events
does not flow through the internal circuitry, thereby damaging it. The power
clamp is a special circuit designed in such a way that it starts conducting only
during an ESD event.
3.4.3 ESD cell
The standard ESD cell with four diodes is used in our design at each I/O
pad. The usage of two up and two down diodes allows it to handle voltages for
35
exceeding the power supply voltage. The schematic generated by the design kit
is shown on Fig. 3.12.
Figure 3.12: ESD cell used on every I/O pad
The design kit generates not only the schematic but also the appropriate
layout of the ESD cell. The INPUT node is connected to the I/O pad as well
as to the inputs of the internal circuitry. This ESD cell with diodes will provide
protection from HBM and MM ESD events. Usually two sets of such ESD cells
are used with an input series resistor in between them in order to provide pro-
tection from CDM event as well. Our design, however, does not utilize the CDM
protection.
3.4.4 Power Clamp
The power clamp consists of an RC network, inverter chain and large-sized
NFET transistor. During an ESD transient event, the RC circuit detects the
high current pulse and turns on the inverter chain. The last inverter turns on
36
the big NFET transistor which handles the ESD current. The power clamp was
configured for a standard time constant of 0.96 µs within the design kit. The time
constant controls the power clamp on-time during the ESD event. Configured and
automatically generated schematics are shown on Fig. 3.13. The kit generates
layout automatically as well. The power clamp is placed at every supply and
Figure 3.13: Power clamp
ground pad of the chip.
3.5 Simulation
This section presents simulation results for the ring oscillator with fixed
voltage, inverter delay, ring oscillator with variable voltage and digital buffer with
transmission line and package parasitic effects.
3.5.1 Simulation of inverter delay
The inverter delay was simulated using an input frequency of 1 GHz on a
unit sized inverter without load. The time difference between the two mid points
on the input and output signal has been taken as the delay. The plot of the
simulation is shown in Fig. 3.14. The difference between two mid points turns out
to be 12.88 ps .
37
Figure 3.14: Unit inverter delay
3.5.2 Simulation of Ring Oscillator with fixed 1.8V voltage
The 31 stage ring oscillator powered with 1.8V followed by a buffer without
a load was simulated using the normal process corner tt . A transient plot of the
simulation is shown in Fig. 3.15. The frequency of oscillation was measured as
750.5 MHz, which is relatively close to the frequency approximated from the
knowledge of the unit inverter delay in Eq. (3.2).
38
Figure 3.15: Transient simulation of 31 stage ring oscillator
3.5.3 Simulation of Ring Oscillator with variable voltage
The ring oscillator with variable supply voltage utilizes a voltage level
shifter in order to drive the digital buffer with signals of the proper voltage level.
The schematic of the simulation testbench is shown in Fig. 3.16. Signal vdd is
the fixed supply voltage of 1.8V and vdd2 is the variable voltage supply. The
inverter between the ring oscillator and voltage level shifter is added in order to
isolate the input of the ring oscillator from the higher capacitance represented by
the voltage level shifter.
Figure 3.16: Simulation testbench for ring oscillator with variable voltage supply
39
A voltage of 0.69V was picked as the supply voltage for the variable ring os-
cillator example transient simulation. The simulation result is shown in Fig. 3.17.
Figure 3.17: Simulation plot for the variable ring oscillator
It can be seen from the plot that the signal logic level of 0.69V at node
vb1 is converted to a standard logic level of 1.8V at the node vb2 by the voltage
level shifter before input to the digital buffer. The frequency calculated at the
output of the digital buffer is 106.7 MHz.
The simulation of the ring oscillator with variable supply ranging from
0.69V to 1.15V in voltage increments of 20 mV was performed under all process
corners. The frequencies computed for each voltage step and process corners tt,
ss, ff, sf, fs, ssf, fff are shown in Fig. 3.18.
40
0.6 0.7 0.8 0.9 1 1.1 1.2
50
100
150
200
250
300
350
400
450
500Plot of Frequency vs Voltage for Simulated ring oscillator
Ring oscillator voltage, V
Rin
g os
cilla
tor
freq
uenc
y, M
Hz
Simulated: ttSimulated: ssSimulated: ffSimulated: sfSimulated: fsSimulated: ssfSimulated: fff
Figure 3.18: Simulated output frequencies for variable supply ring oscillator
3.5.4 Simulation of Digital Buffer
The first simulation of digital buffer is a delay simulation. The buffer input
is connected to a signal source and the buffer output is connected to a capacitance
as shown in Fig. 3.19. The output capacitance is varied between 1 pF and 30 pF
in increments of 1 pF.
Figure 3.19: Testbench for buffer delay simulation
41
Simulation results of the input and output signals are shown in Fig. 3.20
Figure 3.20: Simulation plot of input and output signals for a digital buffer
The bigger the output capacitance the more is the deviation of the output
signal from a square shape. The delay of the buffer corresponding to each value of
parasitic output capacitance is measured using the mid-point principle. The time
difference is taken between mid-point of the input signal and mid-point of output
signals. The plot in Fig. 3.21 shows the measured delay for the digital buffer with
variable output parasitic capacitances connected.
We can observe that, the bigger is the parasitic output capacitance, the
bigger is the delay of the buffer. The frequency of the input signal was 1 GHz.
The next step is to simulate the effects of the pad parasitics, package parasitics
and the transmission line present at the output of the digital buffer. In order to
do that, the testbench with digital buffer, pad parasitic model, package parasitic
42
Figure 3.21: Simulated delays of the buffer for different values of parasitic outputcapacitance
model and ideal transmission line mode of the coaxial cable was constructed as
shown in Fig. 3.22.
The schematics of the testbench includes the pad entity, the ESD protection
cell used at the pad, the parasitic inductance and capacitance of the package,
resistance of the package pin, ideal transmission line of the coaxial cable 12”
length with a delay of 1.54 ns and 50 Ohm terminated load. Figs. 3.23, 3.24,
3.25 and 3.26 show the input and output waveforms at 250 MHz, 1 GHz, 2 GHz
and 3 GHz respectively.
We can notice here that there is no significant signal amplitude degradation
at 3 GHz compared to 250 MHz simulation using this relatively simple and close
to ideal testbench.
43
Figure 3.22: Testbench for digital buffer with transmission line and parasitics
44
Figure 3.23: Buffer simulation at 250 MHz
Figure 3.24: Buffer simulation at 1 GHz
45
Figure 3.25: Buffer simulation at 2 GHz
Figure 3.26: Buffer simulation at 3 GHz
46
3.6 Pad Frame
It is essential for any type of design to have a properly designed frame pad.
A pad frame basically consists of an outer level ground ring, pads, and internal
ground and supply rings. The total silicon area for the chip is 1.5 mm by 1.5 mm.
That is why all the design, including frame and pads, must fit within that area.
The pad frame floorplan is shown in Fig. 3.27.
47
Figure 3.27: Floorplan of the pad frame
48
A thin ground ring surrounds the whole design and goes along the chipedge
layer line, designating the absolute limits of the chip. Within an outer ground
ring the pads are distributed around in a counter-clockwise manner. Next to the
pads are the areas for ESD cell, Power Clamp and different types of buffers. The
designated area can hold either one power clamp, or ESD diodes and the standard
digital buffer designed for this chip. Next goes the thick supply ring implemented
with four metal layers, M1 through M4, densely interconnected with vias in order
to reduce the resistance of the supply line. Note that the small resistance on the
supply lines is also necessary for ESD events, in order to make the excess current
flow through them rather than internal circuitry. Next goes the ground ring also
implemented with four metal layers densely interconnected with vias.
Finally the remaining space which can be used for layout turns out to be a
little more than 1 mm by 1mm. This is considered a lot for a 180 nm process. Note
that we also have three corners with area of about 200 µm by 200 µm available
for design. One of the corners is occupied with a logo.
The designed pad frame together with ESD protection measures will be
used for all other chips in this process.
49
3.7 Test PCB Design
The chip will be evaluated at a high speeds. That is why it is crucial to
design an appropriate test board for the chip in order to provide minimum loss
interconnection from the chip pins to the test SMA connectors. That requires
matching the impedance of the PCB traces to an impedance of the test system
and measurement equipment, which in our case is 50 Ohms. The test PCB also
contains an on-board power supply with fixed 1.8V voltage as well as a variable
power supply for the variable voltage ring oscillators. The Cadence Allegro PCB
design package was used to enter the design schematics and lay out the PCB.
3.7.1 Test PCB Schematics
The figures Figs. 3.28, 3.29, 3.30 and 3.31 show the schematics of the
test board.
The schematic contains jumpers in order to have the opportunity to turn
on specific ring oscillators and power supplies. All the outputs are connected to
straight through-hole SMA connectors. Power supply decoupling arrays are used
on each power rail in order to decouple high speed noise. Two LDO regulators
from Linear Technology are used. One is U3 which is configured to supply constant
1.8V and another, U2, which can be configured with variable resistors R13 and
R15 to supply variable voltage for variable ring oscillators on chip.
50
Figure 3.28: Schematics of the Digital Test Chip PCB
51
Figure 3.29: Schematics of the Digital Test Chip PCB
52
Figure 3.30: Schematics of the Digital Test Chip PCB
53
Figure 3.31: Schematics of the Digital Test Chip PCB
54
3.7.2 Test PCB Layout
The PCB layout was done on a 4 layer FR408 board with dielectric per-
mittivity of 3.66. The board stackup is shown in Table 3.5. The main rules for
the PCB process used are 5 mil trace/space, 10 mil minimum drill diameter and
4 mil minimum annular ring around the drill hole.
Table 3.5: Digital Test Chip PCB Layers stackup
Layer Thickness, mil
Top copper 1.37
Prepreg 6.7
Internal copper 1 0.69
Core 47
Internal copper 2 0.69
Prepreg 6.7
Bottom copper 1.37
The Internal copper 1 layer was used as a ground plane and the Inter-
nal copper 2 layer was used as a power plane. Given the top copper tickness,
the thickness of prepreg (a fiberglass impregnated with resin), the dielectric per-
mittivity of the board and the fact that the Internal copper 1 is a ground, the
trace on top of the board must be 12 mils wide in order to achieve a characteristic
impedance of 50 Ohms.
The soldermask layer, drills, silkscreen and top metal layer of the board
are shown on Fig. 3.32. The signal traces are made of equal length for each side
of the chip with an initial plan to have equal delays, but it was not necessary.
55
The internal layer 1 which is a ground is shown on Fig. 3.33. The internal layer 2
Figure 3.32: Digital Test Chip top layer
which is a main power plane is shown on Fig. 3.34. The soldermask layer, drills,
silkscreen and bottom metal layer of the board are shown on Fig. 3.35.
The photo of the complete and assembled board with a Digital Test Chip
is shown on Fig. 3.36.
56
Figure 3.33: Digital Test Chip internal layer 1
57
Figure 3.34: Digital Test Chip internal layer 2
58
Figure 3.35: Digital Test Chip bottom layer
59
Figure 3.36: Digital Test Chip test board photo
60
3.8 Experimental results
This section presents the experimental results of the measurements using
different scopes and a spectrum analyzer.
3.8.1 Measurements of Variable 31-Stage Ring Oscillator
The measurements of the ring oscillator with variable voltage supply was
performed using an HP54510A oscilloscope with 250 MHz bandwidth limit. A
total 24 measurements have been conducted with variable supply ranging from
0.69V to 1.15V which produced output frequencies from 54.35 MHz up to 256.41
MHz. Table 3.6 gives the measured frequency and amplitude of the variable supply
ring oscillator.
Table 3.6: Measurement results of Variable Ring Oscillator
# Supply Voltage, V Frequency, MHz Amplitude, Vpp
1 0.69 54.35 1.43
2 0.71 61.73 1.43
3 0.73 68.49 1.43
4 0.75 76.92 1.43
5 0.77 83.33 1.43
6 0.79 90.9 1.43
7 0.81 98.04 1.49
8 0.83 106.38 1.5
9 0.85 113.64 1.5
10 0.87 121.95 1.5
11 0.89 128.2 1.5
12 0.91 138.89 1.5
Continued on next page
61
Table 3.6 – continued from previous page
# Supply Voltage, V Frequency, MHz Amplitude, Vpp
13 0.93 144.93 1.5
14 0.95 156.25 1.43
15 0.97 166.67 1.3
16 0.99 175.44 1.3
17 1.01 185.19 1.24
18 1.03 196.08 1.13
19 1.05 204.08 1.05
20 1.07 212.77 1.02
21 1.09 222.22 0.93
22 1.11 232.56 0.83
23 1.13 243.9 0.8
24 1.15 256.41 0.8
Oscilloscope snapshots for measurements number 1, 6, 13 and 24 are shown
in Figs. 3.37, 3.38, 3.39 and 3.40. We can observe here that the amplitude does
not necessarily decrease with increasing frequency, however, the output signal
amplitude at 1.15V supply voltage is roughly 800 mV. We also note that at 1.15V
we are getting a 256 MHz output signal which is already a bit outside of the
bandwidth of the scope. The closer the measured signal approaches the bandwidth
of the scope, the weaker it becomes.
Fig. 3.41 shows a plot of the simulated output frequency versus the mea-
sured one. We note that the measurement results show lower output frequency at
62
Figure 3.37: Measurement for 0.69V supply
Figure 3.38: Measurement for 0.79V supply
63
Figure 3.39: Measurement for 0.93V supply
Figure 3.40: Measurement for 1.15V supply
64
0.6 0.7 0.8 0.9 1 1.1 1.2
50
100
150
200
250
300
350
400
450
500Plot of Frequency vs Voltage for Simulated and Measured ring oscillator
Ring oscillator voltage, V
Rin
g os
cilla
tor
freq
uenc
y, M
Hz
MeasuredSimulated: ttSimulated: ssSimulated: ffSimulated: sfSimulated: fsSimulated: ssfSimulated: fff
Figure 3.41: Simulated vs measured output frequencies for variable supply ringoscillator
the given voltage than the shematics simulation results with the slowest corner.
From Fig. 3.41 we also note that at lower supply voltage the measurement re-
sults and the schematics simulation results with the slowest corner agree, but the
disagreement between those results get bigger once the supply voltage is increased.
65
3.8.2 Measurements of Fixed 1.8V 31-Stage Ring Oscillator
Fixed oscillators in the design powered with 1.8V voltage were measured
using the LecRoy 9384L scope, as well as with the E4403B spectrum analyzer.
In order to make sure that the frequency measurements of the ring oscillator are
reasonable we first applied artificially generated signal from the E4432B signal
generator to the scope and spectrum analyzer using the same RF coaxial cables. A
404 MHz signal was generated and measured on the scope and spectrum analyzer
(this specific frequency was selected because the actual measured frequency of
the ring oscillator was 404 MHz). The scope measurement snapshot is shown in
Fig. 3.42 and the spectrum analyzer measurement snapshot is shown in Fig. 3.43.
Figure 3.42: Scope snapshot of 404 MHz signal from signal generator
66
Figure 3.43: Spectrum analyzer snapshot of 404 MHz signal from signal generator
We can observe the 1.344Vpp signal on the scope snapshot as well as its
spectrum at 404 MHz on the spectrum analyzer. The signal power on the spectrum
analyzer shows about 7.9 dBm for the main signal and -33.8 dBm for its second
harmonic. We can use Eq. (3.10) in order to figure out the signal power in dBm
from the knowledge of VRMS of the signal and system impedance:
dBm = 10× log10
(V rms2
10−3 × 50
)(3.10)
Where 50 is the system impedance of 50 Ohms, and Vrms is the root-mean-
square voltage of the signal. In our case Vrms of the generated signal is 1.344V
divided by 2√
2 which turns out to be 0.4752V. Using Eq. (3.10), our signal power
should be around 6.55 dBm which is less than the measured value by 1.35 dB.
There are many factors coming into play when dealing with high speed signals
transferred over relatively long cables. The magnitude which we measure on a
scope is approximate, and might change a little from time to time. Also, the
67
system impedance is not strictly 50 Ohm due to the mismatches. All these and
other factors lead to the deviation of measured results from one piece of equipment
to another.
Now that the measurement method is established, we can measure the
fixed 1.8V voltage ring oscillator frequency. Note that when we measured the
frequency of the signal generator, the sinusoidal signal was centered at 0V. In the
case of a ring oscillator on the digital test chip, the signal ideally should oscillate
between 0V and 1.8V. Fig. 3.44 shows the frequency measurement on the scope.
Fig. 3.45 shows the amplitude measurement on the scope. And Fig. 3.46 shows
the frequency spectrum measurement on the spectrum analyzer.
Figure 3.44: Frequency measurement of ring oscillator using scope
Substituting the results of the amplitude measurement into Eq. (3.10), we
see that the signal power measured in Fig. 3.46 makes sense.
68
Figure 3.45: Amplitude measurement of ring oscillator using scope
3.8.3 Measurement of the Digital Output Buffer Performance
The digital test chip has buffers on some pads where with both of its inputs
and outputs are connected to neighboring pads and chip pins. This was done in
order to be able to drive those buffers externally with an input signal and observe
an output signal of the same frequency on another pin. This allows us to increase
the frequency of an input signal coming from the signal generator and test the
maximum speed capability of our chip and test setup.
The test PCB was modified and at the pin corresponding to the buffer
input a DC blocking capacitor and parallel combination of 1 MOhm resistors
were added. This was done because the signal generator used in the current test
provides a sinusoidal signal which is centered around 0V and that is unacceptable
for our chip because we would have to drive its IO pad with negative voltage. We
had to shift the input sinusoid so that its minimum amplitude peak is at 0V. The
69
Figure 3.46: Frequency measurement of ring oscillator using spectrum analyzer
DC blocking capacitor provides the DC blocking of the incoming signal and the
two resistors are connected so that one of their ends connects to an input pad and
another end connects to the on-board 1.8V vdd supply and the common ground.
This way, we are centering the input signal at 0.9V.
Figs. 3.47, 3.48, 3.49, 3.50, 3.51 and 3.52 show the output power
spectrum measurement on spectrum analyzer for the frequencies of 500 MHz, 1
GHz, 1.5 GHz, 2 GHz, 2.5 GHz and 2.7 GHz respectively.
70
Figure 3.47: Spectrum power measurement of buffer output at 500 MHz
Figure 3.48: Spectrum power measurement of buffer output at 1 GHz
At each snapshot we can observe both the input signal frequency and its
second harmonic. The signal power stays at fairly acceptable levels of almost 9
dBm for a frequency of up to 2.5 GHz. Starting at 2.7 GHz the signal power drops
71
Figure 3.49: Spectrum power measurement of buffer output at 1.5 GHz
Figure 3.50: Spectrum power measurement of buffer output at 2 GHz
to less than 4 dBm, the noise spectrum rises and additional spurs appear. We
can say that up to 2.5 GHz this buffer is most likely capable of driving the digital
input of another chip. There was no way to look at the time domain waveforms
72
Figure 3.51: Spectrum power measurement of buffer output at 2.5 GHz
Figure 3.52: Spectrum power measurement of buffer output at 2.7 GHz
at such frequencies due to the absence of a high speed scope with a bandwidth
exceeding 2.5 GHz.
73
3.9 Conclusions
The work related to the Digital Test Chip project was conducted in order
to test drive the IBM 180 nm process 7RF technology and prepare a proper de-
sign template which could be used to design more advanced chips such as high
frequency PLLs, LNAs and other digital, analog or mixed-signal chips. The pad
frame, ESD subcircuits, modular internal ground and power rings were customized
in such a way that it is easy to remake them for another type of design within
a short amount of time. The specific design challenge was the fact that the
CMRF7SF Kit is a realistic kit used in industry with realistic and sophisticated
design rules, completely different from design kits aimed for the educational pur-
poses like NCSU. This complexity, added a huge amount of additional issues.
The device models, supply voltage levels, design rules and layer definitions were
thoroughly studied during the whole process of the test chip design. A lot of non-
trivial issues have been resolved related to both the design kit and its integration
with CAD tools.
Another big challenge were the high speed elements present in the design. It
is far more difficult to test something what works above GHz frequencies. Careful
steps have to be taken not only during the measurement but also during the design
of the chip as well as the test PCB for it, since any errors could lead to failed
design or wrong test results. In the end,a working chip with important test circuits
has been successfully submitted for manufacturing and tested in the lab facilities.
The achieved speed of the digital buffer measurement of 2.5 GHz indicates that
the buffer can be used in many other designs requiring digital output at such high
speeds and that a binary data rate of 5 Gbps is possible in differential mode. In
fact, in the case when the digital output will have to be provided to another digital
chip on a the same PCB, the limit of operation might be even more than 2.5 GHz
74
due to the fact that there is no need for SMA connectors and coaxial cables with
big capacitances. The current design was a success.
75
3.10 Micrographs
76
Chapter 4
1.2 GHz Fixed Frequency Multiplying DPLL
This chapter presents the design and implementation of a digital phase locked
loop circuit. The PLL is a widely used component in a variety of analog and
digital systems. It is used for clock recovery in high-speed data communication
channels, LO frequency generation for mixers in RF systems, clocks generation
in digital systems such as DSP chips and microcontrollers. Every application
has specific constraints for the PLL and in most cases it has to be designed and
optimized appropriately in order to achieve best performance. There are different
types of PLLs, Digital PLL or DPLL which is basically an analog PLL with a
digital divider and phase-frequency detector, Analog PLL or APLL with analog
phase detector, All Digital PLL or ADPLL where most of the components such
as phase detector, divider, loop filter and oscillator are digital or at least digitally
controlled. In our case we designed the fixed frequency clock multiplying DPLL,
with digital phase detector, divider, analog charge pump, analog passive loop
filter and current-starved VCO. The input frequency is 200 MHz and the output
frequency is 1.2 GHz.
4.1 System Description
The phase locked loop system produces an output frequency based on the
input frequency. It can be considered as a linear dynamical system once it is
locked. The system is comprised of phase detector, loop filter, oscillator and di-
vider. The phase detector detects the phase error between the input frequency
77
and divided output frequency, the loop filter corrects the voltage fed to the os-
cillator based on the error amount coming from the phase detector. The divider
divides the output frequency before feeding it to the phase detector for compar-
ison against the input frequency. The oscillator generates the output frequency
according to the control voltage corrected by the loop filter. The block diagram
of the implemented DPLL system is shown in Fig. 4.1. Further discussion and
PFD CHARGE PUMP
UP
DNLF VCO
CLOCKBUFFER
DIVIDE BY 6
Fosc 1.2 GHz
200 MHz
Figure 4.1: Block diagram of DPLL
development of the DPLL is based mostly on the design techniques described by
Harris [1].
4.2 PFD Operation and Design
One of the key functions of the DPLL is to be able to detect the phase
difference between the input frequency and the divided output frequency. This
task can be accomplished using the Phase Detector (PD) or Phase-Frequency
Detector (PFD). The Phase Detector can be implemented as a simple XOR gate.
However, the XOR PD detector is sensitive to input duty cycle variation which
can lead to a locking with phase error and it also alternates the sign every 180.
That is why the decision was made to use the flip-flop based phase detector.
The schematics is shown in Fig. 4.2. It consists of typical latched flip-flops with
asynchronous active low reset, inverters and a symmetric NAND2 gate. The
78
Figure 4.2: Schematics of the Phase Frequency Detector
operation of this PFD is as follows: assume the initial state of both flip-flops is 0. If
the reference clock is leading in phase, the UP signal will be 1 because the reference
clock edge appears first on the top flip-flop. When the clock edge of the feedback
clock appears later on the bottom flip-flop DN becomes 1. At that moment the
symmetric NAND2 gate will produce output 0, which will asynchronously reset
both flip-flops and force outputs UP and DN to 0. This way the duration of UP
signal being 1 will indicate the amount of time by which reference clock is leading.
A similar scenario occurs with the DN signal in case the feedback clock is leading
in phase. When both clocks are in phase, the UP and DN signals will be a short
79
pulse peaks appearing at the same time. The inverters are added in order to not
reset flip-flops too fast, rather than do it once their output becomes logic 1.
The NAND2 gate has to be fast and with equal rising and falling edges.
Thus its inputs a and b must have the same parasitic capacitance. The schematics
is shown in Fig. 4.3. In case the frequency of operation is high, the layout of this
Figure 4.3: Schematics of the symmetric NAND2 gate
gate has to be done in such a way that both inputs of the gate experience the
same additive parasitic capacitance from the interconnect metals.
The duration of UP and DN signals controls the operation of the Charge
Pump which produces the current proportional to them. When the PLL is locked
the combined transfer function of PFD and Charge Pump together will be
Ipd(s)
Φe(s)=Icp2π
= Kpd (4.1)
80
where Icp is the current of the charge pump, Kpd is the proportional gain of the
control system, Φe(s) is the phase error between the reference and feedback clocks
and Ipd(s) is the current which has to be produced according to the output of the
PFD.
4.3 Charge Pump
The charge pump is used to convert the UP and DN signals produced by
the PFD into current which is filtered and converted to voltage by the loop filter
in order to control the VCO. The basic implementation of the charge pump is
shown in Fig. 4.4. When the UP signal is high TP9 is on and conducts the
Figure 4.4: Schematics of a basic charge pump
current through TP7 down to node ipd . When the DN signal is high TN2 is
on and conducts the current from ipd down to TN5 . This way the ipd node
connected to the loop filter is being charged and discharged according to the UP
and DN signals produced by the PFD. The main issue with the implementation
shown in Fig. 4.4 is the charge sharing from the switch transistors effecting the
81
ipd node voltage. If the TP9 is turned off after being initially on the gate oxide
charge is injected both to the source and drain, and part of the charge injected
to the drain effects the voltage at the ipd node. The voltage at the ipd node is
also effected by the capacitive feedthrough of the UP signal due to the capacitive
voltage division between gate-drain and ipd node capacitances. Similar effects
are present during the operation of the TN2 switch and TN5 mirror transistor.
In order to overcome that issue another implementation was used as shown
in Fig. 4.5, [3]. In this implementation the mirror with floating current source has
Figure 4.5: Schematics of a charge pump with floating current source
been used. The switch transistors TP5 and TN5 are now connected to the node
ipd through the mirror transistors TP7 and TN2 . This way the effects of the
charge sharing are significantly minimized. If the UP signal is high, and the TP5
transistor is on, the drain and source of the TP7 have about the same voltage.
The sudden voltage change of the ipd node during transition of UP or DN signals
is minimized. The enabled transmission gate at DN signal input equalizes the
delay caused by the UP inverter.
82
The charge pump needs to be designed for a specific current Icp which
depends on the natural frequency of the DPLL, primary capacitance of the loop
filter and the input frequency division factor as shown below
wn =
√Icp ×Kvco
Ndiv × C(4.2)
In order to get the Icp value the natural frequency of DPLL wn has to be
known. As a rule of thumb we choose wn to be about 50 times smaller than input
frequency win which is 2π × 200MHz rad/s as shown below
wn =win50
=2π × 200MHz
50= 25.13MHz (4.3)
Rearranging (4.2) and knowing that our Kvco parameter is 1.51 GHz (determined
during the simulation of the VCO), the primary capacitance is 10 pF, and input
frequency division factor Ndiv is 6 we have
Icp =w2n ×Ndiv × C
Kvco
=(25.13MHz)2 × 6× 10pF
1.51GHz= 25.09µA (4.4)
Once the required current is known we can solve for the resistance value of RPC0
as in
RPC0 =V dd− V tn
Icp=
1.8− 0.45
25.09µA= 53.8kΩ (4.5)
Where Vtn is the NMOS threshold voltage. The final value for RPC0 after
performing simulation and tweaking was selected to be 54.48 kΩ.
4.4 Loop Filter
The loop filter is one of the key elements of the DPLL which directly affects
its ability to phase lock with minimum error. From a control systems perspective
our error correction system is a PI controller and the transfer function representing
83
the loop filter can be shown to be a simple RC filter.
V ctrl(s)
Ipd(s)=
1
s× C+R (4.6)
The integral term of Eq. (4.6) settles to zero once the phase difference between the
divided output clock and reference input clock becomes zero. The schematics of
the loop filter used is shown in Fig. 4.6. The PMOS transistor is used to precharge
Figure 4.6: Schematics of the RC loop filter
the voltage at the control node to vdd during a reset event, its width is 3.2 µm
and length is 0.18 µm.
The closed-loop transfer function of our DPLL is
H(s) =∆Φo(s)
∆ΦI(s)=
Kpd×(R + 1
s×C
)×(2π×Kvco
s
)1 +
(KpdNdiv
)×(R + 1
s×C
)×(2π×Kvco
s
) (4.7)
where ∆Φo(s) and ∆ΦI(s) are the output and input clock phases. Eq. (4.7) can
be rewritten in terms of the natural frequency wn and damping factor ξ as shown
84
in Eq. (4.8).
H(s) = N × 2× ξ × wn × s+ w2n
s2 + 2× ξ × wn × s+ w2n
(4.8)
Choosing the damping factor ξ to be 1 for critical damping, the main capacitor
C to be 10 pF, knowing our natural frequency wn and using (4.9)
ξ =wn ×R× C
2(4.9)
we calculate R to be 7.96 kΩ. After some tweaking during simulation, the final
value selected was 8.05 kΩ. The capacitor C2 was chosen to be 1 pF in order to
smooth out the ripple on the control voltage node of the filter caused by the PFD.
However, care should be taken so that the total capacitance on the control voltage
node together with parasitic capacitance of the VCO does not get too high, or it
might destabilize the control loop.
4.5 Voltage Controlled Oscillator
There are many types of oscillators which can be used in a PLL, current
controlled oscillators, digitally-controlled oscillators and voltage-controlled oscil-
lators. In our case we are using the current-starved voltage controlled oscillator.
The core components of the VCO are five inverters with a controlled voltage sup-
ply. The schematics of the VCO is shown in Fig. 4.7. The control voltage is
applied to the gate of TN22 and the current is mirrored to every stage powering
the individual inverter. The last inverter isolates the five inverters from the out-
put capacitance and acts as a buffer. The relation between the VCO current ID
and the oscillation frequency is given by
fOSC =ID
NV CO × Cnode × V dd(4.10)
85
Figure 4.7: Schematics of the current-starved Voltage Controlled Oscillator
where NV CO is the number of stages which is five, Cnode is the capacitance at each
node, which is approximately 6 fF and ID is the current in the current mirror.
Using this information, ID from (4.10) equals to 64.8 µA. The control voltage
Vctrl can be approximated as
V ctrl =V dd+ V tn
2=
1.8 + 0.45
2= 1.125V (4.11)
Knowing the control voltage and required current for a given frequency we can
calculate the value of the RPC0 resistor as
RPC0 =V ctrl − V tn
ID=
1.125− 0.45
64.8µA= 10.4kΩ (4.12)
Transistor sizes are shown in Table 4.1.
86
Table 4.1: Transistor sizes for the VCO
Width, µm Length, µm
TP1,18,13,14,15,16,17 3.2 0.36
TP0,9,10,11,12 1.6 0.18
TN22 0.4 0.18
TN0,11,12,13,14 0.8 0.18
TN1,15,16,17,18,19 1.6 0.36
4.6 Divider Unit
Since we are generating a 1.2 GHz frequency from input 200 MHz frequency
we need to divide the output 1.2 GHz clock by 6 before feeding the result to the
PFD for phase comparison. The divider is fully digital and realized as shown in
Fig. 4.8.
Figure 4.8: Schematics of the divide-by-6 unit
4.7 Clock Buffer
The design of the clock buffer which is used in the current DPLL is de-
scribed in Chapter 3.2.
87
4.8 Simulation
This section presents the simulation results of different blocks of the DPLL.
After the simulation of specific blocks some design parameters have been changed
in order to optimize and improve the design.
4.8.1 Simulation of the PFD and Charge Pump
The testbench with PFD and Charge Pump was constructed, which also in-
cluded two clock sources and a reset signal source. The schematics of the testbench
is shown in Fig. 4.9. The capacitor C0 is supposed to have a large capacitance
Figure 4.9: Schematics of PFD and Charge Pump testbench
value present at that node, however; it was reduced down to 500 fF in order to
speed up the simulation time.
First the reset transistor was disconnected, and the clock clkb was set to
be delayed by 1.5 ns. The charging of the output capacitor in a stairway fashion
up to vdd can be observed from the plot in Fig. 4.10. The UP signal is much
wider than the DN signal.
Next we connect back the reset transistor to node vc and set the clka to
have a delay of 1.5 ns. The result is shown in Fig. 4.11. After the reset event, node
88
Figure 4.10: PFD simulation with clkb clock lagging by 1.5 ns
Figure 4.11: PFD simulation with clka clock lagging by 1.5 ns
vc starts discharging because the DN pulse is now wider and constantly turns on
the bottom switch in the PFD.
Next we eliminate the delays from both clocks and make them perfectly
aligned in phase. The result of the simulation is shown in Fig. 4.12. We can notice
that both UP and DN signals are now aligned and represent a short impulses,
Fig. 4.13 shows the zoomed plot. The UP and DN signals have almost equal
89
Figure 4.12: PFD simulation with clka and clkb clocks perfectly aligned
Figure 4.13: PFD simulation with clka and clkb clocks perfectly aligned, zoomed
width, the DN pulse is 224.6 ps wide and the UP pulse is 222.8 ps wide. The
voltage at vc node settles down to 1.6V.
90
4.8.2 Simulation of VCO
First the Kvco parameter simulation was performed on a VCO. The input
voltage to the VCO was varied from 0.65V to 1.8V. The result is shown in Fig. 4.14.
Next in order to approximate the Kvco parameter we need to take two points
Figure 4.14: Kvco simulation plot for VCO
around the frequency of interest and compute the slope. The +/- 10 MHz points
around 1.2 GHz frequency were selected. The zoomed plot is shown in Fig. 4.15.
From the cursor values with voltage and frequency, Kvco can be computed as
Kvco =1.21GHz − 1.19GHz
1.142724− 1.129496= 1.51GHz/V (4.13)
Next the VCO was simulated for Phase Noise. In order to simulate Phase
Noise, the PSS analysis (Periodic Steady-State) analysis also must be setup. The
PSS analysis was set up with the following options: beat frequency of 1.2 GHz,
Moderate Accuracy and stabilization time of 5 ns. The Phase Noise simulation was
set up with the following options: start-stop range of 1kHz to 100MHz, Maximum
Sideband of 15, and relative harmonic count of 1. The control voltage of the VCO
91
Figure 4.15: Kvco simulation plot for VCO, zoomed
was set to 1.1357V. The result of the Phase Noise simulation is shown in Fig. 4.16.
The first thing to note is relatively high phase noise of about 11 dBc/Hz at an
Figure 4.16: Phase Noise simulation of the VCO
offset frequency of 1 KHz. At 1MHz the offset phase noise drops down to -50
dBc/Hz. On the other hand, VCOs implemented with ring oscillators are known
to have a poor phase noise performance, [4]. Another quick test was performed
92
in order to identify the noise reason, an ideal 100 pF capacitor was added at the
node where the gates of TP1 and TP18 transistors connect in Fig. 4.7 and the
phase noise starting at the offset frequency of 1 kHz reduced down to around 0
dBc/Hz. Further increase of the capacitance value did not improve the phase
noise performance more. It is obvious that adding such a huge capacitor is not
a practical way of reducing the phase noise, so for an application requiring much
lower phase noise or time jitter another type of VCO has to be used. On another
side, we should note that the phase noise simulated in Spectre (MMSIM) using
the model libraries for the design kit gives sometimes only a rough approximate
values.
4.8.3 Simulation of the complete DPLL
The final testbench for transient simulation was constructed as shown in
Fig. 4.17. The testbench consists of assembled DPLL blocks, digital buffer, input
Figure 4.17: Testbench of DPLL
clock and reset sources, output capacitance of 15 pF and voltage supply. The first
100 ns of simulation plot is shown in Fig. 4.18. We can observe a high width of
UP pulses and the decay of the vctrl node after reset has been released. The next
93
Figure 4.18: Simulation plot for 100 ns
94
plot shows the last 24 ns of simulation in Fig. 4.19. We notice that clk in and
clk fb clocks are almost perfectly aligned in phase. The UP and DN signals take
the form of a short pulses occuring at the same time when the DPLL is in lock.
The vctrl control voltage settles down to about 1.135V. The clk out signal has
relatively sharp edges and almost a 50% duty cycle.
95
Figure 4.19: Simulation plot for last 24 ns
96
4.9 Test PCB Design
This section presents the test PCB design for the DPLL project. The PCB
manufacturing process used was similar to the one described in Chapter 3.7.
4.9.1 Test PCB Schematics
Figs. 4.20 and 4.21 show the schematics of the test PCB for the DPLL chip.
The connectors relevant to the DPLL implemented on a chip are SMA connectors
J8 and J7 . Since the input clock is to be generated by the signal generator
which provides going positive and negative going sinusoid, resistors R4,R5 and
the capacitor C9 are used to change the DC level of the sinusoidal signal such that
the voltage at the CLK IN pin does not go below 0V. Diode D1 and resistor
R1 are used to generate the reset signal for the DPLL. Decoupling capacitors
C1-C4 were selected with a resonating frequency of about 200 MHz in order to
decouple the input signal of 200MHz ringing to the supply line to ground. The
on-board LDO voltage regulator U2 from Linear Technology was used to generate
a precise 1.8V supply voltage for the DPLL chip. An extra pin was provided in
case a manual external voltage needed to be supplied to the DPLL supply lines.
97
Figure 4.20: Schematics of DPLL PCB testbench
98
Figure 4.21: Schematics of DPLL PCB testbench on-board power supply
99
4.9.2 Test PCB Layout
Figs. 4.22, 4.23, 4.24 and 4.25 show top, internal one, internal two and
bottom layers rogether with board edge, soldemask, silk screen and paste mask.
Figure 4.22: Testbench PCB, top layer
100
Figure 4.23: Testbench PCB, internal layer one
101
Figure 4.24: Testbench PCB, internal layer two
102
Figure 4.25: Testbench PCB, bottom layer
103
The photo of the finished and hand assembled PCB is shown in Fig. 4.26.
Figure 4.26: Photo of the finished PCB containing manufactured DPLL chip
104
4.10 Experimental Results
This section presents the experimental results of the DPLL. The experi-
mental procedure was done only using the E4403B Agilent spectrum analyzer since
there was no high-speed scope available in the lab environment with a bandwidth
of more than 1.2GHz which is the operating frequency of our DPLL.
4.10.1 General measurement
The first snapshot in Fig. 4.27 shows the measurement with 3MHz spec-
trum analyzer resolution it shows the whole span up to 3GHz. The first thing to
Figure 4.27: 3 GHz span snapshot from spectrum analyzer
observe is that a peak power of 7.1 dBm which looks pretty fair for most appli-
cations appears right at 1.2 GHz. The second harmonic of the main signal with
power level of -4 dBm appears at 2.4 GHz which, is twice the DPLL’s main fre-
quency. We also notice very small spurs appearing at a multiple of 200 MHz. At
105
this stage we can tell that the DPLL is working as it was supposed to. The power
consumption during the operation measures to be 18 mA. The voltage supply to
the chip was provided externally and was exactly 1.800V.
4.10.2 Phase Noise measurement
The next step is to measure the phase noise. Again due to the fact that
the lab did not have sophisticated phase noise measurement equipment, the same
spectrum analyzer was used to measure the single side band levels at specific
frequency offsets with the later conversion to dBc/Hz as shown in Nutune [5],
although there are several other ways to measure the phase noise.
The snapshot in Fig. 4.28 shows the measurement of signal power at an
offset of 1 kHz. The spectrum analyzer resolution was adjusted to 1 kHz as well.
Note that coarser the resolution of the spectrum analyzer is less precise than the
measurements. The first thing to do is to convert the single side band noise level
at a given offset frequency to a noise level within a 1 Hz bandwidth as shown in
L(noise/1Hz/SSB) = −1.8dBm− 10 log(1KHz) + 2.5 = −29.3dBm (4.14)
After that we can subtract the carrier level from the result to get the phase noise
in dBc/Hz as shown in
PhaseNoise = −29.3− 7dBm = −36.3dBc/Hz (4.15)
Figs. 4.29, 4.30, 4.31, 4.32 and 4.33 show the measured power levels at
offsets of 10 kHz, 100 kHz, 1 MHz, 10 MHz and 100 MHz from the carrier level.
106
Figure 4.28: Signal power at 1 KHz offset
107
Figure 4.29: Signal power at 10 kHz offset
Figure 4.30: Signal power at 100 kHz offset
108
Figure 4.31: Signal power at 1 MHz offset
109
Figure 4.32: Signal power at 10 MHz offset
110
Figure 4.33: Signal power at 100 MHz offset
111
Using (4.14) and (4.15) a table of phase noise values at different offset
frequencies has been obtained and is shown in Table 4.2.
Table 4.2: Phase Noise of DPLL at the offset frequencies
Offset Frequency Phase Noise, dBc/Hz
1 KHz -36
10 KHz -82.16
100 KHz -99.5
1 MHz -82.5
10 MHz -99.3
100 MHz -116.2
4.10.3 Time Jitter Approximation
The time jitter parameter is another important performance parameter of
any type of PLL or oscillator. It can be measured in a time domain using the
high-speed scope with enough bandwidth or it can also be approximated from the
phase noise measurement results as shown by Kester [6]. In order to get the time
jitter, the phase noise data has to be integrated with respect to the frequency
offset. The integrated phase noise power can be converted to RMS phase jitter in
radians using
RMS Phase Jitter =√
2× 10A/10 (rad) (4.16)
112
where A is an integrated phase noise jitter. The rms phase jitter in radians can
be converted to rms jitter in seconds using Eq. (4.17).
RMS Jitter =
√2× 10A/10
2π × fo(sec) (4.17)
where fo is the center frequency of the olscillator. There are many helper spread-
sheets and programs available which automate the process of time jitter calcu-
lation from phase noise data. One of them used in this case was a spreadsheet
from JitterTime.com. Using the phase noise data from Table 4.2 the rms jitter
was approximated to be 52.88 ps. Note that if we were to count 10 KHz as the
lowest frequency offset limit the rms time jitter would be approximated to be 18.8
ps which is considerably lower, however; the lower the starting frequency limit
the more precise is the rms jitter calculated. Given the fact that the spectrum
analyzer did provide at least 1 KHz resolution we can take the 1 KHz as the lowest
frequency offset limit and stick with the result of 52.88 ps of rms time jitter.
Given the fact that our DPLL was using a VCO with single ended ring
oscillators which are known to be very noisy, the overall phase noise measurement
and time jitter approximation results make sense.
4.11 Conclusion and Future Work
This project demonstrated the design and implementation of the DPLL
system on the 180 nm IBM 7RF technology process. The design started with the
prototype of the system, schematics entry, simulation, tweaking, layout and sub-
mission process to the manufacturing foundry with the subsequent testing upon
receival of the chip. Additional challenges were the manufacturing of the test-
bench PCB for a 1.2 GHz chip using a relatively cheap PCB process and a high
speed measurement using only limited hardware, specifically a 3 GHz spectrum
113
analyzer only. However, the overall design was successful, the chip was manufac-
tured and its operation was verified in lab. The relatively high phase noise and as
a result, high time jitter was expected for the DPLL employing athe single-ended
ring oscillator based VCO.
Future work will include a better charge pump design, different type of
VCO, either source coupled or LC tank based, and experimentation with various
types of loop filters, both active and passive. The overall project was a success.
114
Chapter 5
2 GHz Low Noise Amplifier
This chapter presents the design and development of the 2 GHz Low Noise Am-
plifier implemented with an NMOS transistors in a common-source configuration
for the IBM 7RF process. Theory of operation, design, simulation, measurement,
troubleshooting and further development is discussed as well.
5.1 Design
The LNA consists of the main amplifying transistor, cascode transistor and
a biasing transistor. The schematics is shown in Fig. 5.1. A similar design is also
described in Thomas [7] and Razavi [8]. The main amplifying transistor is TN2
which is biased by TN1 . The TN3 is the a diode-connected transistor. The
inductor Ls is used to control the input matching at the frequency of interest,
inductor Lg is used to cancel out the TN2 gate-source capacitive element of re-
actance, and inductor Lo is used as a supply choke and output matching element.
The resistor R1 is used to block the RF input from the biasing line. Capacitors
C0 and C1 performing a function of DC blocking and input/output matching.
Capacitor C3 is used for RF decoupling.
5.1.1 Theoretical Analysis
The model of the amplifier with TN2 and inductors at the gate and source
can be shown as in Fig. 5.2. Zin is the impedance looking into the input port,
Z ′in is the impedance looking into the gate of TN2 . The capacitor Cgs represents
the gate-source capacitance of TN2 . The analysis starts by writing the nodal
115
Figure 5.1: Schematics of the common-source LNA
Figure 5.2: Model of common-source LNA with inductive feedback
equation for node S as shown in below followed by further derivations.
(Vg − Vs)× s× Cgs + gm × (Vg − Vs) =Vs
s× Ls(5.1)
116
(Vg − Vs)× (s× Cgs + gm) =Vs
s× Ls(5.2)
Vg × (s× Cgs + gm) = Vs ×(s× Cgs + gm +
1
s× Ls
)(5.3)
VsVg
=s× Cgs + gm
s× Cgs + gm + 1s×Ls
(5.4)
From (5.2) we have:
Vg − Vs =Vs
s× Ls × (s× Cgs + gm)(5.5)
From (5.4) we have:
Vs =Vg × (s× Cgs + gm)
s× Cgs + gm + 1s×Ls
(5.6)
Substituting (5.6) into (5.5) we get:
Vg − Vs =Vg × (gm + s× Cgs)(
s× Cgs + gm + 1s×Ls
)× s× Ls × (s× Cgs + gm)
(5.7)
Vg − Vs =Vg(
s× Cgs + gm + 1s×Ls
)× s× Ls
(5.8)
The current Iin is:
Iin = (Vg − Vs)× s× Cgs (5.9)
Iin =Vg × s× Cgs(
s× Cgs + gm + 1s×Ls
)× s× Ls
=Vg ×
(Cgs
Ls
)s× Cgs + gm + 1
s×Ls
(5.10)
The impedance looking into the gate is therefore:
Z ′in =VgIin
=s× Cgs + gm + 1
s×Ls
Cgs
Ls
(5.11)
117
Z ′in = s× Ls +gm × LsCgs
+1
s× Cgs(5.12)
The second term of Eq. (5.12) is the real part of input impedance to the gate.
The natural frequency of interest can be represented as:
ω0 =1√
Cgs × L, f0 =
1√Cgs × L
× 1
2× π(5.13)
where L is the total inductance present at the gate and source:
L = Lg + Ls (5.14)
The tansition frequency is defined as:
ωT =gmCgs
(5.15)
Now using (5.15) and the second term of (5.12) we have:
Ls =Rin
ωT(5.16)
where Rin is the real input impedance to the amplifier. The total input impedance
looking into the amplifier is:
Zin = s× Lg + Z ′in (5.17)
While proceeding with the design and selection of the component values we keep
in mind that the amount of inductance we use on chip is limited. We first assume
118
that total inductance L cannot exceed 8nH and rewrite (5.13) as follows:
Cgs =1
ω20 × L
(5.18)
Knowing that our frequency of interest f0 is 2 GHz in (5.18) we get the value
of Cgs capacitance 791fF. We next obtain the total width of the main amplifying
transistor:
W =Cgs
Cgso + 23× Length× Cox
(5.19)
Knowing that our approximate values of Cgso and Cox are 0.745 fF/µm and 8.42
fF/µm2 respectively, the length of the transistor is 180nm, we get 450 µm as our
width of transistor from (5.19). The next step is to calculate gm of the transistor:
gm = µn × Cox ×(
W
Length
)× (Vgs − Vth) (5.20)
With the values of width and length of the transistor as well as other parameters
of the NMOS transistor for the current process, the value of gm is calculated to
be 117 mA/V. Next we calculate the current for the transistor:
IB =1
2× gm × (Vgs − Vth) (5.21)
Assuming Vgs−Vth to be 0.15V the current turns out to be 8.8mA. The next step
is to calculate the value of the Ls, the source inductor using (5.16). Assuming
ideal real impedance of 50 Ohm and the value of ωT calculated from Eq. (5.15)
we get 338 pH inductance for Ls. Knowing that we initially assumed 8nH as a
total inductance at the gate and source and utilizing (5.14) we get the value of
7.66nH for Lg.
119
Of course the value of the input resistance Rin is not going to be exactly 50
Ohm once the LNA is implemented on chip. There are many parasitic elements,
from the package pin, from the ESD cell at the pad, from the pad itself as well as
the interconnection and additional elements, such as biasing line and resistor R1
from the 5.1. That is why our next step is to put the schematics of the LNA into
a realistic testbench which accounts for most of the parasitics and other elements
in the design and start tweaking the initial values of the selected components, like
inductances and the width of the transistors in order to adjust the Cgs.
5.1.2 Practical Implementation
The LNA was placed in the testbench shown in Fig. 5.3. The testbench
includes a relatively simple model of package parasitics with lumped elements
Cpack , Rpack and Lpack which represent capacitance, resistance and induc-
tance of the package pin and bonding wire. The values are 416 fF, 56 MOhm and
1.37 nH, respectively. The initial values were taken from the provided datasheet
for similar packages. As a result, these values are just rough approximates of the
package and bonding wire parasitics. The testbench also includes the model of
Figure 5.3: Testbench for the LNA
the PAD used in the layout and the model of the ESD cell used with the PAD
for each IO pin. The current testbench does not account for losses from the lossy
120
transmission line of test cables and PCB traces. Two RF ports are put at the
beginning and the end of the whole chain. The LNA under test is in the center
with the biasing resistor Rb connected to the node va .
After several simulation runs, the width of the main amplifying transistor
was selected to be 277.2 µm. It is quite different from the initially calculated
width of 450 µm. The new size was adjusted until the dip on S11 parameter
occured at 2 GHz.
The next step was to improve the amplifier by adding a second stage. The
schematics is shown in Fig. 5.4. Here TN4 , TN2 , TN3 and TN5 have same
Figure 5.4: Two stage LNA
width of 277.2 µm and all of them have a length of 180 nm. The biasing transistor
also has length of 180 nm but twice smaller width. Capacitor C1 is used to pass
the signal to the second stage without the DC component. Resistor R2 is used
as a biasing line blocker just like R1 . Resistor RPC2 is used as feedback on
the second stage in order to improve the S22 parameter at the price of reduced
121
forward gain. The values of inductors Lg , Ls and Lo were 7.323 nH, 500 pH and
11.2 nH, respectively. Inductors Lg2 , Ls2 and Lo2 had similar values as the
ones in the first stage.
5.2 Simulation
The bias current was adjusted to 8.5mA. The current flowing through the
first stage was 16.4 mA and the current flowing through the second stage was 20.4
mA. The vdd voltage was 1.8V. The S11, S21, S12 and S22 parameters are shown
in Figs. 5.5, 5.6, 5.7, and 5.8, respectively.
Figure 5.5: Simulated S11
122
Figure 5.6: Simulated S21
Figure 5.7: Simulated S12
123
Figure 5.8: Simulated S22
Figure 5.9: Simulated S22, without feedback resistor at the second stage
124
As it was mentioned before, resistor RPC2 improves the S22 parameter,
or the output matching. The S22 parameter simulation without RPC2 resistor
in place in the schematics of Fig. 5.4 is shown in Fig. 5.9.
The Noise Figure simulation plot is shown in Fig. 5.10. It can be seen
Figure 5.10: Simulated Noise Figure
that the Noise Figure at the center frequency of interest is around 2.55dB. The
input referred 1dB compression plot is shown in Fig. 5.11 and from the simulation
result, it turns out to be -19.5 dB.
125
Figure 5.11: Input referred 1dB compression plot
126
5.3 Test PCB Design
This section presents the test PCB design for the LNA including both the
schematics of the PCB and layout. The PCB manufacturing process used was
similar to the one described in Chapter 3.7.
5.3.1 Test PCB Schematics
The test PCB schematics are shown in Fig. 5.12. Fig. 5.13 shows the
schematics of the on-board LDO for 1.8V output for the LNA. The SMA connec-
tors J3 and J4 are for RF input and output. Resistor R1 sets the bias current
and resistor R10 is for setting the maximum current limit. Capacitors C1 and
C2 provide decoupling at the bias line.
127
Figure 5.12: LNA1 test PCB, chip under test
128
Figure 5.13: LNA1 test PCB, on-board power supply
129
5.3.2 Test PCB Layout
The pictures of layout top layer, first internal layer (common ground),
second internal layer (power) and the bottom are shown in Figs. 5.14, 5.15, 5.16
and 5.17, respectively.
Figure 5.14: PCB Layout, Top layer
Figure 5.15: PCB Layout, First internal layer, Ground
130
Figure 5.16: PCB Layout, Second internal layer, Power
Figure 5.17: PCB Layout, Bottom layer
131
The photo of the manufactured and hand assembled PCB is shown in
Fig. 5.18.
Figure 5.18: Photo of the manufactured and assembled PCB for LNA
132
5.4 Experimental Results
This section presents the experimental results, investigation and trou-
bleshooting of the manufactured LNA.
5.4.1 Measurement Results
The first thing which was done before measuring the AC parameters of the
LNA is checking the DC parameters and operating currents both in the biasing
branch and the main power supply rail. A voltage of 1.8V voltage was provided to
the vdd power rail of the LNA and the current in the biasing branch was adjusted
to 8.5 mA with the on-board variable resistor. The current consumption on the
power supply rail observed to be around 16 mA, which is significantly lower than
the simulated value 36 mA. Obviously, we see a big difference in the DC operating
conditions of the LNA.
In order to investigate the DC behavior of the circuit given different inputs
at the bias branch and power supply rail, a series of measurements was performed
with different supply voltages and biasing currents. Two types of voltage supply
values were used 1.8V and 3.6V. It is important to note that this is a 1.8V process.
Using voltages exceeding the manufacturer’s limits is highly discouraged for the
designs which are supposed to be produced in series, however; given the fact that
in our case it is an experiment and also the fact that our LNA consists of stacked
transistors and Vgs of each transistor does not exceed 2V, we can perform these
tests. Shown below is a measurement set with four variations.
1. vdd = 1.8V, IB = 8.5 mA, IDC,measured = 16 mA
2. vdd = 1.8V, IB = 17 mA, IDC,measured = 18 mA
3. vdd = 3.6V, IB = 17 mA, IDC,measured = 48 mA
4. vdd = 3.6V, IB = 8.5 mA, IDC,measured = 44 mA
133
The LNA was supplied with a 1.8V voltage, its input was connected to
the Agilent E4432B signal generator configured for -30 dBm output signal at a
frequency of 2 GHz. The output of the amplifier was connected to the Agilent
E4403B spectrum analyzer. The snapshot of the measurement result is shown in
Fig. 5.19. We notice around 9 dB gain, at a frequency of 2 GHz instead of 23.2
Figure 5.19: Measurement of output signal power at 2 GHz, -30 dBm input signal
dB gain as shown in the simulation plot in Fig. 5.6. The loss of RF coaxial cable
which is around 0.8 dB was taken into account.
134
Next, the LNA was supplied with a 1.8V supply voltage, and bias current
of 8.5 mA and connected to the Agilent E5062A Network Analyzer in order to
measure the S-Parameters. The minimum power used during a measurement was
-5 dBm which is higher than the simulated 1 dB input referred compression. The
S11 results are shown in Fig. 5.20 and S21 results are shown in Fig. 5.21. It can
be seen that the S11 parameter which is around -7.3 dB at 2 GHz is larger than
what we could see in the simulation plot in Fig. 5.5 which was -19.6 dB. Also we
can see that the S21 gain is around 5.2 dB at the frequency of interest as well
as over a broad range of frequencies around 2 GHz. This value is also different
from the simulation plot of S21 shown in Fig. 5.6. We notice that at very low
frequencies S21 is extremely low, which was planned and which is provided by the
blocking capacitors implemented on-chip.
Figure 5.20: Measured S11 with -5 dBm power
135
Figure 5.21: Measured S21 with -5 dBm power
Providing higher power to an amplifier input drives it deeper into com-
pression. Figs. 5.22 and 5.22 show the S11 and S21 measurements with 0 dBm
power. From the snapshots we can see that S11 at the frequency of interest is
-5.9 dB and S21 is only 0.5 dB.
136
Figure 5.22: Measured S11 with 0 dBm power
137
Figure 5.23: Measured S21 with 0 dBm power
138
Next, a series of measurements with different input power at 2 GHz has
been done with the signal generator and spectrum analyzer. The output power
from the amplifier was measured and recorded for each test. Table 5.1 shows the
input power provided to the amplifier, measured output power and gain. The 0.8
dB loss of RF coaxial cables was taken into account again. From the results shown
Table 5.1: Measured output power given the input power at 2 GHz
Input Power, dBm Output Power, dBm Gain, dB
-30 -21 9
-25 -16 9
-20 -11 9
-15 -6.2 8.8
-10 -1.9 8.1
-5 -0.15 4.85
0 0.13 0.13
in Table 5.1 we can conclude that 1 dB compression point is roughly at -10 dBm
compared to simulated value of -19 dBm as shown in Fig. 5.11.
139
Next, the supply voltage was increased up to 3.6V and S21 parameter was
measured again. The snapshot is shown in Fig. 5.24. We notice 9.6 dB gain.
Figure 5.24: Measured S21 at 3.6V supply
5.4.2 Investigation
In order to troubleshoot and figure out the operation of the LNA, firstly
simulation tests have been performed which conform to the four different types
of measurements done before. Below is a list of simulations with normal corners
with DC parameter measurements.
1. vdd = 1.8V, IB = 8.5 mA, IDC,measured = 36.8 mA
2. vdd = 1.8V, IB = 17 mA, IDC,measured = 49.5 mA
3. vdd = 3.6V, IB = 17 mA, IDC,measured = 129 mA
140
4. vdd = 3.6V, IB = 8.5 mA, IDC,measured = 114 mA
We can observe that the results of DC current through the supply line is
way off from the measured four sets. There can be several reasons for that, such as
high loss and resistance of the inductors with their interconnects. The degraded
S21 parameter can be due to the fact that inductors and interconnect lines had a
high loss. Poor matching can be due to the low Q of the inductor.
One of the important details regarding the layout of LNA was the fact that
inductors were implemented with level 6 and 5 metals; however, right after the
inductor the connection was brought down to level 2 metal and continued to the
appropriate nodes on a relatively long path. The width of the level 2 metal was
1.96 µm. That might have contributed to a high DC resistance as well as AC loss.
At this stage, the decision was made to obtain access to an Electromagnetic
3D simulation package and simulate the inductors together with their connection
lines in order to figure out their true Q, inductance values both in shunt and
differential configuration, as well as resistance and loss at all frequencies. At the
time the LNA was designed and layed out we had no way of estimating all the
above mentioned parameters at all frequencies. We could only rely on the standard
models provided by the IBM 7RF design kit; however, it did not include the effect
of losses from our specific layout due to interconnects. Also those models are not
as precise anyway.
The tool which was used to simulate each inductor from layout and create
a more realistic model for it to be re-used in Spectre or MMSIM was Agilent
Momentum within the ADS package. The link was created between the Cadence
environment and Agilent Momentum simulator and each inductor from the layout
cell of LNA was transfered to a separate layout cell for the Momentum 3D EM
simulation.Figs. 5.25, 5.26, 5.27, 5.28, 5.29 and 5.30 show the inductance,
141
Q-factor and Resistance both in shunt and differential configuration of inductor
calculated as shown on each plot from the simulated S-Parameters. Inductor
modeling and parameter computation techniques are detailed in Okada [9].
Figure 5.25: Ls inductor parameters in the left branch
142
Figure 5.26: Ls inductor parameters in the right branch
143
Figure 5.27: Lo inductor parameters in the left branch
144
Figure 5.28: Lo inductor parameters in the right branch
145
Figure 5.29: Lg inductor parameters in the left branch
146
Figure 5.30: Lg inductor parameters in the right branch
147
The first thing we notice is very high resistance for all the inductors at
all frequencies. The next thing is extremely low Q-factor of Ls inductor which
can explain poor input matching. A broadband model of each inductor which
accounts for our layout interconnects and DC characteristics was created from
the Momentum results. The model was re-used in the LNA for the simulation
purpose. Each inductor from the Design Kit was replaced by that model as
shown in Fig. 5.31. Table 5.2 shows the simulated and measured DC current under
Figure 5.31: LNA schematics with each inductor replaced by Momentum gener-ated model
different supply and bias conditions. First and second columns show the data for
normal and slow corners, respectively. The third column shows the normal corners
but with all inductors replaced by Momentum generated model which accounts
for not only inductor but the interconnect lines. The fourth results column shows
the measured data. We can see now that the column representing measured data
148
does not egree neither with the normal simulated corner results nor with the slow
simulated corner results, however; it does agree very well with the normal corner
simulation which uses Momentum models.
Table 5.2: DC current under different supply and bias conditions
IDC , tt IDC , ssf IDC , tt, MoM IDC , Measured
vdd = 1.8V, IB = 8.5 mA 36.8 mA 31 mA 14.3 mA 16 mA
vdd = 1.8V, IB = 17 mA 49.5 mA 43.6 mA 18 mA 18 mA
vdd = 3.6V, IB = 17 mA 129 mA 117.4 mA 45.6 mA 48 mA
vdd = 3.6V, IB = 8.5 mA 114 mA 102.4 mA 41.5 mA 44 mA
The S21 gain at the frequency of interest during the normal corner simu-
lation with Momentum inductor models still was around 7dB, it is not 23dB as
it was in the first simulation; however, it is close to 9 dB gain which we observed
during the measurements.
Obviously, we see that the layout had a huge impact on the operation of
the LNA and in the simulation it decreased S21 parameter significantly. We also
take into account the fact that in the layout inductors were not placed far enough
from substrate contacts, which accounted for additional signal loss. As a result
during experementation we had 9 dB gain under normal operating conditions.
5.5 Design Modification
The next step was obviously to correct the errors. A new LNA has been
designed. This time the decision was made to make it even simpler, just with
one stage and blocking capacitors off-chip for more accessible DC testing. The
schematics is shown in Fig. 5.32. We also removed the on-chip huge decoupling
149
Figure 5.32: Schematics of the modified LNA
capacitors, since it is not that practical in terms of space, and since the newly
designed inductors hold their inductance well up to the required operating fre-
quency. The new design only has one common source stage, a diode-connected
transistor and three inductors. The size of the main amplifying transistor TN2
is 328 µm as well as the size of TN5 . The size of TN3 is twice less. Resis-
tor RPC0 at the bias line has increased the value to 10 kOhm for better AC
blocking at the bias line. The shunt inductor at the source, shunt inductor at the
supply line and the gate inductor have square outlines of 100 µm, 160 µm and
150 µm, respectively. After the design was completed and tweaked, each inductor
was simulated using Momentum as described previously. Each inductor was also
made just using layer 6 metal for spiral, and layer 5 metal for connecting another
side of it to the circuit. There was no grounded metal layer 1 plane underneath it.
Simulations and inductor parameter computations for each inductor are shown in
150
Figs. 5.32, 5.32 and 5.32. The first thing we notice is much lower resistance at
Figure 5.33: Lg inductor parameters for Modified LNA
the frequency of interest for the source inductor of about 2 Ohms compared to 19
Ohms for the inductor of the initial LNA. We also notice that the Q-factor for the
source inductor in this case is 2, compared to Q-factor of only 0.4 of the initial
LNA. This is 5 times improvement of inductor Q-factor. This was achieved by
laying out interconnect lines from the inductor on metal levels 6 and 5. Inductor
itself was implemented on level 6 metal. The width of metal 6 interconnect line
this time was 10 µm compared to the width of 1.96 µm metal 2 interconnect line
in previous LNA. The inductor parameters shown in the figures account for the
new layout of interconnect lines.
151
Figure 5.34: Ls inductor parameters for Modified LNA
152
Figure 5.35: Lo inductor parameters for Modified LNA
153
After the layout was optimized and inductor parameters including the lay-
out of interconnect lines were calculated, the broadband models were again created
in Momentum for re-simulation in Spectre. The testbench also was modified and
included S-Parameter models of the off-chip C0G class capacitors from Kemet.
The modified testbench is shown in Fig. 5.36. The boxes close to the input and
Figure 5.36: Testbench for the modified LNA
output port instances represent models with S-parameters of the off-chip capaci-
tor. The S-parameters of the new LNA are shown in Figs. 5.37, 5.38, 5.39 and
5.40. Simulation was done with 1.8V supply voltage, 8.6 mA bias current and the
DC current through the amplifying stage was 15 mA. Fig. 5.41 shows the Noise
Figure simulation which is now 3.15 dB at 2 GHz.
154
Figure 5.37: S11 of Modified LNA
Figure 5.38: S21 of Modified LNA
155
Figure 5.39: S12 of Modified LNA
156
Figure 5.40: S22 of Modified LNA
Figure 5.41: Noise Figure of Modified LNA
We notice that the S21 gain at the frequency of interest now is 13.6dB
which is less than for the previous design. The output is not matched to 50 Ohm
load. As a result, S22 at the frequency of interest is -6.6dB. However, those are not
the main criteria for the modified design. The main purpose of this re-design is
to explore the agreement between simulation with Momentum-generated inductor
models and real measurements.
157
Another measurement was performed for S11 and S21 parameters using
the Spectre models from Design Kit for inductors. The results are shown in
Fig. 5.42. We notice that values for S11 and S21 at 2 GHz are approximately 3
Figure 5.42: S11 and S22 of the modified LNA using Spectre models for Inductors
dB higher than those shown in Figs. 5.37 and 5.38, which is why it was necessary
to simulate the inductors taking into account the interconnect lines in order to
tune the amplifier for the required response more precisely.
After a satisfactory simulation, which included inductors with models cre-
ated from the layout simulation, the second LNA design was finalized and sub-
mitted for manufacturing.
The layout of the LNA has a huge impact on its operation. Inductance
values at different frequencies, losses and Q-factors are very sensitive to how the
interconnect was implemented. At very high frequencies interconnect has to be
done using the transmission line concept (almost the way the test PCB’s were
designed for all boards in these projects). The new actual layout pictures cannot
be shown due to the NDA aspects of the 7RF Design Kit.
Below are important considerations regarding LNA layout:
158
1. Keep the inductor layout side and corners far away from substrate contacts,
maybe around 100 µm.
2. If the inductor is implemented with top metal, connect it to your circuit
using that same top metal and a thick line of about 10 µm. Depending on
the process, the width might be more or less. Do not use vias to go down
to the lower level metals right near the inductor borders.
3. Consider using some type of 3D EM solver to simulate your inductor with
interconnect lines the way they appear in your real layout. After that sim-
ulation depending on the EM tool, either the S-parameters can be used in
your Spectre model, or the tool can create the model itself or another tool
will have to be used in order to create the lumped elements model of the
simulated inductor for using it in Spectre.
4. If interconnect lines are too long and the frequency is too high, consider im-
plementing them as stripline transmission lines. In that case the help of the
EM tool with the knowledge of metal thickness and dielectric permettivity
in between metal layers will be required for proper simulation.
5. Keep big top level metal shapes and objects far away from inductor.
5.6 Conclusions and Future Work
This work presented the design, implementation and further development
of the 2 GHz Low Noise Amplifier. The design process included many techniques
from a wide range of areas, such as inductor modeling, high-speed RF layout,
matching testing and troubleshooting. The first version of the LNA was manu-
factured and had some problems; however, it was carefully analysed, proper tools
for 3D EM simulation have been used and the design was completely re-done and
159
submitted for manufacture again. This work demonstrates the importance of RF
sensitive layout and usage of the proper RF 3D CAD tools in conjunction with
the Virtuoso CAD tool for LNA design.
Future work includes testing the newly submitted and redesigned LNA,
using a different set of equipment in order to perform other types of measurements
such as Noise Figure, third order intermodulation etc. as well as the design of other
types of LNAs with different architectures. Another important step which will be
done soon is more careful RF modeling of the PAD parasitics, characterization of
the package parasitics and the creation of the simulation model for it in order to
more realistically model the effect of PAD+ESD+Package parasitics, since it is
very important when it comes to the design of LNAs working at a high frequency.
160
Appendices
161
APPENDIX A
REFERENCES
162
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biased techniques,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 31,
no. 11, pp. 1723–1732, November. 1996.
[4] A. H. Thomas H. Lee, “Oscillator phase noise: A tutorial,” IEEE JOURNAL
OF SOLID-STATE CIRCUITS, vol. 35, no. 3, pp. 326–336, March. 2000.
[5] NuTune, How to measure Phase Noise with a Spectrum analyzer. NuTune,
2010.
[6] W. Kester, Converting Oscillator Phase Noise to Time Jitter. Analog Devices,
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[7] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, Second
Edition. Cambridge University Press, 2003.
[8] B. Razavi, RF Microelectronics. Prentice Hall, 1998.
[9] K. M. Kenichi Okada, Modeling of Spiral Inductors, Advanced Microwave Cir-
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163