design of cuk derived transformerless´ common grounded pv ...€¦ · index terms—single stage...

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2017.2677352, IEEETransactions on Industrial Electronics

Design of Cuk Derived TransformerlessCommon Grounded PV Micro-inverter in CCM

Vasav Gautam Student Member, IEEE, and Parthasarathi Sensarma, Member, IEEE

Abstract—Photovoltaic micro-inverters dispense withthe line frequency transformer, however at the cost ofsystem grounding and ground leakage current problems.These have been erstwhile resolved by the topologies de-rived from buck, boost, buck-boost, Zeta, Watkins-Johnsonand Cuk converters, or combinations of these. The Cukderived inverters, employing second order input and out-put filters, offer the most efficient, lightweight and eco-nomical solution in the class. This paper presents designand detailed operation of a Cuk derived, common-groundPV micro-inverter in continuous conduction mode (CCM)operation. The inverter is shown to be compatible withboth linear and non linear loads, in stand-alone and gridconnected modes of operation. Optimal design rules ofpassive components are rigorously derived to ensure at-tenuation of input voltage ripples arising from the twineffects of switching and double-frequency output poweroscillation. Additionally, the design rules also incorporateconsiderations of efficiency maximization and some as-pects of easing control complexity. Inverter performanceis experimentally validated with a 300 VA, 110 V, 50/60 Hzlaboratory prototype.

Index Terms—Single stage inverter, transformerless in-verter, common grounding, PV inverter, inductor design

I. INTRODUCTION

Potential induced degradation of solar photovoltaic (PV)modules is caused by ground leakage current [1], whichreduces module power capacity. Leakage current occurs dueto common mode voltage (Vcm), defined as [2],[3]

Vcm = (Van + Vbn) /2, (1)

in an H-Bridge inverter (Fig. 1). While using unipolar pulsewidth modulation (PWM), Vcm varies at inverter switchingfrequency and its multiples. The low impedance offered bythe parasitic capacitance (Cpv), between earth and PV, atthese frequencies causes large common mode currents [2],[3].Reduction in the common-mode frequency has been achievedusing bipolar PWM [4] or multi-level, neutral-point clamped(NPC) transformerless topologies [4],[5], or its variant usingsplit inductors [4],[6],[7]. But these offer no voltage boost andhence require series connection of a large number of PV panelsor a prior boost stage, both of which degrade efficiency.

Manuscript received November 14, 2016; revised February 7, 2017;accepted February 14, 2017. This work was supported by the Depart-ment of Science and Technology, Government of India under GrantDST/RCUK/SEGES/2012/14 (C).

The authors are with the Department of Electrical Engineering, In-dian Institute of Technology Kanpur, India (phone: +91 512 2597822,fax: +91 512 2590063, email: [email protected], [email protected],[email protected]).

Cin

CPV

PV

Filtera

b

n

Fig. 1: Leakage current in H-bridge inverter

H-bridge derived topologies, viz. H-5, H-6, HERIC [8] andHB-ZVR inverters [9] decouple the PV modules from thegrid during current freewheeling, when the PV terminals areleft floating. For such PV systems, NEC 690.35 stipulatesadditional ground fault protection. Since the utility neutralis already earthed, this additional protection is inherentlyobviated in common-grounded PV interface. Though a line-frequency transformer easily achieves double grounding, itmakes the system bulky. Topologies using high frequencytransformers [10],[11] suffer from increased losses in theensuing three-stage power conversion.

Several common-grounded, transformerless topologies havebeen reported in literature [12]-[23], which implicitly combinebuck-boost and inversion functions. Of these [12], a buck-boost derived topology comprises five active switches andtwo diodes. In every half cycle, the inductor connectionswith respect to the output capacitor are reversed by a switchnetwork. A variant [13], based on the same principle, usesan extra diode. However, both are unable to transact reactivepower because the series diodes prevent current reversal. Usinga pair of coupled inductors, [14] proposes a combination ofCuk and Watkins-Johnson topologies. However, this resultsin higher currents in the coupled windings, which increasesboth inductor size and losses. In [15], the circuit topologyalternates between a Cuk converter, during the negative half-cycle of the output ac voltage, and Zeta converter, for thepositive half. Since the plant model changes every half-cycle,controller design becomes exceedingly complex.

An interesting Cuk derived topology [16] achieves cyclicreversal of the connection between the intermediate dc linkcapacitor and the output filter, during each half cycle of theoutput ac voltage. Plant models in the two modes, correspond-ing to positive and negative output voltages, are similar [24].Since the inverter retains all the advantages of a Cuk converter,in terms of efficiency, weight and cost [25], it is the bettersolution in the class. Another variant [17] uses an extra switchin the freewheeling path of the output filter to reduce conduc-



tion loss. In both [16] and [17], use of diodes in series withswitches prevent load and source current reversal within eachof the modes. Also, the switching sequence is only applicablefor unity power factor (UPF) loads, which unnecessarily limitsthe scope of this promising circuit topology. The major lacuna,however, is in the lack of any justifiable basis for the majorperformance metrics and design equations which, on someoccasions, lead to unacceptable inaccuracies. No analytical orexperimental validation of the design rules, for the passivecomponents in the circuit, is provided.

This paper presents a modification in the topology of[16],[17], which allows bi-directional power flow, hence en-abling applications involving reactive loads, in addition toUPF loads. It thus includes a thoroughly different switchingstrategy, apart from justified circuit design rules. Operationof the proposed converter is presented in section II, wheresteady state expressions for inverter states and voltage gainare derived for ideal and non-ideal circuit elements. SectionIII analyzes the effect of double-frequency power oscillationon the input voltage. Section IV systematically lays downwell-justified and vastly improved design rules for the invertercomponents. All analytical conclusions are experimentallyvalidated with a 300 VA laboratory prototype.

II. CIRCUIT DESCRIPTION AND OPERATION

Circuit diagrams of the inverter in grid connection (GC)and stand-alone (SA) modes are shown in Fig. 2. The circuitdoes not require any common-mode noise filter. The negativeconductor and grid neutral (N ) are shorted to ensure commongrounding hence reduced or no common mode ground current.In GC mode of operation earth connection is provided throughgrid neutral, whereas in SA mode the negative rail is earthedto avoid runaway potential at the circuit nodes.

Composition of circuit elements includes one dc capacitor(C1), five MOSFET (two quadrant) switches (S1−S5) and sec-ond order input (Cin, L1) and output (C2, L2) filters. SwitchS1 is considered as the main switch and the time interval whenswitch S1 is ON is designated as ON time, the remainingduration of the switching period is designated as OFF time.

Depending upon output voltage polarity the inverter operatesin two modes, as described below. For ease of explanation, thePV source is replaced by a dc voltage source, Vin.

L1

C1

2S

3SS5

4S

L2

C2

Lg

Cin

vin

N

vgS1

A

PV

+

−

+

−

(a) Case I: The inverter in GC mode

L1

vo

1i vc1

L

OA

DS1

2i

L2

S2

C2

V

Pinv

Cin

C1

S3

S4

S5

+

−

++

(b) Case II: The inverter in SA mode

Fig. 2: Inverter schematic

A. Mode-1 (Vo > 0)Figures 3a and 3b, respectively, show the circuit configu-

rations for the ON and OFF times in this mode of operation.Reference capacitor voltage polarities and inductor currentdirections are indicated. The actual inductor current directiondepends upon the load. Switch current (iS1, ..., iS5), inductorcurrent and capacitor voltage waveforms with switching sig-nals, Sg1, ..., Sg5 of devices S1, ..., S5 respectively, are shownin Fig. 4a. Since MOSFETs allow bi-directional current flow,the inverter operates in continuous conduction mode (CCM)under all the load conditions.

Considering flux-balance of inductors L1 and L2, steady-state duty cycle average (DCASS) [26] of vc1 and vo, overone switching period, Ts, are obtained as

V(1)c1 = Vin + V (1)

o , (2)

V (1)o = Vin

D

1−D, (3)

where, D is the steady state duty cycle.Equating input and output powers, and using (3), DCASS ofi1 is expressed as

I(1)1 =

V(1)o

VinIo =

D

1−DIo, (4)

where, Io is the duty cycle average of the load current. Peak topeak switching ripple in i1, vc1 and i2 (4i1, 4vc1 and 4i2),are

4i1 = (VinDTs)/L1, (5)

4vc1 = |I(1)1 |(1−D)Ts/C1 = (|Io|DTs)/C1, (6)

4i2 = V (1)o (1−D)Ts/L2 = (VinDTs)/L2. (7)

Currents passing through switch pairs (S1, S5) and (S3, S4) arei1 and i2, respectively. During ON period current through S2

is i2, whereas during OFF period this is (i1 − i2). SwitchesS1 and S3 − S5 are required to block a forward voltage ofmagnitude equal to |vc1|. Energy transfer during ON and OFFtimes depends upon load current direction. Thus two cases areformed, which are as follows.

1) Case-1a, (Io > 0): This is the forward powering mode.Inductor current directions are as shown in Figs. 3a and 3b.

2) Case-1b, (Io < 0): This is the forward braking mode,which is relevant for reactive loads. Inductor current directionsare opposite to those shown in Figs. 3a and 3b.

B. Mode−2, (Vo < 0)

Figures 3b and 3c, show the circuit configurations for thismode during OFF and ON times, respectively. Switchingwaveforms of capacitor voltage, inductor current and switchcurrent are shown in Fig. 4b. In this mode, S1 and S2 areswitched in a complementary manner. Also, throughout theswitching period, both S4 and S5 are kept in conduction whileS3 is not triggered at all. Assuming switching ripples on thestates are small, expressions for DCASS of vo and vc1 are

V (2)o = −Vin

D

1−D, (8)

V(2)c1 =

Vin1−D

= Vin − V (2)o . (9)



1L

v1c

L2

2i1i

C2

L

OA

D

vo

io

S1

vin C1

S5

S2

3S

S4

++

+

−

(a) mode−1, ON period

1L

v1c

L2

2i1i

C2

L

OA

D

vo

io

S1

vin C1

S5

S2

S4

S3

++

+

−

(b) mode−1 and 2, OFF period

1L

v1c

L2

2i1i

C2

L

OA

D

vo

io

S1C1v

in

S5

S2

S4

S3

+

−

++

(c) mode−2, ON period

Fig. 3: Circuit diagrams during various operating states of the inverter

g4S , S g5

Sg2

g1S , S g3

vc1

vo

i1

i2

iS1 iS5

S2i

iS3 iS4

(a) Mode−1

g4S , S g5Sg3

Sg1

Sg2

vc1

vo

i2

i1

iS1 iS2

S4i , i

S5iS3

(b) Mode−2

Fig. 4: Switching signals, inductor current, switch current andcapacitor voltage waveforms

Current i1 and switching ripple in states (4i1, 4vc1, 4i2)are expressed by (4)-(7), which were derived for Mode 1operation. Currents passing through switch pair (S1, S2) is(i1 − i2) and that through S4 is i2. Switch S5 carries i2and i1 during ON and OFF periods, respectively. The forwardblocking voltages of S1, S2 and S3 are identically equal tothe magnitude of vc1. The two cases for different directionsof load current are as follows.

1) Case−2a (Io < 0): This is the reverse powering modeand inductor current directions are as shown in Figs. 3b and3c.

2) Case−2b (Io > 0): This is the reverse braking mode andarises while feeding reactive loads. Inductor current directionsare opposite to those shown in Figs. 3b and 3c.

C. Dead-time operationMOSFET pairs (S1, S5), (S3, S4) in mode-1 and (S1, S2)

in mode-2 appear across C1 and the devices in each pairsoperate in a complementary manner. Similarly, for modechangeover during ON period, switching takes place betweenpairs (S2, S3) and (S4, S5). No switching in MOSFETs takesplace during OFF period mode changeover.

To prevent shorting of C1 during switching of powerdevices, the dead-time introduced between complementaryswitching signals cause an interval when no MOSFET in theabove pairs is in conduction. Since any interruption in inductor

1L

v1c

L2

2i1i

C2

L

OA

D

vo

io

S1

vin C1

S5

S2

S4

S3

++

+

−

(a) mode−1 (i1, i2 > 0)

1L

v1c

L2

2i1i

C2

L

OA

D

vo

io

S1

vin C1

S5

S2

3S

S4

++

+

−

(b) mode−1 (i1, i2 < 0)

1L

v1c

L2

2i1i

C2

L

OA

D

vo

io

S1

vin C1

S5

S2

S4

S3

++

+

−

(c) mode−1 (i1 > 0, i2 < 0)

1L

v1c

L2

2i1i

C2

L

OA

D

vo

io

S1

vin C1

S5

S2

S3

S4

++

+

−

(d) mode−1 (i1 < 0, i2 > 0)

1L

v1c

L2

2i1i

C2

L

OA

D

vo

io

S1

vin C1

S5

S2

S4

S3

++

+

−

(e) mode−2 (i1 − i2 < 0)

1L

v1c

L2

2i1i

C2

L

OA

D

vo

io

S1

vin C1

S5

2

S4

S3

S

++

+

−

(f) mode−2 (i1 − i2 > 0)

1L

v1c

L2

2i1i

C2

L

OA

D

vo

io

S1

vin C1

5

S2

S3

S4

S

++

+

−

(g) ON period mode switching, (i2 >0)

1L

v1c

L2

2i1i

C2

L

OA

D

vo

io

S1

vin C1

S5

S2

S3

4S

++

+

−

(h) ON period mode switching, (i2 <0)

Fig. 5: Circuit diagram during dead time interval

currents would cause disastrous spikes in switch voltages, thepresent topology ensures continuity of both inductor currents(i1, i2) during dead-time. Figure 5 shows these flow-paths,during dead-time, for all possible changeover situations. Itis thus shown that no inductor current is interrupted, whichprecludes any unwanted switch voltage stress.

D. Composite AC operationSince the converter is capable of operation in all the four

quadrants of the vo − io plane, without requiring any reversalin the source voltage polarity, quasi-static operation in eachmode successfully ensures inverter operation. Provided thefrequency of the output AC is significantly lower than theswitching frequency, it is also able to source a reactive load.Using (3) and (8), voltage gain of the inverter is succinctlyexpressed as

Av∆=

vovin

= sgn(vo)D

1−D= sgn(vo)

D

D′. (10)

Also, the general expression for the voltage across C1 is

Vc1 = Vin + |Vo|. (11)



0 0.2 0.4 0.6 0.8 1

0

2

4

6

8

10

Fig. 6: |Av|, |A(1)v | and |A(2)

v | as function of D.

Considering damping elements in the inverter, voltage gainsA

(1)v and A(2)

v for Mode-1 and Mode-2, respectively, are

A(1)v =

Av

1 + α2 + 2αsD′ +A2v(α1 + αs) +Av(αc +Dαs)

,

(12)

A(2)v =

Av

1 + α2 + 2αs +A2v(α1 + αs)− (3αs + αc)Av

,

(13)

where,αx = rx

V Arated

v2o,rated

cosφ, (14)

vo,rated and V Arated being the inverter rated output voltageand power respectively, φ the power factor angle, r1 and r2

internal resistances of L1 and L2 respectively, rc the ESR ofC1 and rs the ON resistance of each switch. Figure 6 plotsthe absolute values of these voltage gains as a function ofduty cycle for the values of rx, listed in table IV, ‘systemparameter’.

To generate a sinusoidal output voltage, the inverter isswitched alternately between these two modes at output fre-quency. From Fig. 6, the maximum gain for these two modesare seen to be unequal. Hence, to obtain a zero-mean output,the plausible voltage gain in inverter mode operation is statedas

Avi = min(|A(1)v |, |A(2)

v |). (15)

Ignoring internal losses, a closely approximated sinusoidaloutput voltage vo(kTs) = Vm sin(ωlkTs), of line frequencyωl, can be produced from a fixed input dc voltage, where kis the index of the switching cycle. The required variation inthe duty ratio is obtained from (10) as

d(kTs) =Vm| sin(ωlkTs)|

Vin + Vm| sin(ωlkTs)|. (16)

In the actual inverter, with inevitable presence of internaldamping, the exact duty ratio is to be determined using a close-loop control scheme. The controller generates a binary signalM which decides mode of operation and binary signal Sg ,which is same as switching signal for switch S1, Sg1. SignalSg and M generate switching signal for switches S2 − S5

(Sg2 − Sg5). The high state of M corresponds to mode-1 andhigh state of Sgi corresponds to ON state of switch Si. TableI lists the high(1)

/low (0) states of all the switching signals

during different intervals.

TABLE I: ON-OFF states of switches

SwitchingSignal

mode-1, M = 1 mode-2, M = 0ON period OFF period ON period OFF period

Sg = Sg1 1 0 1 0Sg2 1 1 0 1Sg3 1 0 0 0

Sg4, Sg5 0 1 1 1

III. EFFECT OF POWER OSCILLATIONS ON vin

From (11), it follows that over one cycle of the output acvoltage, vc1 and rectified vo, |vo| have same ac components.So |vo| can be expressed by a Fourier series as

|vo| = Vm| sin(ωlt)| = Vm

(ko +

∞∑n=1

k2n cos(2nωlt)

),

(17)where,

ko =2

π, k2n = − 4

π(4n2 − 1). (18)

Thus ac component of vc1 is

vc1,ac = Vm

∞∑n=1

k2n cos(2nωlt). (19)

Therefore current in C1, iC1is

iC1= C1

dvc1,acdt

= −ωlC1Vm

∞∑n=1

2nk2n sin(2nωlt). (20)

Capacitor current iC1 depends upon switch states and currenti1, i2 as follows

iC1=Sg1Sg3Sg5 (Sg2 + Sg4)

i1

+Sg2Sg4Sg5

i2 −

Sg2Sg3Sg5

i2. (21)

Realizing the switching combinations as a function of M andSg using table I, the low frequency components in iC1 are

< iC1 > =< Sgi1 +MSgi2 −MSgi2 >

= D′ < i1 > −sgn(vo)D < i2 > . (22)

Hence, using (10) and (22), < i1 > is expressed as

< i1 >=vovin

< i2 >︸︷︷︸T1

+1

D′︸︷︷︸T21

< iC1>︸︷︷︸

T22

. (23)

Since i2 is the summation of io and the current through C2,

< i2 >= Im sin(ωlt+ φ) + ωlC2Vm cos(ωlt). (24)

Using (24), T1 in (23) is expressed as

T1 =Vm2vin

[Imcos(φ)− cos(2ωlt+ φ)+ ωlC2Vm sin(2ωlt)] .

(25)Using (10), the term T21 in (23) is simplified as

T21 =1

D′= 1 +

|vo|vin

. (26)

Using (17), harmonic components in (26) are

1

D′= 1 +

Vmvin

[ko +

∞∑n=1

k2n cos(2nωlt)

]. (27)



Using (20), (23), (25) and (27) current i1 and its ac compo-nents i1,ac are expressed as

i1 =T1 − ωlC1Vm

∞∑n=1

ks2n sin(2nωlt), (28)

i1,ac =Vm2vin

ωlC2Vm sin(2ωlt)− Im cos(2ωlt+ φ)

− ωlC1Vm

∞∑n=1

ks2n sin(2nωlt), (29)

where,

ks2n = 2nk2n

(1 + ko

Vmvin

)+

nVmvin

∞∑m=1

k2mk2(n+m) +

[n−12 ]∑

m=1

k2mk2(n−m)

. (30)

The major part of i1,ac passes through capacitor Cin. There-fore voltage vin is expressed as

vin(t) = Vin + vin(t) = Vin +1

Cin

∫i1,acdt, (31)

where, vin(t) is the ac component of vin, expressed as

vin(t) =C1Vm2Cin

∞∑n=1

ks2n

ncos(2nωlt)

− Vm4VinωlCin

Im sin(2ωlt+ φ) + ωlC2Vm cos(2ωlt) .(32)

The ac components in vin is caused by the oscillation in loadpower. Cin is designed to attenuate these oscillations, whichis explained in the next section.

IV. DESIGN OF PASSIVE COMPONENTS AND SWITCHES

A. Selection of capacitor Cin

It is clearly shown in [27] that if PV voltage, vin hasa overriding oscillation, with amplitude 8.5% of the MPPvoltage, then utilization ratio of the panel reduces to 98%. Toensure no further reduction in utilization ratio, the maximumand minimum values of vin are obtained from (32). The peak-to-peak ripple voltage, 4Vin, across Cin, is obtained as

4Vin =C1Vm2Cin

∞∑n=1

ks2n

ncos(2nθ2)− cos(2nθ1)

− Vm4VinωlCin

[Imsin(2θ2 + φ)− sin(2θ1 + φ)

+ωlC2Vmcos(2θ2)− cos(2θ1)] , (33)

where, θ1 and θ2 are two consecutive zero-cross instants ofi1,ac. Table IV lists the system parameters, which are used in(33) to get minimum value of Cin.

B. Design of inductor L1 and L2

Design constraints for L1 and L2 are first individuallyspecified. Subsequently, details of engineering optimization tominimize losses are presented.

1) Constraints for L1: L1 is required to ensure the switch-ing ripple in vin is restricted to the allowable maximum,4V (s)

in . Thus,

4V (s)in ≥

1

2Cin

4i12

Ts2. (34)

Using (34) and (5), the constraint on L1 is expressed as

L1 ≥ L(1)1,min =

VinDT2s

8Cin 4 V(s)in

. (35)

Simultaneously, L1 is also required to restrict the switchingripple to an allowable maximum, 4i1,max. Therefore, using(5) and (10),

L1 ≥ L(2)1,min =

VinDmaxTs4i1,max

=VinTs4i1,max

VmVm + Vin

. (36)

Thus, the viable constraint for L1 is

L1 ≥ L1,min = max(L

(1)1,min, L

(2)1,min

). (37)

2) Constraint for L2: Minimum value of L2 is decided bythe maximum allowable switching current ripple. Using (7)and (10)

L2 ≥ L2,min =VinDmaxTs4i2,max

=VinTs4i2,max

VmVm + Vin

. (38)

3) Engineering optimization for minimal loss: With in-crease in inductance value the inductor rms current decreases,which decreases switch conduction loss. But decrease ininductance values decreases the diode current at turn OFFinstant. Thus reverse recovery loss is reduced. In case theinductor current ripple is high enough to change the switchcurrent direction, the body diode of the corresponding switchturns ON before the switch. Thus both, diode turn OFF andswitch turn ON transitions become lossless. However, switchturn OFF loss increases due to increased current magnitude.

Hence the optimization problem is formulated as

maximize, ηCEC

(L1, L2), (39)subject to,

Li ≤ Li,max, i ∈ 1, 2 (40)Li ≥ Li,min, i ∈ 1, 2, (41)

where, ηCEC

(L1, L2) is the inverter CEC efficiency, evaluatedusing accepted procedure [28],[29] for switching and reverserecovery (Prr) loss estimation. The values of L1,max andL2,max are decided by the inverter volume constraint. Forinductor loss estimation, the inductor resistance is updated bythe Dowell function [30] to include skin and proximity effects.The estimated losses at 100% load using parameters listed intable IV, are shown in table II.

C. Design of capacitor C1

The choice of C1 is based on restricting its per-unit voltageripple, ¯4vc1, which is expressed as

¯4vc1∆=4vc1Vin

=i2Vin

DTsC1

. (42)



TABLE II: Losses break-down

Component Conduction loss(mW)

Switching loss(mW)

Prr

(mW)S1 (D1) 4017.8 (22.7) 4555.2 7.7S2 (D2) 1207 (227.4) 86.6 3015.1S3 (D3) 449.2 (1.4) 313.4 1.2S4 (D4) 763.6 (55.3) 4.6 1541.4S5 (D5) 1116.6 (157.6) 77.2 2708.5L1 (L2) 146.7 (68.3) - -C1 (C2) 31.9 (33.8) - -

Substituting (10) and (24) in (42)

¯4vc1 =

∣∣∣∣ Gm| sin(ωlt)|1 +Gm| sin(ωlt)|

Im sin(ωlt+ φ) + iC2(t)

Vin

TsC1

∣∣∣∣ ,(43)

where, Gm = (Vm/Vin). This attains a maximum in ωlt ∈[0, π] at t = tc and φ = (π/2 − ωltc), where ωltc is thesolution of

Im cos(ωlt) +ωlC2Vmcos(2ωlt)−Gm sin3(ωlt) = 0 (44)

obtained from the time derivative of (43). Hence,

C1,min =Gm sin(ωltc)

1 +Gm sin(ωltc)Im + iC2

(tc)TsVin(

¯4vc1)max

. (45)

D. Designing capacitor C2

Choice of C2 is based on improvement of the dampingfactor associated with the oscillations in the output voltage,vo. This is obtained from the impedance function, Zp = vo/i1,which is derived from the “dc-transformer” model [26] of theconverter as shown in Fig. 7. Thus,

Zp(s) =sgn(vo)D(1−D)

s(C1C2L2s2 + C1C2r2s+ C1 + C2D2). (46)

The natural frequency, ωo, and damping factor, ζ, [26] are

ωo =

√C1 + C2D2

L2C1C2, (47)

ζ =r′22

√C1C2

L2

1

C1 + C2D2, (48)

where, r′2 is the ac resistance of L2 at frequency ωo.Impedance Zp at the frequency, ωo is

Zp(jωo) =L2

r′2

D(1−D)

(C1 + C2D2). (49)

Increasing C2 improves the damping factor, which easesthe constraints for controller design. But it also decreases theresonance frequency, ωo, which limits the control bandwidth,despite improving switching ripple attenuation. This conflictis resolved by nominally choosing C2 so that the naturalfrequency is close to (but larger than) the overall systembandwidth. The exact value obviously requires slight tuningduring controller design.

E. Selection of switchesMinimal switch rating is obviously based on the maximum

on-state current and off-state voltage, which are detailed insection-II. Based on this, table III lists the selection criteriafor all the converter switches.

vc1

Dvc1

Di2

vc1

vo v

o

D’i1

1sC

1D’i1

1sC

1

Di2

Dvc1

2sC

12

sC1

sL +r ’22sL +r ’

22

(b)(a)

Fig. 7: Converter model for (a) vo > 0 and (b) vo < 0

TABLE III: Switch Ratings

S1, S2 S3, S4 S5

Current Im1 + (Vm/Vin) Im Im(Vm/Vin)Voltage Vm + Vin Vm + Vin Vm + Vin

V. RESULTS AND DISCUSSION

A 300 VA, 110 V, 50/60 Hz MOSFET based converteris fabricated in laboratory (Fig. 8), according to the designrules presented earlier. Switching signals are generated usinganalog electronics, supported by a low-cost FPGA in the back-end. The experimental set-up includes a pair of roof-mountedsolar photovoltaic (PV) panels, which are used to test inverterperformance. All system data are presented in Table IV.

Figure 9a shows inverter output voltage, vo and PV terminalvoltage, vpv and its ac components, vpv,ac, for a 300 W resis-tive load. It shows that the crest and trough of vpv,ac lag zerocrossing of vo by 32.9 and 127.4 respectively. These ob-servations corroborate the analytical results (35.09,127.50)obtained from (32), which validates the design considerationsfor limiting the effect of double-frequency power oscillation.Figure 9b shows the frequency spectrum of the inverteroutput voltage for this load condition and its THD is 3.08%,which satisfies IEEE 519-2014 requirements (THD≤8%). Theinverter performance under grid connection is shown in Fig.9c, 4.55% THD in injected current, also fulfills IEEE 519-2014. Figure 10 showing output voltage and load current for145 VA, 0.5 pf load confirms its capability of feeding reactiveloads.

Performance with a non-linear load is tested with a diodebridge rectifier load (300 W) feeding an R-L network. Corre-sponding output voltage and load current waveforms are shownin Fig. 11. Measured THD in output voltage is 2.88%, whichhighlights low inverter output impedance.

Next the inverter is supplied from a PV panel, while feedinga resistive load and Fig. 12 shows the variation of PV outputpower and current with PV voltage. At start, the inverter outputvoltage is zero, and the PV is under open circuit condition(point-A). The MPP tracker gradually increases the load, by

Fig. 8: Inverter prototype



ov

vpv

vpv,ac

(a) With a 300 W resistive load

1 2 3 4 5 6 7 8 9 100

0.5

1

1.5

2

2.5

3

3.5

Harmonic order

Ma

gn

itu

de

(%

of

fun

da

me

nta

l)

vo

IEEE std. 519−1992

(b) Frequency spectrum of vo in SA mode

vg

ig

(c) Under grid connection

Fig. 9: Inverter performance in SA and GC modes. Scale: vo (50 V/div), vpv,ac (2 V/div), vpv (10 V/div), grid voltage vg(50 V/div), grid current ig (1 A/div), Time (10 ms/div)

TABLE IV: System parameters

Inverter rating input 40-100 V dc,output 300 VA, 110 volts

Switching frequency, fs 50 kHzL1 and r1 52 µH, 2 mΩL2 and r2 120 µH, 7 mΩC1 and ESR 11 µF, 8 mΩC2 and ESR 3.8 µF, 21 mΩCin and ESR 2.2 mF, 65 mΩ

rs 100 mΩS1, S2, S5 (S3, S4) IRFP4868 (FDA38N30)

iovo

Fig. 10: System performance with non-UPF load. Scale: vo(50 V/div), io (500 mA/div), Time (10 ms/div)

iovo

Fig. 11: System performance with non-linear load. Scale: vo(50 V/div), io (1 A/div), Time (10 ms/div)

increasing output voltage, until MPP is reached (point-B).Another similar panel is switched in series with the connectedpanel, so net power and open circuit voltage VOC are doubled.The I−V curve moves to new MPP point C. Hence the invertercan be easily controlled to maintain power balance between aPV source and a standalone load. With an MPPT loop it canalso be used for direct grid-connected operation.

Figure 13 plots the estimated and experimental efficienciesat 50 V input, at different loads, and the correspondingCEC efficiencies are 94.43% and 94.55%, respectively. Closeagreement in these values validates the efficiency estimationapproach. Table V compares the inverter with recent reportedtopologies, under identical input-output conditions. The design

A

inVVin

PV

curr

ent

PV

pow

er B

C

A

B

C

Fig. 12: Maximum power point tracking. Scale: Vin (10 V/div),PV power (30 W/div), PV current (500 mA/div)

Load (in Watts)

50 100 150 200 250 300

Effic

iency (

%)

86

88

90

92

94

96

Experimental

Estimated

Fig. 13: Experimental and estimated efficiencies

rules legitimately employed for efficiency evaluation are usedto determine appropriate circuit parameters for each set ofinput-output conditions. Since both conduction and switchinglosses of the kth power device usually decrease with increasedcurrent rating (Is,k) for similar blocking voltages (Vs,k), aspecific metric to compare the rated output with the total VArating of M devices used is defined as the Device Utilizationfactor (DUF). Mathematically,

DUF = Prated

/ M∑k=1

Vs,kIs,k, (50)

is an inverse measure of over design and listed in the lastcolumn, where DUF of the proposed inverter for identical loadis shown in brackets. This shows that the topology ensuresmaximal switch utilization, minimal power device count (M )and the best efficiency for PV applications.

The switching components in voltage of Cpv , vCpv alongwith inductor current i1 and switching signal Sg1 are shown inFig. 14. Amplitude of vCpv is within 50 mV, which guaranteesnegligible leakage ground current, passing through Cpv . Formeasuring the ground current both the leads from the PV



TABLE V: Comparison with recent topologies

Topology Vin(volts)

vo(volts)

Prated

(watts) Mefficiency (%) DUF

(×10−3)Existing circuit Proposed[18] 60 110 500 12 94.1 (peak) 94.39 (CEC) NA (5.83)[19] 90 110 200 6 86 (peak) 96.33 (CEC) 0.417 (2.33)

[20] 100 110 500 8 92.5 (@500W) 95.73 (CEC)95.43 (@500W) NA (5.83)

[21] 60 110 100 8 90.2 (peak) 95.28 (CEC) 0.63 (1.17)[22] 48 110 200 7 89.3 (peak) 94.69 (CEC) 0.86 (2.33)[23] 45 110 110 8 90.1 (CEC) 94.63 (CEC) NA (1.28)

NA: Data not available

vCpv

S1

i1

Fig. 14: Switching signal Sg1, current i1 and vCpv . Scale: i1(5 A/div), vCpv (50 mV/div), Time (10 µs/div)

GC mode

SA mode

Fig. 15: Ground current in the system. Scale: current(1 mA/div), Time (10 ms/div)

source are passed through a current sensor and the recordedwaveforms are shown in Fig. 15. The amplitudes in grid con-nection (GC) and standalone (SA) modes are within 500 µAand 800 µA, respectively, which verify that the common modecurrent is indeed restricted even without any common-modenoise filter. This validates one of the main objectives of thetopology.

VI. CONCLUSION

This paper presents design, operation and performance ofa cost effective, compact, non-isolated, single-stage, single-phase dc-ac PV interface. The topology is specifically designedto practically eliminate common-mode ground leakage current,which has been validated experimentally. All the operatingmodes, including dead-time operation, are detailed. Optimaldesign of passive components is described, which considerripple components due to both switching and double-frequencypower oscillations. Additionally, design of all inductors isaimed at maximizing overall efficiency. Output filter designensures improvement in resonance damping for easing controlcomplexity, while minimally affecting power losses. Inverterperformance, with linear

/non linear loads in stand-alone mode

and UPF operation in grid connected mode, is verified byexperiment. Output voltage THD in stand-alone operation andoutput current in grid-connected mode are both shown to

satisfy IEEE 519-2014 stipulations. Comparison with recenttopologies, of comparable rating, is carried out on the basisof efficiency and switch utilization which shows that thetopology returns the most competitive efficiency figures. Thusthis micro-inverter fulfills all the demands of stand-alone andgrid-connected operation and is a strong candidate for reliablecommercialization.

ACKNOWLEDGMENT

The authors would like to thank Amit K. Basu, StyendraKumar and Nandkishore for their support during developmentof the experimental hardware.

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Vasav Gautam (S’13) received his B.Tech. inElectrical Engineering from Indian Institute ofTechnology, Kanpur, India in 2010. He is cur-rently working toward the Ph.D. degree in theDepartment of Electrical Engineering, Indian In-stitute of Technology Kanpur, Kanpur, India.

His research interests include design, model-ing and control of power converters.

Parthasarathi Sensarma (M’00) received hisB.E.E. (’90), M.Tech (’92) and PhD (2001) fromJadavpur University, IIT Kharagpur and IIScBangalore, India, respectively, all in the area ofElectrical Engineering. He had held positionsin Bharat Bijlee Ltd., Thane, India, CESC Ltd.,India and ABB Corporate Research, Baden-Daettwil, Switzerland, where he was a StaffScientist with the Power Electronics Depart-ment. Since 2002, he is with the Department ofElectrical Engineering, IIT Kanpur, where he is

presently a Professor. There he teaches courses on Power Electronicsand Electrical Engineering. His research interests include Power Quality,FACTS devices, Power converters and Renewable Energy integration.

design of cuk derived transformerless´ common grounded pv ...€¦ · index terms—single stage...

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