ee457_pipe_cpu_r3_Fall2009_Part5.fm 10/24/09 1 C Copyright 2009 Gandhi Puvvada / Lab #6 Part 5

EE457 Computer Systems Organization Lab #6 Part #5 of Fall 2009

Design of a Pipelined CPU (Part 5) (slightly different from part 2 design)

Important difference between the earlier part 2 and this part 5

In part 2 of the lab, we have a rather artificial division of the hazard detection mechanism in two parts (HDU and HDU_Br); similarly, we have an unnecessary division of the forwarding mechanism in two parts (FU and FU_Br). Also we do not need separate comparators for hazard detection and forwarding. In this part 5, we removed these four components and we are asking to add logic directly to the main design to perform the needed stalling and forwarding.

How many total 5-bit comparisons needed?

Basically an instruction in ID stage needs to see if it is dependent on instructions in EX and MEM stages. It does not have to check dependency on the instruction in WB stage as the internally forwarding register file takes care of the WB Hazard. So, basically we need four 5-bit comparators to compare the two source register IDs (identifications) of the instruction in the ID stage with the destination register IDs (identifications) of the instructions in the EX and MEM stages. We also need two 5-bit comparators (actually two 5-bit NOR gates) to check to see if the destination registers in EX and MEM are $0. Is it destination register or source register that we need to check to see if it is zero? Since you are acting (i.e. either stalling or forwarding) only when there is a match between a source register ID and a destination register in a stage ahead, it is one and the same!

When is it best to make these comparisons?

In early branch, you have to do these comparisons in the ID stage because you may need to stall a beq instruction in ID stage. Even in the late branch, two of the four comparisons (comparing with the destination register of the EX stage) are needed in the ID stage since you want to stall an instruction in ID stage if it is dependent on a lw in EX stage. While the remaining two comparisons in the late branch (the two comparisons corresponding to MEM hazard) can be postponed to EX stage, an experienced designer would do these comparisons in the ID stage as you would get timing

RegInstr.

HDU

Data

FU

IF ID EX MEM WB

BRANCH

BR

1

FU_Br

PC

cont

rol

HDU_Br

Zero

EQ

5 5

EQ

5 5

EQ

5 5

EQ

5 5

EQ

5 5

EQ

5 5