JADAVPUR UNIVERSITY

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

BCSE-IIIGROUP A1

DESIGN LABORATORY

ASSIGNMENT 1:DESIGN OF AN UP/DOWN DECADE COUNTER

Object:The project is to design a Two Digit Synchronous BCD Up/Down Counter with a data loading (preset) facility.

Properties:The Counter Circuit is to have the following facilities:

1. We can enable either the up counting mode or the down counting mode between the two limits of 00 to 99.The Maximum Count that can be counted by this Circuit is 99 and the Minimum Count that can be counted by this Circuit is 00.

2. The Counter recycles after reaching any one of those two limits (00 or 99) i.e. it is not Self-Stopping.

3. We can load any number of our choice between 00 and 99 at any time externally. There is a load input, which decides whether an external input will be accept or not.

4. The output of the counter should be displayed through two 7 Segment Display Units. One is used for MSB and other is for LSB displays.

To design a BCD Counter which will count from 00 to 99 (Up count) and also from 99 to 00(Down count), we need

1. Two 7 segment LED displays to display the MSB and LSB of the count.

2. Two BCD decade counter chips that serve as the backbone of the circuit. 3. Two BCD to 7 segment decoder chips that serve the interface between the

counter and display units.

4. A timer unit that will be used as an astable multivibrator for generating a clock pulse of desired frequency to drive the counter chips.

5. A NOT Gate chip used for transmitting the (inverted)carry pulse generated from the LSB to the clock input of the MSB counter chip.

.

SI No

Chip Code Purpose/Function Quantity

1. SN74LS191 BCD Up/Down Hex Counter 2

2. SN74LS47 BCD to Seven Segment Decoder Chip 2

3. LM555 Clock Generator (Astable Multivibrator) 1

4.

5.

SN74LS04

SN74LS00

NOT gate

NAND gate

1

1

Chips Used:

Other Components Used:

SI No

Name of the item Specification Quantity

1. LT542 Seven Segment LED Display 2

2. Carbon Resistances 470 Ohm 14

670 Ohm 1

330 Ohm 1

3. Connecting Wires

4. Wish Board 1

5. Electrolytic Capacitor 1 Microfarad 1

6. Ceramic Capacitor 0.01 Microfarad 1

Instruments Used:

SI No Name of the item Specification Quantity

1 D.C. Power Supply 5 Volt/0 Volt 1

2. Digital Multimeter KUSAM MECO 1

3. Oscilloscope 1

COMPONENTS USED

BCD UP/DOWN Hex CounterIC74lS191

Description

It is a BCD Up/Down Hex Counter, which has 4 external input lines named as A, B, C, D and 4 output lines, which are to be connected with driver’s input named as a, b, c, d. It also has a clock input, a count enable input, one load pin, one ripple carry output, one up/down pin and one max/min pin.

CLK:For asynchronous connection, the clock pulse is connected to the clock input of

the LSB chip only.______

CTEN: This is the count enable input of the chips. To keep the chips in counting mode,

this input should be LOW.______LOAD:

To load any external input to the chips, this input is kept LOW state and to disable loading it should be at HI State. _D/U:

This input selects the counting direction. For up counting, it is kept LOW and for down counting it is made HIGH.

Diagram:

7 - Segment DisplayLT – 542

Description:

It contains 7 LED s, with the help of which the binary digits are displayed. From the chip level diagram of 7-segment display it is evident that when output of the counter (i.e. input to the driver) is 0001, the display should be 1. In order to achieve this, Decoder output b, c must be HIGH, while a, d, e, f, g must remain LOW. Decoder performs this action. So driver is nothing but a Combinational Circuit. We observe that ‘a’ output will be HIGH if the input (equivalent decimal) is either of 0,2,3,5,7,8,9.

Diagram:

NOT GATECHIP-SN74LS04

Description:

This is a Hex inverter. It complements the given input. Inputs are given at the odd numbered pins 1,3,5,9,11,13 and corresponding outputs are obtained from the even numbered pins 2,4,6,8,10,12 respectively. Pin no. 7 is grounded, and pin no. 14 is connected to the supply. The truth table for the NOT gate is:

a b c d e f g .

V+

a b c d e f g .

V+

Diagram:

NAND gate IC 7400

Description:

Truth table:

Diagram:

7 SEGMENT DECODERCHIP- SN74LS47

Description:

A 7 Segment Decoder (also called a Driver ) is a chip which takes the BCD output of the counter as input and decodes it for 7 segment display, giving outputs a,b,c,d,e,f,g. the inputs are A,B,C,D the 4 bits of BCD output from counter. Two decoders are to be used – one for LSB and other for MSB. The driver chip is a 16 pin chip, of which pin 14 is to be connected with V cc and pin 7 is to be grounded. To display the BCD integer, the corresponding input lines to the 7 segment display are made High, so that the digit is shown. Three pins LT, RB1, RB0 are shorted and connected to V cc (5 Volts).

Diagram:

CIRCUIT DIAGRAM