design & implementation vhdl et062g & et063g lecture 7 najeem lawal 2012
TRANSCRIPT
Design & Implementation
VHDL ET062G & ET063G Lecture 7
Najeem Lawal 2012
2VHDL ET062G & ET063G Lecture 7
DESIGN & IMPLEMENTATION
OUTLINE– Line buffer diagnosis
– Creating the 3x3 window
– Computing Gx, Gy and edge output
Najeem Lawal, 2012
3VHDL ET062G & ET063G Lecture 7
DESIGN METHODOLOGY
Najeem Lawal, 2012
PROJECT DESIGN
Najeem Lawal, 2012 4VHDL ET062G & ET063G
Lecture 7
Camera Sliding Window
Sobel Operator
Range Sensor
Number Displayer
Range sensor
Monitor
Sobel WrapperTop Module
DESIGN TOP MODULE
Najeem Lawal, 2012 5VHDL ET062G & ET063G
Lecture 7
1.Connect FPGA to Camera, Range Sensor and Monitor through the UCF file
2.Interface modules by following the time diagrams
3.Use extra IO ports for debug purposes
SOBEL OPERATOR TOP MODULE
Najeem Lawal, 2012 6VHDL ET062G & ET063G
Lecture 7
1.Self contained image processing module
2.Can be simulated with input and output images
3.Contains sliding window and sobel operator
4.Can be synthesized to extract amount resources used
7VHDL ET062G & ET063G Lecture 7
TESTBENCH IMAGES
Najeem Lawal, 2012
SLIDING WINDOW
Najeem Lawal, 2012 8VHDL ET062G & ET063G
Lecture 7
1.Use 2 line buffers
2.Generates 3x3 pixels for the sobel
3.Simulate the linebuffers to investigate the synchronous alignment of the data
640
640
p1 p2 p3
p4 p5 p6
p7 p8 p9
Linebuffer
pdata_in
1 clock delay
SOBEL OPERATOR
Najeem Lawal, 2012 9VHDL ET062G & ET063G
Lecture 7
1.Given a set of 9 data calculate Gx, Gy and edge
2.Simulate to verify that the calculations work
3.What out for negative results!
p1 p2 p3
p4 p5 p6
p7 p8 p9
G’ = |Gx| + |Gy|
G = G’(8 msb)
Gx = (p3 – p1) + ((p6 & ‘0’) – (p4 & ‘0’)) + (p9 – p7)
Gy = (p7 – p1) + ((p8 & ‘0’) – (p2 & ‘0’)) + (p9 – p3)
9 bits 8 bits?
RANGE SENSOR
Najeem Lawal, 2012 10VHDL ET062G & ET063G
Lecture 7
1.Generate a pulse and send it out through the trigger port / pin
2.Use datasheet for duty cycle of the trigger
3.Capture the response, interpret it using a counter
RANGE SENSOR
Najeem Lawal, 2012 11VHDL ET062G & ET063G
Lecture 7
1.Output of sobel operator wrapper
2.Output of RS decoder interface (+VGA lab)
3.Select when to print which output based on last lecture
479
00
300
301
50
364
400
4020
64
if (vcount > 300 and vcount < 365) then
if ((vcount - 300) >= (64 - pixel_data(7 downto 2))) then
red_out <= "111";
green_out<= "111";
blue_out <= "11";
else
red_out <= "000";
green_out<= "000";
blue_out <= "00";
end if;
else
red_out <= red_in;
green_out <= green_in;
blue_out <= blue_in;
end if;
12VHDL ET062G & ET063G Lecture 7
RANGE SENSOR
Najeem Lawal, 2012
SRF05 HTTP://WWW.ROBOTSTOREHK.COM/SENSORS/DOC/SRF05TECH.PDF
– 10us pulse to the Trigger input – 50ms period between each Trigger pulse– Mode 1 recommended
SUMMARY
Najeem Lawal, 2012 13VHDL ET062G & ET063G
Lecture 7
SIMULATE TO VERIFY THAT IT WORKS– Include the simulation results in the report– Synthesis to extract the resource usage of each sub module
and include the usage in the report– Verify the RS trigger using oscilloscope– Verify the RS value using the LEDs or 7-segment display
• Take pictures and include them in your report– Group work
• State which part of the project each member worked on• Be familiar with all parts of the project and prepare for
questions
14VHDL ET062G & ET063G Lecture 7
QUESTIONS
Najeem Lawal, 2012
ABOUT FPGA / VHDL
ABOUT VGA DISPLAY / TIMING
ABOUT IMAGE SENSOR TIMING
ABOUT RANGE SENSOR
ABOUT LINE BUFFERS
ABOUT MEMORIES & COUNTERS
15VHDL ET062G & ET063G Lecture 7
END OF LECTURE 7
Najeem Lawal, 2012
OUTLINE– Line buffer diagnosis
– Creating the 3x3 window
– Computing Gx, Gy and edge output