data storage vhdl et062g & et063g lecture 4 najeem lawal 2012

Data StorageVHDL ET062G & ET063G Lecture 4

Najeem Lawal 2012

VHDL ET062G & ET063G Lecture 4

DATA STORAGE

2

OUTLINE– Counters– Shift registers– Memories– Generate– Generics– Error management– Line Buffers

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COUNTERS IN VHDL

3VHDL ET062G & ET063G Lecture 4

MODULO-256 COUNTERlibrary ieee;use ieee.std_logic_1164.ALL;use work.numeric_std.ALL;

entity modulo256 IS PORT(clk: in std_logic; cnt: buffer unsigned (7 downto 0));END modulo256;

architecture rtl of modulo256 isbegin process (clk) begin if rising_edge(clk) then cnt <= cnt +1; end ifend process;end rtl;

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SHIFT-REGISTER IN VHDL


library ieee;use ieee.std_logic_1164.ALL;

entity shift_l is port ( clk, resetn, d_in, shift_en : in std_logic; shift_out:out std_logic_vector(3 downto 0));end shift_l;

d_in shift_outshift_en

resetn

Alternative ways

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architecture rtl of shift_l is signal shift_reg: std_logic_vector(3 downto 0); begin process (clk, resetn) begin if resetn = '0' then shift_reg <= (others=>'0'); elsif clk'event and clk = '1' then if shift_en='1' then shift_reg(3 downto 1)<=shift_reg(2 downto 0); -- shift_reg <= shl(shift_reg, "1"); -- shift_reg <= shift_reg sll 1; shift_reg(0) <= d_in; end if; end if; end process;

shift_out <= shift_reg;end rtl;

MEMORIES IN VHDL


MEMORIES OCCUR AS – Registers (signals, constants, variables or ports)– RAMs– ROMs

A RAM OR ROM CAN BE DESIGNED IN TWO WAYS– Use the data-type array– Use a pre-defined macro cell for the memory

device

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MEMORIES IN VHDL


A RAM CAN BE DUAL PORT OR SINGLE PORT

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MEMORIES IN VHDL


Address contention in dual port can be solved by specifying the order of execution for example, read first or write first.

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MEMORIES IN VHDL


•data path 1 writes to and read from Port A, •data path 2 write to and read from Port B, •data path 3 implements data transfer from Port A to Port B, •data path 4 implements data transfer from Port B to Port A.

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EXAMPLE: 48 ROM IN VHDL


library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;

entity ROM is port ( address : in std_logic_vector(1 downto 0); dout : out std_logic_vector(7 downto 0));end ROM;

architecture rtl of ROM is

type rom_table is array (0 to 3) of std_logic_vector(7 downto 0); constant rom_contents : rom_table := rom_table'("00101111", "11010000", "01101010", "11101101"); begin -- rtl dout <= rom_contents(conv_integer(address));end rtl;

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EXAMPLE #1: RAM IN VHDL


Define existing RAM module existing in a library

architecture rtl of rmodul is

component RAM4_8 port ( din: in std_logic_vector(7 downto 0), address0, address1, we : in std_logic; dout : out std_logic_vector(7 downto 0); end component; begin -- rtl ram1: RAM4_8 port map ( din => d, address0 => a0, address1 => a1, we => we, dout => q); end rtl;

din dout

address0

address1we

RAM4_8din

a0

a1we

q

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library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;

entity ram32_16 is port ( addr : in std_logic_vector(4 downto 0); clk, we_n : in std_logic; din : in std_logic_vector(15 downto 0); dout : out std_logic_vector(15 downto 0));end ram32_16;

din doutaddr

we_n

RAM32_16

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Define an matrix

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architecture rtl of ram32_16 is

type ram_type is array (31 downto 0) of std_logic_vector(15 downto 0); signal ram_array : ram_type;

begin process(clk) begin if clk'event and clk='1' then if we_n='0' then ram_array(conv_integer(addr)) <= din; end if; end if; end process;

dout <= ram_array(conv_integer(addr));end rtl;

GENERATE COMMAND IN VHDL


If the same component is to be instantiated many time in the same architecture, the generate command is the most effective approach

Syntax:

<g_Label> : FOR <loop_iteration> Generate<i_label >: <entity_name> port map (

<port-association-list>

);

End generate <g_Label>;

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Entity adder_4bit is

Port (a, b : in std_logic_vector(3 donwto 0);

cin : in std_logic;

sum : out std_logic_vector(3 downto 0);

cout : out std_logic);

End entity adder_4bit;

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USING GENERATE TO CREATE A 4-BIT ADDER FROM 1-BIT ADDER



Architecture rtl of Adder_4bit is

component adder_1bit

port(a,b,cin : in std_logic;

sum, cout : out std_logic);

end component;

Signal c_chain : std_logic_vector(4 downto 0);

Begin

c_chain(0) <= cin;

cout <= c_chain(4);

gen : for i in 0 to 3 generate

u : adder_1bit port map (a(i), b(i), c_chain(i), sum(i), c_chain(i+1));

End architecture rtl;

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.....

Begin

c_chain(0) <= cin;

cout <= c_chain(4);

gen : for i in 0 to 3 generate

u : adder_1bit

port map (

a <=a(i),

b <=b(i),

cin <= c_chain(i),

sum <= sum(i),

cout <= c_chain(i+1));


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GENERIC COMMAND


GENERICSThe generic statement declares constants that are analogous to arguments in functions in procedural programming.

These constants are set in the module that is hierarchically above the current one.

If they are not set, they take the default value that you give it.

Generic declarations are optional and their mapping.

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GENERIC COMMAND


GENERICS Are used for – Timing: delays – Sizing: bus width– Limits: counter range

SYNTAX:<GENERIC_NAME>: TYPE [:= <INITIAL_VALUE>];

EXAMPLES:BUS_WIDTH: INTEGER := 8;MY_BOOLEAN: BOOLEAN := FALSE;DELAY: TIME :=5NS

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GENERIC & GENERATE COMMAND


HOW CAN WE CREATE A 64-BIT ADDEROR 128-BIT OR N-BIT ADDER?

WHERE N > 0.

HINTS: GENERICS AND GENERATE

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Entity adder_Nbit is

Generic (N : integer := 100);

Port (a, b : in std_logic_vector(N - 1 donwto 0);

cin : in std_logic;

sum : out std_logic_vector(N - 1 downto 0);

cout : out std_logic);

End entity adder_Nbit;

Architecture rtl of Adder_Nbit is

component adder_1bit

port(a,b,cin : in std_logic;

sum, cout : out std_logic);

end component;

Signal c_chain : std_logic_vector(4 downto 0); --.....

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--.....

Begin

c_chain(0) <= cin;

cout <= c_chain(N);

gen : for i in 0 to (N – 1) generate

u : adder_1bit

port map (

a <=a(i),

b <=b(i),

cin <= c_chain(i),

sum <= sum(i),

cout <= c_chain(i+1));


By combining generic and generate, it is possible to achieve a compact and variable number of construction. Here is an example of 100 bit adder.

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ERROR MANAGEMENT IN VHDL


Assert statement Used to test constraint during simulation

functional constraint

time constraint

If the condition is satisfied i.e. confirmed or asserted

simulation continues

If condition (functional or time) is not satisfied

- print a report

- specify the severity of the condition

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Assert statement

Syntax:

Assert <condition>

Report <message>

Severity <error_level> ;

Message and Error Level are displayed in the simulator console as text.

Assert statements can be both sequential and concurrent statements.

Assert statements should only be in the test-benches because there are not synthesizable.

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Assert <condition>

assert in /= '0'

assert in1 /= '0' AND in2 = '1'

assert now = 200 ns

Report <message>

report “Values of input in1 and in2 are invalid!”

report “Simulation completed”

report “Output x is out of range”

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Severity <error_level>

severity

Note

Warning

Error

Failure

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Entity assert_ex is

port ( a,b : in std_logic;

q : out std_logic);

end entity assert_ex;

architecture ex of assert_ex is

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architecture ex of assert_ex is

begin

assert a /= '1' or b /= '1'

report “a='1' and b='1' at the same time!”

severity Warning;

P1 : process(a,b)

begin

if a ='1' and b = '1' then

assert false

report “a='1' and b='1'”;

end if

end process P1;

end architecture ex;

LINE BUFFERS


– Memories used to buffer a set of repitive data– Implemented as a read first then write block RAM– A First-In-First-Out shift register (FIFO) that can be

implemented as a circular buffer– An example of a modulo-8 data set memory buffer

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RAM Location

Data_in

WE

Clock

Address

Data_out

Pn-8

Current pointer Position

Incremented at every clock cycle.

Firstly, read pixel Pn-8

Pn-7

Pn-6

Pn-5

Pn-4 Pn-3

Pn-2

Pn-1

After read, write pixel Pn

LINE BUFFERS


entity linebuffer isgeneric (

ADDR_WIDTH : integer := 10;DATA_WIDTH : integer := 8;WINDOW_SIZE : integer := 3;ROW_BITS : integer := 9;COL_BITS : integer := 10;NO_OF_ROWS : integer := 480;NO_OF_COLS : integer := 752 );

port(clk : in std_logic;fsynch_in : in std_logic;rsynch_in : in std_logic;pdata_in : in std_logic_vector(DATA_WIDTH-1

downto 0);fsynch_out : out std_logic;rsynch_out : out std_logic;pdata_out1 : out std_logic_vector(DATA_WIDTH

-1 downto 0);pdata_out2 : out std_logic_vector(DATA_WIDTH








-1 downto 0) );end linebuffer;

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LINE BUFFERS


entity linebuffer isgeneric (

ADDR_WIDTH : integer := 10;

DATA_WIDTH : integer := 8;

WINDOW_SIZE : integer := 3;

ROW_BITS : integer := 9;

COL_BITS : integer := 10;

NO_OF_ROWS : integer := 480;

NO_OF_COLS : integer := 752 );

port( ---..... );end linebuffer;

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LINE BUFFERS


entity linebuffer isgeneric (----....);port(

clk : in std_logic;fsynch_in : in std_logic;rsynch_in : in std_logic;pdata_in : in std_logic_vector(DATA_WIDTH-

1 downto 0);fsynch_out : out std_logic;rsynch_out : out std_logic;pdata_out1 : out std_logic_vector(DATA_WIDTH









-1 downto 0) );end linebuffer;

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QUESTIONS

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ABOUT FPGA / VHDLABOUT VGA DISPLAY / TIMINGABOUT IMAGE SENSOR TIMINGABOUT RANGE SENSORABOUT LINE BUFFERSABOUT MEMORIES & COUNTERS


END OF LECTURE 4

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OUTLINE– Counters– Shift registers– Memories– Generate– Generics– Error management– Line Buffers

data storage vhdl et062g & et063g lecture 4 najeem lawal 2012

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