design guidelines for emc of components. 2 summary 1. which problems? 2. emc guidelines at pcb level...
TRANSCRIPT
2
Summary
1. Which problems?
2. EMC Guidelines at PCB level
3. IC Guidelines for low emission
4. IC Guidelines for low immunity
5. Starcore case study
19 Apr 2023
3
EMC management
EMC should be taken into account at early design stage…
K. Armstrong, Advanced PCB design and layout for EMC
19 Apr 2023
4
EMC guidelines
Which problems? Know your enemy
Integrated circuits / electronic applications
Signal integrity (SI)
Power integrity (PI)
Conducted emission (CE)
Radiated emission (RE)
Conducted immunity (CI)
Radiated immunity (RI)
ESD, EFT, EOS
19 Apr 2023
Origin of effects on both lines ?
EMC guidelines at PCB level
Signal integrity (SI) issue
Example: voltage measurement at 3 terminals of two 20 cm long
parallel PCB tracks.
The first line is excited by a pulse generator, the second is
terminated by two resistive loads.
EMC guidelines at PCB level
Signal integrity (SI) issue
Let’s consider a transmission along two conductors = 2-conductor
transmission line. Let’s suppose an homogeneous lossless line
Equivalent model:
Interconnect+ + + + + +
- - - - - - -
I(z,t)
I(z,t)
VG
ZG
ZL
Transmission line LoadThevenin generator
z0 L
v
ztV
Zv
ztV
ZtzI
v
ztV
v
ztVtzV
CC
11,
, The voltage and current on each point
of the line is superposition of a
forward and backward voltage,
travelling in opposite directions.
11
lc
v
c
lZC
6
EMC guidelines at PCB level
Signal integrity (SI) issue The voltage at each point of the line depends on the reflection coefficient at
each line terminals:
CL
CLL ZZ
ZZ
v
LtV
v
LtV
Transient behavior of voltage at each line terminals:
LtLVv
LtV
v
LtVtLzV
1,,
CG
CGG ZZ
ZZ
tV
tV
GtVtVtVtzV 1,0,0At generator side (input):
At generator side (input):
Complex transient behavior related to the reflection coefficient on each extremities and transmission line discontinuities
7 19 Apr 2023
EMC guidelines at PCB level
Signal integrity (SI) issue Analysis of the round-trip period of the wave along the line
Source LoadTime (ns)
0
L/v
LG
0V
VVV L 44.101
LL VV 10
VL(0)=0V
2L/v
GCG
C VZZ
ZVtVtV
0,0,0
GL
G
VtV
VVtV
11,0
1,0
0
10
8
Vsource
t0
0V
GLV 110
2L/v 4L/v
Overshoot / Undershoot
Vload
t0 L/v 3L/v
LV 10
Overshoot / Undershoot
19 Apr 2023
Zc ; Tp
t
VL or VG
Vdd
0
VIH
VIL
VL
Overshoot
Undershoot Undetermined level
Longer setting time
Criterion for SI issue:
if Tr is the rising or falling time of a signal, SI issues due to the propagation of the EM wave along the transmission line arise if:
Pr TT Ringing
9
EMC guidelines at PCB level
Signal integrity (SI) issue
VG
19 Apr 2023
10
EMC guidelines at PCB level
Signal integrity (SI) issue
19 Apr 2023
K. Armstrong, Advanced PCB design and layout for EMC
Cancel reflection coefficient at each line terminals by impedance matching
CGG
CLL
ZZ
ZZ
0
0 Impedance matching of a uniform transmission line with constant characteristic impedance Zc.
Rs : serial resistor= Rdriver - Zc
ZcRs
Rpd
Rpd : pull down resistor = Zc
Zc
Rpd
Ct
Vcc
EMC guidelines at PCB level
Ensuring Signal integrity – Rule 1
Practical designs for a digital transmission:
19 Apr 202311
12
Control the characteristic impedance of (2-conductor) transmission line (PCB track, package) avoid line discontinuities
EMC guidelines at PCB level
Ensuring Signal integrity – Rule 2
Microstrip line configuration:
h
W
I εr
Ideal ground plane
tW
hZ
eff
C 8.0
98.5ln
414.1
87
t
67.0475.034.3/ rp mmpsT
Is it better to use wide or narrow trace ?
19 Apr 2023
13
Ensure a controlled and short return current path.
EMC guidelines at PCB level
Ensuring Signal integrity – Rule 3
Place a full ground plane in microstrip line.
Avoid slot in return plane (e.g. ground plane)
Keep a symmetry (avoid unbalance in the return current path)
Low frequency behavior
I
Microstrip line Ground plane
Return current
I
High frequency behavior
Microstrip line Ground plane
Return current
CORRECT BAD
I
Microstrip line
Ground plane with a slot
Return current
19 Apr 2023
14
From ECST Broadcheck – www.cst.com
EMC guidelines at PCB level
Ensuring Signal integrity – Rule 3 Example: a microstrip line routed over 2 separated power planes.
SI design rule violation
19 Apr 2023
EMC guidelines at PCB level
Signal integrity (SI) - Crosstalk
h
WI1
εr
W
I2
Trace 1 (emitter) Trace 2 (victim)
V
d
I1’Crosstalk (near-field
coupling)
Let’s consider 2 traces separated by a distance d.
“Normal” return current path
Parasitic return current path
Emitter trace
Victim trace
VE
RSRL
RNE RFE
Near endFar end
VNE VFE
CM LM
Capacitive coupling
Inductive coupling
Equivalent model:
15 19 Apr 2023
SLNEFE
MMFELNE
S
NE
RRRR
LCRRRj
V
V
SLNEFE
MMNELFE
S
FE
RRRR
LCRRRj
V
V
f
dBVVorV FENE
Validity of quasi-static approximation
EMC guidelines at PCB level
Signal integrity (SI) - Crosstalk Low frequency model (quasi-static approximation propagation effects
neglected)
VNE
VFE
16 19 Apr 2023
(εr = 4.5)
Increase the isolation between emitter and victim lines
EMC guidelines at PCB level
Ensuring Signal integrity – Rule 4
Increase the distance between traces (rule 3 W = “the separation between
traces must be 3 times the width of the trace as measured from centerline
to centerline of two adjacent traces”)
Substrateground
h
t
W < 3W
W
17 19 Apr 2023
EMC guidelines at PCB level
Power integrity (PI) issue – Power Distribution Network
18
Voltage converter / regulator
Power source
Ground reference
Vdd
Vss
PCB – Power / ground plane
HF capacitor (ceramic)
1 µF – 10 mF 100 nF – 1 nF
Ferrite
1 nF
Package and IC
Bulk capacitor (Low frequency)
Transistors, gates, interconnects
19 Apr 2023
Noisy Integrated circuit
Power supply source (regulator, DC-DC converter)
PDN
Vss
Vdd
i(t)
Circuit
PDN
ΔVdd
ΔVssPower supply bounce t
iLiRV PDNPDN
t
iLiRV PDNPDN
Delta-I noise
EMC guidelines at PCB level
Power integrity (PI) issue
19 19 Apr 2023
Switching
High frequency contribution
Low frequency contribution
SwitchingSwitching
EMC guidelines at PCB level
Power integrity (PI) issue Example: on-chip measurement of the power supply voltage fluctuation
of a digital circuit
Noise with a large frequency content and some major resonance modes
20 19 Apr 2023
EMC guidelines at PCB level
Power integrity (PI) issue Equivalent model of a PDN (the most basic model…)
fIfZfV ICPDNdd IIC
CircuitVdd
gnd
ZPDN
PDN
ΔVdd
Power supply voltage bounce:
Ensuring power integrity relies on the control of a low impedance of the PDN.
A target impedance ZT can be defined as a design objective:
average
ddT I
VZ max
ZPDN
Frequency
Zt
Target frequency range21 19 Apr 2023
EMC guidelines at PCB level
Ensuring Power integrity – Rule 1
22
Reduce interconnect parasitic (mainly inductance) of power and ground connections
Use traces as wide as possible for Vdd and Vss connections
i.e. use power and ground planes
Be careful of the common impedance of Vdd and Vss connections (finite
impedance, even for ground plane):
Régulateur Circuit 1 Circuit 2 Circuit 3VDD
VSS
VDD VDD
VSS VSS
I3I2+ I3I1+I2+ I3
L3L2L1
dt
dIdIdILV 321
11
dt
dIdILVV 32
212
dt
dILVV 3
323
Régulateur Circuit 1 Circuit 2 Circuit 3VDD
VSS
VDD VDD
VSS VSS
I3L3L2L1
Plan de masse
I2I1
Single point grounding with serial circuits
Direct grounding to a reference ground plane
19 Apr 2023
Voltage regulator IC
PCB
Decoupling capacitor
Vdd
Vss
Vdd
Vss
Voltage bounce v(t)
i(t)
Principle: Local charge tank
In time domain
dt
tdvCti dec
Large capacitors react rapidly to charge demand.
In frequency domain
fIZfV Cdec
Large capacitors reduce PDN impedance.
EMC guidelines at PCB level
Ensuring Power integrity – Rule 2
Add decoupling capacitor to reduce power supply bounce as close as possible from noise source (current demand)
23 19 Apr 2023
Effect of on-board capacitors:
Parasitic emission (dBµV)
-1001020304050607080
1 10 100 1000Frequency (MHz)
Customer’s specification
No decoupling
No decoupling
10 – 15 dB
10-100 nF decoupling
10-100 nF decoupling
Efficient on one decadeEfficient on one decade
X7R 50 V ceramic capacitors
Exemple : C = 100 µF, ESR = 80 mΩ, ESL = 1 nH
100 µF electrolytic capacitor
EMC guidelines at PCB level
Ensuring Power integrity – Rule 2
24 19 Apr 2023
maxdd
rdec V
tIC
EMC guidelines at PCB level
Ensuring Power integrity – How choosing decoupling capacitor
If ideal capacitor, only one decoupling capacitor would be enough:
• Cdec: the minimum capacitor able to provide a current to the circuit without any large voltage fluctuations.
• ΔVddmax : max allowed voltage fluctuation
• ΔI : current peak absorbed by the circuit
• tr : rise time of the current peak
However, due to the parasitic elements associated to decoupling
capacitors, its efficiency frequency range is limited or it can not respond
to rapid current demand.
It is necessary to place several decoupling capacitors in parallel to
increase the efficiency frequency range of the decoupling.
25 19 Apr 2023
EMC guidelines at PCB level
Ensuring Power integrity – How choosing decoupling capacitor
Methodology to optimize the choice of decoupling capacitors:
Board model Regulator model Circuit(s) model
Capacitors model
PDN without decoupling model
Define freq. range of decoupling Fmin Fmax
Add capacitor(s) and/or change capa values
If ZPDN(f) > Zt for f in [Fmin;Fmax]
Compute ZPDN
Power integrity OK – Decoupling budget
Define Zt
NO
YES
19 Apr 2023
EMC guidelines at PCB level
Ensuring Power integrity – How choosing decoupling capacitor
Example: decoupling of a 16 bit microcontroller (dspic33F).
The circuit produces a significant amount of noise over the range 1 – 500 MHz.
We select Zt = 2 Ω.
IC Current (1 Ω probe) Z PDN (VNA measurement)
Board + IC without decap
With 6×100 nF decap
ZT
27 19 Apr 2023
EMC guidelines at PCB level
28
Ensuring Power integrity – Anti-resonance issue
What happens if 2 “real” capacitors are placed in parallel ?
Fantires
Fantires =
19 Apr 2023
29
EMC guidelines at PCB level
Ensuring Power integrity – Anti-resonance issue
Example: power integrity of a 16 bit microcontroller (dspic33F) with 6×100 nF
X7R decoupling capacitor.
The PDN impedance measurement shows an anti-resonance at 162 MHz
Fantires
PDN equivalent model
What is the cause of this anti-resonance ?
19 Apr 2023
30
EMC guidelines at PCB level
Ensuring Power integrity – Anti-resonance issue
Example: power integrity of a 16 bit microcontroller (dspic33F) with 6×100 nF
X7R decoupling capacitor.
Measurement of power supply voltage in time domain (16 I/O pads switch
simultaneously).
19 Apr 2023
31
EMC guidelines at PCB level
Ensuring Immunity – Anti-resonance issue
Example: power integrity of a 16 bit microcontroller (dspic33F) with 6×100 nF
X7R decoupling capacitor.
Measurement of conducted immunity (harmonic signal coupled on power
supply plane according to DPI standard). At each harmonic frequency, the
disturbance power is increased until a circuit failure arises.
Max. Power
EMC guidelines at PCB level
Radiated emission – basic mechanisms
32
Radiated emissions come from interconnects excited by a transient
current or voltage. They become parasitic antennas.
Two basic radiated mechanisms:
Circuit
VDDVSS
I
Magnetic field
Surface S
CircuitClock
Electric field
High Z loadLength l
Loop antenna (magnetic)
Low impedance load (power supply, I/O loaded by low impedance
H field proportional to surface S
Dipole antenna (electric)
high impedance load (I/O loaded by high impedance)
E field proportional to length l
19 Apr 2023
EMC guidelines at PCB level
Radiated emission – basic mechanisms Differential vs. common radiated mode.
Common mode appears when the return current path is not perfectly defined.
Interco 1
Interco 2
I1
I2
1
2
Id
Id
1
2
Ic
Ic
Decomposition in 2 distinct propagation
modes
Differential mode
Common mode
2
2
21
21
III
III
C
D
DC
CD
III
III
2
1
If I1 ≠ I2
33 19 Apr 2023
EMC guidelines at PCB level
Radiated emission – basic mechanisms Comparison of common and differential radiated mode.
Let’s consider electrically 2 short parallel interconnects (length L << λ):
34
DD Ir
fdLE
214
max
..10.316.1
CC Ir
fLE
.10.257.1 6
max
L: interconnect length
d: interconnect separation
f: frequency of excitation current
r: distance between E field measurement point and interconnect centers
ID and IC: differential and common mode currents
ED and EC: differential and common mode radiation (E field)
L=10 cm, d=2 mm, r = 1 m, ID = 50 mA, IC = 5 mA
Main conclusions about radiation mechanisms ?
19 Apr 2023
EMC guidelines at PCB level
Reducing radiated emission – Rule 1
35
Reduce parasitic antenna (length or surface) to reduce differntial and common mode radiation
CircuitVDD
VSSDecoupling capacitor
CircuitVDD
VSSId
Id
Identify current loops on PCB and reduce their surface.
Place decoupling capacitors as close as possible to IC pins.
Use power or ground plane to reduce current loop surface.
Reduce the length of interconnects which carry high frequency signals.
Decoupling capacitor
Large loop High radiated differential mode
Smaller loop Reduced radiated differential mode
19 Apr 2023
EMC guidelines at PCB level
36
Reducing radiated emission – Rule 2
Control the current return path to reduce common mode
CircuitVDD
VSS1
IVdd
Power
GNDIVss1
IVSS2
VSS2
Example 1: one Vdd pin but two Vss pins
Example 2: one differential output buffer with a non
symmetrical routing
Differential buffer
D+
D-
I+
I-
Ic
I+ ≠ I-
IVdd = IVSS1+IVSS2
Parasitic coupling
19 Apr 2023
37
EMC guidelines at PCB level
Reducing radiated emission – Rule 3
Use a “good” ground plane(s) to shield noisy interconnects
Use coplanar or stripline configuration to shield noisy interconnect.
A “good” reference plane is equipotential at any point !
Connect two reference plane witth same potential by vias regular interval
less than λ/20 !
line
Ref plane
Ref plane
Stripline configurationCorrect connection between
two planes with same potential
GND
GND
20
d
via
19 Apr 2023
38
EMC guidelines at PCB level
Radiated emission – Case study Basic digital applications routed on a 2 layer board with the auto-router
function of the board design tool. Only one 100 nF decoupling capacitor
for all the application.
Measurement of radiated emission in TEM cell.
Limit CISPR25
EMC guidelines at PCB level
39
Radiated emission – Case study Numerous EMC design rules violation: large power-ground loops, long
fast clock interconnect, return path not ensured by a ground plane…
Change the placement & routing of the board by starting to place
Vdd/Vss and fast clock, add a ground plane on both side.
Design rule violation examples:
“High speed” clock source
Equivalent surface of fast clock interconnect
Vdd connection
Vss connection
CMOS inverter
Large loop
EMC guidelines at PCB level
40
Radiated emission – Case study
Top layer
Bottom layer
Effect of placement & Routing improvement (still one 100 nF decoupling capacitor)
-30 dB
19 Apr 2023
EMC guidelines at PCB level
41
Radiated emission – Case study
Effect of GND vias densityEffect of decoupling capacitors
(one capacitor per circuit)
≈ -5 dB
+ or – effect depending on freq.
19 Apr 2023
EMC guidelines at PCB level
Summary
EMC can be improved at PCB level, mainly by an adequate placement and routing of rapid signals, power and ground references.
Several EMC issues have the same root causes one EMC design rule can solve several problems.
The modeling is important to understand the problem and optimize solution.
An accurate IC model is mandatory to manage EMC at PCB level.
42 19 Apr 2023
43
Lead: L=0.6nH/mm
Bonding: L=1nH/mm
Golden Rules for Low Emission
• Inductance is a major source of resonance• Each conductor acts as an inductance• Ground plane modifies inductance value (worst case is far from ground)
A) Use shortest interconnection to reduce the serial inductance
Rule 1: Power supply routing strategy
Reducing inductance decreases SSN !!
Reducing inductance decreases SSN !!
19 Apr 2023
44
A) Use shortest interconnection to reduce the serial inductance
Leadframe package:
L up to 10nH
Rule 1: Power supply routing strategy
PCB
Long leads
Die of the IC
Close from ground
bonding
Die of the ICShort leads
ballsFlip chip package:
L up to 3nH
Far from ground
Requirements for high speed microprocessors : L < 50 pH !Requirements for high speed microprocessors : L < 50 pH !
Golden Rules for Low Emission
19 Apr 2023
45
Correct
Fail
9 I/O ports
Golden Rules for Low Emission
B) Place enough supply pairs: Use One pair (VDD/VSS) for 10 IOs
Rule 1: Power supply routing strategy
19 Apr 2023
46
Current density simulation
Golden Rules for Low Emission
C) Place supply pairs close to noisy blocks
Rule 1: Power supply routing strategy
Layout view
Digital core
Memory PLL
VDD / VSS
VDD / VSS
VDD / VSS
19 Apr 2023
47
•to increase decoupling capacitance that reduces fluctuations•to reduce current loops that provoke magnetic field
Golden Rules for Low Emission
D) Place VSS and VDD pins as close as possible
Rule 1: Power supply routing strategy
Current loop
EM field
Added contributions
currentsDie
LeadLead
current
EM wave
current
EM wave
Reduced contributions
19 Apr 2023
48
Case 1 : Infineon Tricore Case 2 : virtex II
Golden Rules for Low Emission
Rule 1: Power supply routing strategy
Worst casenot enough supply pairs, bad distribution & dissymmetry
Not idealNot enough supply for IOs : (core emission is lower than IO one)
Case study 2:
19 Apr 2023
49
courtesy of Dr. Howard Johnson, "BGA Crosstalk", www.sigcon.com
Golden Rules for Low Emission
2 FPGA , same power supply, same IO drive, same characteristicsSupply strategy very different !
Case study 2:
Rule 1: Power supply routing strategy
• More Supply pairs for IOs
• Better distribution
• More Supply pairs for IOs
• Better distribution
19 Apr 2023
50
courtesy of Dr. Howard Johnson, "BGA Crosstalk", www.sigcon.com
Golden Rules for Low Emission
Case 1: low emission due to
a large number of supply
pairs well distributed
Case 1: low emission due to
a large number of supply
pairs well distributed
Case 2: higher emission
level (5 times higher)
Case 2: higher emission
level (5 times higher)
Rule 1: Power supply routing strategy
19 Apr 2023
51
Golden Rules for Low Emission
Rule 1: Power supply routing strategy
Case study 3: conducted (150 ohms probe placed on Vdd) and radiated (TEM cell) emission from a microcontroller mounted in either & 208-BGA or a 324-BGA.
208-BGA (31 Vdd/Vss pairs)
324-BGA (49 Vdd/Vss pairs)
Larger conducted emission from 208-BGA (less power supply pins)
Larger radiated emission from 324-BGA (larger interconnects)
E. Rogard and al., "Characterization and Modelling of Parasitic Emission of a 32-bit Automotive Microcontroller Mounted on 2 Types of BGA", IEEE EMC Symposium Austin, Texas, USA 2009
19 Apr 2023
52
Golden Rules for Low Emission
Rule 2: Add decoupling capacitance
On chip decoupling capacitance versus technology and complexity:
Devices on
chip
Intrinsic on-chip supply
capacitance
100K 1M 10M
10pF
100pF
1.0nF
10nF
100M 1G
100nF
0.35µm
0.18µm90nm
65nm
Example: in 65nm technology, for a 200 Million devices on chip the intrinsic capacitance is 10nF
19 Apr 2023
53
Golden Rules for Low Emission
Rule 2: Add decoupling capacitance
Effect of on chip capacitance: smooth on-chip voltage fluctuation and reduce conducted
emission.
Example: two versions of a CMOS 90 nm digital core, Vdd = 1.2 V, same mounting board: Core 1: No on-chip decoupling capacitance
Core 2 : Add 100 pF MIM decoupling capacitance
A. Boyer (LAAS-CNRS)
59 mV
27 mV
On-chip voltage measurement 1 ohm conducted measurement
19 Apr 2023
54
Golden Rules for Low Emission
Rule 3: Reduce I/O noise
f
Emission level
1/Tr11/Tr2
Reduction of the fast rate of I/O current.
Minimize the number of simultaneous switching lines (bus coding)
Reduce di/dt of I/O by controlling slew rate and drive
SR & Drive control
Tr1 Tr2
19 Apr 2023
55
Golden Rules for Low Emission
Example: I/O buffer with Drive and slew rate control options: Full or
reduced drive, high and limited slew rate.
Impact of I/O options on timing waveform:
Rise time = 2 ns Rise time = 8.6 ns
Full Drive – High slew rate Reduced Drive – High slew rate
Rule 3: Reduce I/O noise
19 Apr 2023
56
Golden Rules for Low Emission
Impact of I/O options on timing waveform and output drive current:
What is the more « emissive » option ? The less emissive ?
Rule 3: Reduce I/O noise
19 Apr 2023
57
Golden Rules for Low Emission
Comparison of conducted emission (1 ohm method)
Rule 3: Reduce I/O noise
58
Golden Rules for Low Emission
Comparison of conducted emission (1 ohm method)
Rule 3: Reduce I/O noise
19 Apr 2023
59
Origin of electromagnetic emission
The switching of output buffer contributes to a large part of conducted and radiated emission. When several I/O switches simultaneously, their contributions tend to add: Simultaneous Switching Noise.
Minimize the number of simultaneous switching lines (bus coding)
Effect of the number of simultaneous switching buffers
Rule 4: Reduce SSN
16 output buffers, two different switching sequences.
19 Apr 2023
60
Reduction or spreading of clock harmonics by frequency modulation.
Example : sinus clock at Fc = 100 MHz vs modulated sinus clock:
tmdttS
tF
dfttS
MCFM
MM
CFM
coscos
coscos
Spread spectrum over B
Reduction of narrow band RF energy
Golden Rules for Low Emission
Rule 5: Reduce clock noise – Spread Spectrum Frequency Modulation
Carrier frequency Fc = 100 MHz
Modulation frequency FM = 1 MHz
Frequency excursion dF = +/- 5 MHz
Modulation index md = 5
Carson rule: 12 mod mdFB
19 Apr 2023
61
Golden Rules for Low Emission
In practice, a triangular signal is used as modulating signal.
Clock in
Tc
Modulantt
Clock out
Tc+/-dt
Frequency Modulated clock
Freq. modulation ΔF
Unmodulated clock
Modulated clock
dP
B
TMod
RBW
BdBdP log10
+/- dt
Carson rule applies also:
12 mod mdFB
If Fmod < RBW (reso BW of the receiver):
Rule 5: Reduce clock noise – Spread Spectrum Frequency Modulation
Real case study: FM-PLL block of the 32 bit microcontroller MPC 5604B from
Freescale. PLL frequency set at 64 MHz.
Measurement of near-field emission above the circuit.
Modulation parameters: triangular waveform, FM = 100 KHz, dF = +/- 0.64 MHz.
Receiver bandwidth = 1 KHz.
Golden Rules for Low Emission
10 dB
Predicted value of spreading reduction ?
A. Boyer (LAAS-CNRS)
62
Rule 5: Reduce clock noise – Spread Spectrum Frequency Modulation
19 Apr 2023
Golden Rules for Low Emission
Real case study: Effect on emission spectrum
Modulation parameters: triangular waveform, FM = 100 KHz, dF = +/- 0.64 MHz.
Receiver bandwidth = 10 KHz.
A. Boyer (LAAS-CNRS)
Average reduction of 64 MHz harmonics = 10.6 dB
63
Rule 5: Reduce clock noise – Spread Spectrum Frequency Modulation
19 Apr 2023
Golden Rules for Low Emission
The reduction amount is dependent of the receiver bandwidth RBW if the
modulation frequency is less than RBW.
Example: FM = 50 KHz, dF = +/- 1.28 MHz.
RBW = 1 KHz vs. RBW = 100 KHz.
3 dB
A. Boyer (LAAS-CNRS)
64
Rule 5: Reduce clock noise – Spread Spectrum Frequency Modulation
19 Apr 2023
65
Work done at Eseo France (Ali ALAELDINE)
Immunity level (dBm)
Frequency
Golden Rules for Low susceptibility
Rule 1: Decoupling capacitance is also good for immunity
No rules to reduce susceptibility
Substrate isolation
Decoupling capacitanc
e
• DPI aggression of a digital core
• Reuse of low emission design rules
for susceptibility
• Efficiency of on-chip decoupling
combined with resistive supply path
• DPI aggression of a digital core
• Reuse of low emission design rules
for susceptibility
• Efficiency of on-chip decoupling
combined with resistive supply path
19 Apr 2023
66
Analog
Standardcells
Noisy blocks
Far fromnoisy blocks
Bulk isolation
Separate supply
Why ? • To reduce the propagation of
switching noise inside the chip• To reduce the disturbance of
sensitive blocks by noisy blocks (auto-susceptibility)
How ?• by separate voltage supply• by substrate isolation• by increasing separation between
sensitive blocks• By reducing crosstalk and
parasitic coupling at package level
Golden Rules for Low susceptibility
Rule 2: Isolate Noisy blocks
19 Apr 2023
67
Golden Rules for Low susceptibility
separate supply
Rule 2: Isolate Noisy blocks
substrate isolation
increasing separation between sensitive blocks
From Prof. Adrijan Barić , FER Zagreb EMC Compo 2011
19 Apr 2023
68
Golden Rules for Low susceptibility
Rule 3: Improve noise immunity of IOs
• Add Schmitt trigger on digital input buffer
• Use differential structures for analog and digital IO to reject common mode noise
Schmitt trigger2 dB
19 Apr 2023
69 19 Apr 2023
Case study – Starcore floorplan improvement
Design guidelines for EMC of IC
The Starcore is 16-bit micro-controller used in automotive industry:
• 16 bit MPU with 16 MHz external quartz, on-chip PLL providing internal 133 MHz operating clock
• 128 Kb RAM, 3 general purpose ports (A, B, C, 8 bits), 4 analog inputs 12 bits, CAN interface
SIGNAL Description
VDD Positive supply
VSS Logic Ground
VDD_OSC Oscillator supply
VSS_OSC Oscillator ground
PA[0..7] Data port A (programmable drive)
PB[0..7] Data port B (programmable drive)
PC[0..7] Data port C (programmable drive) external 66MHz data/address
ADC In[0..3] 4 analog inputs (12 bit resolution)
CAN Tx CAN interface (high power, 1MHz)
CAN Rx CAN interface (high power, 1MHz)
XTL_1, XTL_2 Quartz oscillator 16MHz
CAPA PLL external capacitance
RESET Reset microcontroller
70
Case study – Starcore floorplan improvement
Design guidelines for EMC of IC
Several tests were conducted by the customer and a huge list of problems appeared. Now that you learnt some rules about low emission floor-planning, you are probably able to understand the origin of the listed problems. In this case study, you act as an EMC engineer which is called urgently to improve the floor-planning of the chip (without changing the chip layout which would cost too much), in order to save the contract.
Warning:
• Reliability problems (over current) on pin
• 23 Ground bounce: voltage drop around 500mV (spec: 50mV)
• VDD bounce: voltage drop around 700mV (spec 50mV)
• ADC measured resolution: 6 bits (required 10 bits)
• CAN bus erratic problems
• Oscillator PLL sometimes do not lock
71
Case study – Starcore floorplan improvement
Design guidelines for EMC of IC
The first action is to identify which block is a noisy block, which part is a sensitive part.
SIGNAL Description Emission Susceptibility Remark Assign to
VDD Positive supply + A l’opposé, 1 seule paire, sur les diagonales
VSS Logic Ground +
VDD_OSC Oscillator supply + + Réassigner broches Osc près Bloc Osc.
VSS_OSC Oscillator ground + + à éloigner du CAN
PA[0..7]Data port A (programmable drive)
PB[0..7]Data port B (programmable drive)
PC[0..7]Data port C (programmable drive) external 66MHz data/address
Mettre une paire Vdd/Vss à proximité
ADC In[0..3]4 analog inputs (12 bit resolution)
+++
Paire alim dédiée VddA/VssA, repositionner près du bloc ADC
CAN TxCAN interface (high power, 1MHz)
CAN RxCAN interface (high power, 1MHz)
XTL_1, XTL_2 Quartz oscillator 16MHz
CAPA PLL external capacitance
RESET Reset microcontroller - - Mettre dans un coin
72
Case study – Starcore floorplan improvement
Design guidelines for EMC of IC
Then you can try to assign the various I/os to specific pins. Place your solution here. Several good solutions exist. Was this an imaginary
scenario? No! Most of the contents of this course come from severe ignorance of EMC problems, that are found at the end of the design cycle and may induce losses of millions of Euro.