design for testability

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,, VLSI Testing and DFT

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Design For Testability


• No single methodology solves all testing problems.

• No single DFT techniqne is effective for all kinds of circuits.

DFT techniqnes:

1. Ad hoc techniqnes.

2. Structured techniqnes:

a. Full scan.

b. Partial scan.

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Ad Hoc DFT Guidelines

1. Employ test points to enhance controllability & observability (testpoints: control points (CPs) & observation points (OPs)).

C1C2

M C3

CP2CP1

OP

CP3CP4

.

.

. ...

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2. Partition large circuits into smaller subcircuits to reduce test generation cost (using MUXes and/or scan chains).

.

C1

M S0 1

T1T2

S10

10

SM

C2

S M1 0

M

Mode T2T1

NormalTest C1

Test C2

0 00 11 0


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3. Design circuits to be easily initializable.

4. Disable internal one-shots (monostables) during test

(due to difficulty for tester to remain synchronized

with DUT).

5. Disable internal oscillators and clocks during test.


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6. Partition large counters into smaller ones.

7. Avoid the use of redundant logic.

8. Provide logic to break global feedback paths.


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9. Keep analog and digital circuits physically apart.

10. Avoid the use of asynchronous logic.

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11. Avoid diagnostic ambiguity groups such as wired-

OR/wired-AND junctions and highfanout nodes.

12. Consider tester requirements (pin limitation,

tristating, etc.)

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• High fault coverage not guaranteed.

• Manual test generation still required.

• Design iterations also required.

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Syndrome-Testable Design

Savir, IEEE TC-29(6), 1980, & TC-30(8), 1981

S

kk s n

syndrome testable S f S

n

f

21, # & #

, .

where independent input variables.

A circuit is iff fault

Gate ANDn ORn XORn NOT

S 1/2n 1-1/2n 1/2 1/2

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Consider a circuit having 2 blocks, f and g, with unshared inputs:

S

O/p gate OR

Sf +Sg - SfSg

AND XOR NAND NOR

1 - Sf - Sg + SfSg1 - Sf - SgSf + Sg - 2SfSgSfSg

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Exercise 1Show that for blocks with shared inputs (circuits having reconvergent fanouts):

S f g S fg

S fg S fg

S f g S f g S fg

f g

f g

S SS S

1

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S

S = S1

1

2

3

4 2 3 2 3

4

11

4

3

4

11

4

3

41

81 7 32

21 128

S

S

S S S S S

S

( ) /

/ .

S1

S2

S3S4

S

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Definition 1

A logic function is unate in a variable xi if it can be represented as an sop or pos expression in which the variable xi appears either only in an uncomplemented form or only in a complemented form.

Theorem 1

A 2-level irredundant circuit realizing a unate function in all its variables is syndrometestable.

Theorem 2

Any 2-level irredundant circuit can be made syndrome-testable by adding control inputs to the AND gates.

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Let Then If then

Syndrome untestable.

Now add a control input c where

1 when in normal operation modenormal i / p when in test mode

and syndrome testable.

f xz yz S a z af y aS S

f cxz yz

c

S af y aS S

. . , . .

' ,

' , ' , ' ' .

12 0

12

38

12

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Drawbacks:

Only for combinational logic.

Exhaustive: all patterns applied, and # of 1s

recorded. Only applicable to small circuits (larger

circuits partition).

Modification doubles test set size.


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Scan -Type Design• To provide controllability and observability of internal state variables f

or testing.

• To turn the sequential test problem into a combinational one.

Four Major Approaches:

1. Shift-register modification [M. Williams & Angell, IEEE TC-22(1), 1973].

2. Scan path [Funatsu et al., DA Symp., 1975, & ITC, 1978].

3. LSSD [Eichelberger & T. Williams, DAC, 1977, & JDAVTC-2(2), 1978].

4. Random access [Ando, COMPCON, 1980].

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Shift-Register Modification

• Invented at Stanford in 1973 by M. Williams & Angell.• Later adopted by IBM---heavily used in IBM products

State Vector

CombinationalLogic

X Z

y Y

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To make elements of state vector controllable and observable, we add

1. A TEST mode pin(T).

2. A SCAN-IN pin(SI).

3. A SCAN-OUT pin (SO).

4. A MUX (switch) in front of each FF (M).


C/LZX

SI

CT

M FF M FF M FF SO

D QD Q

DI

SIT

C

L1 L2

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Test procedure:

1. Switch to the shift-register mode and check the SR operation by shifting in an alternating sequence of 1s and 0s, e.g., 00110 (functional test)

2. Initialize the SR---load the first pattern.

3. Return to the normal mode and apply the test pattern.

4. Switch to the SR mode and shift out the final state while setting the starting state for the next test. Go to 3.

• The SI pin may be a redefined input pin (using a MUX ) in test mode.

• The SO pin may be a redefined output pin (using a MUX ) in test mode.

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Scan Path

• By Kobayashi, 1968, and Funatsu, 1975, at NEC, and adopted by NEC.

• Uses raceless D-FFs: each FF consists of 2 latches operating in master-slave fashion, and has 2 clocks to select either SI or DI.

Normal mode: C2 = 1 to block SI; C1 = 0 - 1 to load KI.

SR(test) mode: C1 = 1 to block DI; C2 = 0 - 1 to load SI.

C2

SI

DI

C1

L1

L2

DO

SO

2-port raceless master-slave D FF

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Level-Sensitive Scan Design (LSSD)

• By Eichelberger and T. Williams, 1977, 1978

• Latch-based design used at IBM.

• Race-& hazard-free operation and testing: insensitive to rise time, fall time, delay, etc.

• Faster than SR modification; lower hardware complexity.

• More complicated design rules.

• Uses 2 latches: one for normal operation and one for scan.

A logic circuit is level sensitive iff the steady state response to any allowed input change is independent of the delays within the circuit. Also, the response is independent of the order in which the inputs change.

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LSSD

Polarity-Hold Latch:

• The correct change of the latch output (L) is not dependent on

the rise/fall time of C, but only on C being ,1, for a period of time

data propagation and stabilization time.

L

D

L

D

C

+L

C D

0 0

0 1

1 0

1 1

+L

L

L

0

1

C

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LSSDPolarity-Hold Shift-Register Latch (SRL):

• Normal mode: A = B =0, C =0 1.

• SR (test) mode: C =0, AB = 10 01 to shift SI through L1 and L2.

L1

L2

DICSIA

B

+L1

+L2

+L1

+L2

DI

C

SI

A

B

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LSSD

• Polarity-Hold, hazard-free, and level-sensitive.

• To be race-free, clocks C & B as well as A & B must be nonoverlapping.

• Avoids performance degradation introduced by the MUX in shift-register modification.

• Can replace B with A+B, i.e., NOR(A,C).

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Double-Latch LSSD

XC/L

Z

SI SO

CA

B

L1L2 L2 L2

L1 L1

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Single-Latch LSSD

C/LZX

SI SO

CA

B

L1L2 L2 L2

L1 L1

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Single-Latch LSSD With Conventional SRLs

L1 L2

L2L1

L2

L2

L1

L1

N1

N2

X1

Y1

X2

Y2SRL

e 11

e 1n

Scan Path

...

...

... ...

..

.

..

.

.~~

~~

e 1m

S in

AC2

.

Z1

Z12y21

y2m .

Y2

B

y1n

..

y11 .

S outY1

C1

e 21

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SRL Using Two-Port L2*

D = DI

C = CK1

S = I = D2

A = CK2

G1

G3

G4

G2

.

. ..

G8G7

G5

G6

..

.

B = CK4

D* = D3

C* = CK3

L*

L*

(a) Gate model

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D1

CK1

D2

CK2

L1

Q L1

Q

D1

CK1

D2

CK2

L2

Q L2

L*

L*.

(b) Symbol

SRL Using Two-Port L2*

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Single-Latch LSSD With L2* Latches

N1

D1CK1

D2CK2

L1

D1CK1

CK2

L1

N2D1

CK1

D2

CK2

D1CK1

D2CK2

Y2

X1

D2

Z1e 11

e 1n

... ...

y11

y1n

SRL

Y 1

L *

L *

L *

L *

y2n

y21

Y 2

X2

CA

...

Z2e 21

e 2n

C*B

S in

S out

...

Y1

.

.

.

.

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LSSD Design Rules

1. Internal storage elements must be polarity-hold latches.

2. Latches can be controlled by 2 or more nonoverlapping clocks that satisfy:

(1) A latch X may feed the data port of another latch Y

iff the clock that sets the data into Y does not clock

X.

(2) A latch X may gate a clock C to produce a gated

clock Cg , which drives another latch Y iff Cg , or any

other clock C1g , produced from Cg , does not clock X.

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LSSD Design Rules

3. There must exist a set of clock primary inputs from which the clock inputs to all SRLs are controlled either through (1) single-clock distribution tree or (2) logic that is gated by SRLs and/or nonclock primary inputs. In addition, the following conditions must hold:

(1) All clock inputs to SRLs must be OFF when clock PIs

are OFF.

(2) Any SRL clock input must be controlled from one or

more clock PIs.

(3) No clock can be ANDed with either the true or the

complement of another clock.

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LSSD Design Rules4. Clock PIs cannot feed the data inputs to latches, either directly

or through combinational logic.

5. Every system latch must be part of an SRL; each SRL must be part of some scan chain.

6. A scan state exists under the following conditions:

(1) Each SRL or scan-out PO is a function of only the

preceding SRL or scan-in PI in its scan chain during the

scan operation.

(2) All clocks except the shift clocks are disabled at the SRL

inputs.

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LSSD Design Rules

(3) Any shift clock to an SRL can be turned ON or OFF by

changing the corresponding clock PI.

• A network that satisfies rules 1-4 is level-sensitive.

• Race-free operation is guaranteed by rules 2(1) & 4.

• Rule 3 allows a tester to turn off system clocks and use the shift clocks to force data into and out of the scan chain.

• Rules 5 & 6 are used to support scan.

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Advantages With LSSD

• Correct operation independent of AC characteristics.

• Reducing FSM to C/L as far as testing is concerned.

• Eliminating hazards & races; simplifying test generation and fault simulation.

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Problems With LSSD

• Design rules imposed on designers --- no freedom to vary from the overall schemes, and higher design and hardware costs (4-20% more h/w & 4 extra pins).

• No asynchronous designs. • Sequential routing of latches can introduce irregular structures.• Faults Changing combinational function to sequential may

cause trouble, e.g., bridging and CMOS stuck-open. • Function to be tested has been changed into a quite different

combinational one, so specification language won, t be of any help.

• Slow test application; normal-speed testing is impossible.• Not good for memory intensive designs.

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Random Access

• Uses addressable latches.

• Provides random access to FFs via multiplexing---address selection.

• Used by Fujitsu, Amdahl, & TI (developed by Fujitsu [Ando, 1980]).

C/LZX

SIC

L1 L1 L1 L1

addrdecoder

DI

CKI

SI+L

CK2

Addr

SO

(C = CK1 & CK2)

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Random Access

Advantages:

Fast; minimal impact on normal path. Fast for testing---random access.

Ability to ,watch, a node in normal operation mode

(impossible with LSSD).

Disadvantages:

Address decode---and thus h/w overhead---is large.

More pins added ( ... parallel address).

No asynchronous circuits.

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A Typical CMOS Scan Cell Design

Q

SO

BC

A

QSO

Latch on FF

MUX

DI

SI

DISI

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Partial Scan

D: Sequential depth (the distance along the longest

path)

L: Maximum length of any cycle

The length of a test sequence for a sequential circuit is propotional to D . 2L .

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Partial ScanBASIC IDEA

Select a subset of flip-flops for scan

Lower overhead (area and speed)

Relaxed design rules

METHOD 1 (Trischler et al, ITC-80)Use testability measure for flip-flop selection

Use sequential ATPG

METHOD 2 (Agrawal et al, D&T, April 1988)Use functional vectors for initial fault coverage

Use comb. ATPG to select flip-flops for scan

Overhead about 50% of full-scan

METHOD 3 (Cheng and Agrawal, FTCS-19)Select scan flip-flops to simplify sequential ATPG

Overhead about 25% of full scan

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Partial Scan (Cheng and Agrawal)

• SELECT MINIMAL SET OF FLIP-FLOPS TO ELIMINATE SOME OR ALL CYCLES

• SELF-LOOPS (CYCLES OF UNIT LENGTH) ARE NOT BROKEN TO KEEP THE SCAN OVERHEAD LOW – THE NUMBER OF SELF-LOOPS IN REAL

DESIGN CAN BE QUITE LARGE

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1 2

3

4 5 6

A CIRCUIT W ITH SIX FLIP-FLOPSL = 1 L = 2

L = 31

2

3

4 5 6

D

GRAPH OF THE CIRCUIT

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MODE

1 2 4 5 6

3

SCANIN

SCANOUT

CLOCK 1CLOCK 2

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Partial Scan (Cheng and Agrawal)• SEPARATE SCAN CLOCK IS USED

• SCAN FLIP-FLOPS ARE REMOVED AND THEIR INPUT AND OUTPUT SIGNALS ARE ADDED TO THE PO/PI LISTS

• A SEQUENTIAL CIRCUIT TEST GENERATOR IS USED FOR TEST GENERATION

• THE VECTOR SEQUENCES ARE THEN CONVERTED INTO SCAN SEQUENCES:

• EACH VECTOR IS PRECEDED BY A SCAN-IN SEQUENCE TO SET THE STATES OF SCANNED FLIP-FLOPS

• A SCAN-OUT SEQUENCE IS ADDED AT THE END OF EACH VECTOR SEQUENCE

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CIRCUIT NAHE

TOTALNO. OF FFs

SCAN FFs

NO. %

NO. OF TESTVECTORS

FAULT COVERAGE (%)

TESTED REAUND. TOTAL

Tgen +Fslm SEC.(VAX 8650)

s400 s713

s5378

s9234

21

19

179

228

9

7

32

53

42.86

36.84

17.89

23.25

107

83

2612

3458

98.11

90.71

93.38

43.23

1.89

9.29

6.32

55.80

100.00

100.00

99.70

99.04

7

18

1253

6208

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Partical Scan (Gupta, Gupta, and Breuer)

C 1

R 2

R 1 R 4

R 5C 2

C 3

R 3

R 6

C 4

A

B

(a) Synchronous circuit S

C 1

R 2

R 1 R 4

R 5C 2

C 3

R 3

R 6

C 4

A

B

(b) A partial scan design of S

HOLD control(for test)

S o

S i

..........

.....

..........

...............

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C 1

R 2

R 1 R 4

R 5C 2

C 3

C 4

A

B

(c) Kernel K of S

C 1

C 2

C 3

C 4

A

B

(d) Combinational equivalent of K

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C 1

R 2

R 1R 4

R 5C 2

C 3

R 3

R 6

C 4

(b)

.....

.....

.....

..........

..........

..........

.....

.....

.....

Different partial and full scan designs for S

C 1

R 2

R 1 R 4

R 5C 2

C 3

R 3

R 6

C 4

(a)

.....

.....

.....

..........

..........

..........

.....

.....

.....



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C 1

R 2

R 1 R 4

R 5C 2

C 3

R 3

R 6

C 4

(c)

.....

.....

.....

..........

..........

..........

.....

.....

.....


C 1

R 2

R 1 R 4

R 5C 2

C 3

R 3

R 6

C 4

(d)

.....

.....

.....

..........

..........

..........

.....

.....

.....



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C 1

R 2

R 1 R 4

R 5C 2

C 3

R 3

R 6

C 4

(e)

.....

.....

.....

..........

..........

..........

.....

.....

.....

..........

..........

..........

..........

design for testability

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