Design Equations for Optimum Operation of Class E Amplifier with NonlinearShunt Capacitance at Any Duty Cycle

Tadashi Suetsugu †, and Marian Kazimierczuk ‡† Department of Electronics Engineering and Computer Science, Fukuoka University

8-19-1, Nanakuma, Johnan, Fukuoka, 814-0810 Japan‡ Department of Electrical Engineering, Wright State University

Dayton, OH, 45435 USA,Email: suetsugu@mail.tl.fukuoka-u.ac.jp, mkazim@cs.wright.edu

Abstract– Design equations for satisfying optimumconditions of Class E amplifier with a nonlinear shuntcapacitance with a grading coefficient of 0.5 at any dutycycle are derived. By exploiting sub-optimum class Eoperation, various amplifier parameters such as inputvoltage, operating frequency, output power, and loadresistance can be set as design specifications. An exampleof a design procedure of the class E amplifier is given.The theoretical results were verified with Pspicesimulation using SPICE MOSFET model Level 3.

1. Introduction

It is well known that the output capacitance of aMOSFET transistor is a nonlinear function of the drain-to-source voltage. The shunt capacitance of the class Eamplifier consists of the nonlinear transistor outputcapacitance. Especially at very high operating frequencies,whole of the shunt capacitance consists of the transistoroutput capacitance. However, most analyses of class Eamplifier have been done with linear capacitance.

An analysis of the class E amplifier with a nonlinearshunt capacitance of grading coefficient 0.5 was presentedfor the first time by Chudobiak for optimum operation atthe duty cycle D = 0.5 [4]. This analysis was done onlyfor the optimum operation at the duty cycle of D = 0.5.Authors have extended the Chudobiak analysis to sub-optimum operation and compared his results with linearshunt capacitance, subsequently. However, the analysisfor the optimum operation at any duty cycle has not beendone yet.

In this paper, design equations for the optimumoperation at any duty cycle are derived for a class Eamplifier with a nonlinear shunt capacitance of gradingcoefficient 0.5. In this analysis, expressions for allelements, peak switch voltage, peak switch currents, andoutput power capability are derived. A class E amplifiercircuit was designed and its operation was verified withPSpice using Level 3 MOSFET model.

2. Voltage and Current Waveforms of the Class EAmplifier with Nonlinear Capacitance

The circuit analyzed in this paper is a class E amplifiershown in Fig. 1. The shunt capacitance of the amplifierconsists only of the MOSFET output capacitance. The

derivations of design equations are carried out under thefollowing assumptions:

1) The inductance of the choke coil RFCL is largeenough to neglect its current ripple.

2) The internal resistance of the choke coil is zero;therefore, the DC voltage drop across the choke iszero.

3) The loaded quality factor Q of the outputresonance circuit is high enough so that the outputcurrent can be considered a sine wave.

4) The load resistance includes parasitic resistancesof the series resonance circuit, i.e., the resonancecircuit is considered to be a pure reactance.

5) The MOSFET on-resistance transistor is zero.6) The MOSFET turns on and off instantly.7) The shunt capacitance 1C is entirely comprised of

the MOSFET output capacitance.8) The grading coefficient of the MOSFET output

capacitance is 0.5. The shunt capacitance isdescribed by

bi

S

j

Vv

CC

+=

1

01 (1)

where 0jC is the shunt capacitance at the drain to switch

voltage 0=Sv and biV is the built-in potential of theMOSFET body diode.

The transistor is OFF for Dπθ 20 <≤ , and ON forπθπ 22 <≤D . While the transistor is OFF, the current

through the shunt capacitance is( ) ( )φθθ +−= sinmDDC IIi (2)

where DDI is the dc input current, mI is the outputcurrent amplitude, and tωθ = . The switch voltage Sv isthe integral of the shunt capacitor current Ci given by

θddvCi S

C 1= . (3)

Integrating both side of this equation with respect of θgives

θω didvC CS ∫∫ =1 . (4)

Substituting 1C given by (1),

2004 International Symposium on NonlinearTheory and its Applications (NOLTA2004)

Fukuoka, Japan, Nov. 29 - Dec. 3, 2004

331

( )[ ]∫∫ +−=+

θ

θφθω00

0 1

ʹʹsin dIIdv

Vv

CmDD

v

bi

jS

. (5)

Solving this equation, the switch voltage Sv can bederived as

( )

( )[ ] 112

2

0−

+−++

=

jbi

mDDbi

S

ωCVθIθIV

v

φφ

θ

coscos

(6)3. Circuit Parameters for Optimum Operation at Any

Duty Cycle

For the optimum operation,( ) 02 =DiC π (7)

and( ) 02 =DvS π (8)

are satisfied. Substitution of (7) into (2) yields

DDDDDDπππ

πππφ222

1222cossin

cossinarctan−

−+= . (9)

Fig. 3 shows φ as a function of the duty cycle D . φdecreases from positive to negative values as D increases.Substituting (8) into (6),

( )φπππ += DDIDI mDD sinsin . (10)Since the power loss in the circuit is zero, the outputpower is equal to the input power,

2

2RIVIP mDDDDo == . (11)

Substituting (10) into (11), one can obtain the outputcurrent amplitude mI and the output power oP for theoptimum operation at any duty cycle.

( )DR

DDVI DDm π

φππ +=

sinsin2 (12)

( )RD

DDVP DDo 22

2222π

φππ +=

sinsin . (13)

Fig. 4 shows normalized output current amplitude

DDm VRI / and normalized output power 2DDo VRP / as a

function of the duty cycle D . The normalized outputcurrent amplitude DDm VRI / decreases from 2 to zero as

D increases. The normalized output power 2DDo VRP /

also decreases from 2 to zero as D increases.Fig. 5 shows RCj0ω as a function of the duty cycle D

and biDD VV / . RCj0ω for the optimum operation can beobtained by substituting (9) into

( )

( )[ ]

( ) ( )

( ) ( )[ ]

( )[ ] .sincos22sin22

1

cos22cos2sin22

42sin322sin2sincos2

424sin

38

81

112

coscos21

21

22

0

22

22

232

20

2

2

0

2

0

2

0

φφπφπππω

φπφπφππ

φφππφπφππ

ππω

θφφ

π

θθπ

π

π

−−+++

−++++

++−−+

+++

=

−

+−++

=

=

∫

∫

DDIIDC

DDDDII

DDDDDI

IDVC

dωCVθIθI

V

dvV

mDDj

mDD

m

DD

bij

D

jbi

mDDbi

SDD

(14)RCj0ω reaches the maximum value for 50.=D . It

increases with an increase in biDD VV / . The phase angle

1φ of the voltage 1v , i.e., the phase of the sum of theoutput voltage and the fundamental component of thevoltage across the reactance X , is derived as

2

11 b

barctan=φ (15)

where( )[ ]

( ) ( )

( )

( ) ( )

( )

( ) ,4

sin2sincoscos4

4sin

12cos2sin28

cos72coscos2sincos2

cos8

4cos24sin

2

122sin2cos

424sin

44sin

2sincos4

22sin12

26sin22sin

4

2cos42sin244

0

0

2220

2

220

2

2

2220

2

2

1

−−+

++

−+++−−

+

++

++

−−

+−−−

+

++

+++

+−=

φπφφπφπω

πππω

φπφπφπ

φπφπφππω

φφπφπππ

πφφπφππω

ππππω

DDDCI

DDDC

IDDD

DDDDVC

II

DDDD

DDDDVC

I

DDDDVC

Ib

j

m

j

DD

bij

mDD

bij

m

bij

( )[ ]

( ) ( )

( )

( ) ( )

( )

( ) . 4

cos32coscossin4

4cos

2sin2cos28

sin2sincos2coscos2

sin8

4sin24cos

2

41cos

122cos52sin

424cos

44cos

2coscos4

22cos12

26cos22cos

4

22sin42cos244

0

0

2220

2

2

220

2

2

2220

2

2

2

+−+

++

−+++−

+

+−

++

−−+−

+−−

+

+−

+++

+−−=

φπφφπφπω

πππω

φπφπφπ

φπφπφππω

φφφπφππ

πφφπφππω

ππππω

DDDCI

DDDC

IDDD

DDDDVC

II

DDD

DDDDVC

I

DDDDVC

Ib

j

m

j

DD

bij

mDD

bij

m

bij

DD

Fig. 6 shows RX / as a function of the duty cycle D and

biDD VV / . RX / can be obtained by substituting (9) into(15). RX / increases with an increase in the duty cycleD , but it does not change significantly with a change in

biDD VV / . Fig. 7 shows normalized peak switch voltage

DDSM VV / versus duty cycle D and biDD VV / .

DDSM VV / increases from zero to a positive value as theduty cycle D is increased from 1 to zero. Fig. 8 shows

332

power output capability pc versus duty cycle D and

biDD VV / . pc is obtained as

SMSMp VI

Pc 0= . (16)

where oP is the output power of the optimum operation,

SMI is the peak switch current for the optimum operation,which is obtained by substituting (12) into (2), and SMVis the peak switch voltage for the optimum operation,which is obtained as ( )1θSv in which 1θ is obtained from(6). pc is maximum when 50.=D . pc does not change

much with a change in biDD VV / when 5>biDD VV / .

4. Simulation Results

The example circuit was simulated with PSpice. Thecircuit parameters were V 10=DDV , H 100 µ=RFCL ,

nF 779.=C , H 183 µ.=L , Ω= 2R . The operatingfrequency was 1 MHz. The duty cycle was 0.6. TheSPICE MOSFET MODEL Level 3 was used for theMOSFET. In the SPICE MOSFET model, the drain-source capacitance is expressed as [4]

MJ1

PB1

CBD

+

=Sv

C , (65)

where CBD is the zero-bias bulk-junction capacitance,which is the same as 0jC , PB is the bulk junction

potential which is the same as biV , and MJ is the bulkbottom grading coefficient which is 0.5 in this example. Inaccordance with the calculations, we set CBD = 65 nF, PB= 0.7 V, and MJ = 0.5. The simulated waveforms of switch voltage Sv and theoutput voltage ov are shown in Fig. 9. The peak switchvoltage SMV was 32.5 V (36 V in theory). The outputvoltage amplitude mV was 6.35 V (7.66 V in theory). Inour design, the MOSFET on-resistance and the gate-draincapacitance were ignored. The existence of these parasiticcomponents may cause errors.

References

[1] N. O. Sokal and A. D. Sokal, “Class E - A new class of high-efficiency tuned single-ended switching power amplifiers,” IEEE J.Solid-State Circuits, vol. SC-10, pp. 168-176, June 1975.

[2] M. J. Chudobiak, “The use of parasitic nonlinear capacitors inclass E amplifiers,” IEEE Trans. Circuits Syst. I, vol. 41, no. 12,pp. 941-944, Apr. 1994.

[3] M. K. Kazimierczuk and D. Czarkowski, Resonant PowerConverters, New York: John Wiley & Sons, Inc., 1995, Chapter13.

[4] R. M. Kielkowski, SPICE Practical Device Modeling, NewYork: McGraw-Hill Inc., 1995, Chapters 3 and 6.

[5] C. H. Li and Y. O. Yam, “Maximum frequency and optimumperformance of Class E amplifiers,” IEE Proceedings,Circuits,Devices and Systems, vol. 141, pp. 174-184, 1994.

-4.00

-3.00

-2.00

-1.00

0.00

1.00

2.00

0 0.2 0.4 0.6 0.8 1

Duty cycle D

(rad

)

Fig. 3. Phase angular φ versus duty

Fig. 2. Normalized output current amplitude ImR/VDD,normalized output power PoR/VDD

2, and normalizedshunt capacitance current at switch turning-oniC(π)R/VDD as functions ofφ .

-1.5

-1

-0.5

0

0.5

1

1.5

-3.14 -2.64 -2.14 -1.64 -1.14 -0.64 -0.14

φ (rad)

ImR/VDD

PoR/VDD2

iC(π)R/VDD

φ = -0.567

Sub-optimumoperation area

Sub-optimum Sub-optimum

φ = -π

Optimumoperation

Zeropower

C1

Fig. 1. Basic circuit of a class Eamplifier.

RFCLrLC

R

DDVDDI

oi

ovSv

Si

jX

rCL1=ω

L

iC

1v

Xv

333

0.00.20.30.40.60.70.9

0

65 0

200

400

600

X/R

Duty cycle D

V DD /Vbi

Fig. 6. RX / versus duty cycle D.

0.00.20.30.40.60.70.91.0

0

95 0

0.5

1

1.5

2

ω Cj 0R

Duty cycle D

VDD /Vbi

Fig. 5. RCj0ω versus duty cycle D.

0.00.

20.40.

60.70.

9

0

90

0

50

100

150

VSM/VDD

Duty cycle DVDD/Vbi

Fig. 7. Normalized peak switch voltageDDSM VV / versus duty cycle D and biDD VV / .

0.00.2

0.40.6

0.70.9

0

65

00.02

0.04

0.06

0.08

0.1

cp

Duty cycle DVDD/Vb i

Fig. 8. Power output capability pc versus duty

cycle D and biDD VV / .

-0.5

0

0.5

1

1.5

2

2.5

0 0.2 0.4 0.6 0.8 1

Duty cycle D

I m

ImPo

Fig. 4. Normalized output current amplitudeDDm VRI / and normalized output power2DDo VRP / versus duty cycle D.

Fig. 9. Simulated waveforms of the switch voltageSv and the output voltage ov .

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