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Synthesis & Gate-Level GateSimulationREF: CIC Training Manual Logic Synthesis with Design Compiler, July, 2006 TSMC 0.18um Process 1.8-Volt SAGE-XTM Stand Cell Library Databook, September, 2003 TPZ973G TSMC 0.18um Standard I/O Library Databook, Version 240a, December 10, 2003 9 3G S C 0 8u Sta da d /O b a y ataboo , e s o 0a, ece be 0, 003 Artisan User Manual
Advanced Reliable Systems (ARES) Lab.
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12/8 : Synthesis & Gate-level Netlist Simulation Edit your synthesis script file Familiar with the Design Compiler g p Gate-level netlist simulation script constraints (ex: timing, area, etc)script Design Compilerscript file : script file : gate-level netlistsimulation
LAB 2 simple 8-bit microprocessor
Advanced Reliable Systems (ARES) Lab.
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Outline Basic Concept of the Synthesis Synthesis Using Design Compiler Simulation-Based Power Estimation Using PrimePower Artisan Memory Compiler y p LAB
Advanced Reliable Systems (ARES) Lab.
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Basic Concept of the Synthesis
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Cell-Based Design FlowSpec. System LevelMATLAB/ C/ C++/ System C/ ADS/ Covergen (MaxSim) Memory Generator
RTL Level
Verilog/ VHDL Conformal/ Formality
NC-Verilog/ ModelSim Debussy (Verdi)/ VCS Ph hysical Com mpiler/ Mag gma Blast Fusion Design/ Power Compiler DFT Compiler/ TetraMAX NC-Verilog/ ModelSim Debussy (Verdi)/ VCS SOC Encounter/ Astro GDS II DRC/ LVS (Calibre)PVS: Calibre xRC/ NanoSim (Time/ Power Mill)
Syntest
Logic Synthesis Design for Test Gate Level
Layout Level Post-Layout Verification
Tape OutAdvanced Reliable Systems (ARES) Lab. 5
What is Synthesis Synthesis = translation + optimization + mappingif(high_bits == 2b10)begin residue = state_table[i]; [ ]; end else begin residue = 16h0000; end
Translate (HDL Compiler)
HDL Source (RTL)
No Timing Info. Optimize + Mapping (HDL Compiler)
Generic Boolean (GTECT)
Timing Info. The synthesis is constraint driven and technology independent !!Advanced Reliable Systems (ARES) Lab.
Target Technology6
Logic Synthesis OverviewRTL Design
Architecture Optimization
HDL Compiler
Design Ware Library
DW Developer
Logic Optimization
Design Compiler
Technology Library
Lib p Compiler
Optimized Gate-Level Netlist
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CompileRTL code or netlist Compile Attributes & ConstraintsTechnology Library Lib(Can be set by the GUI interface or user-defined Script File !!)
Optimized Design Schematic Reports
(Gate-Level Netlist)
( (Timing, Area, Power, , etc) g, , , , )
Flatten
Structure
Logic Level Optimization
Gate Level OptimizationTechnology LibraryAdvanced Reliable Systems (ARES) Lab.
Map8
Logic Level Optimization Operate with Boolean representation of a circuit Has a global effect on the overall area/speed characteristic of a design Strategy Structure Flatten (default OFF) ( ) If both are true, the design is first flattened and then structuredEx:f = acd + bcd +e g = ae + be h = cde f = xy + e g = xe h = ye x=a+b y = cd f0 = at f1 = d + t f2 = te te t=b+c f0 = ab + ac f1 = b + c + d f2 = bce bce
(Structure)Advanced Reliable Systems (ARES) Lab.
(Flatten)9
Gate Level Optimization - Mapping Combinational Mapping Mapping rearranges components combining and re-combining components, logic into different components May use different algorithms such as cloning, resizing, or buffering b ff i Try to meet the design rule constraints and the timing/area goals
Sequential Mapping Optimize the mapping to sequential cells technology library Analyze combinational logics surrounding a sequential cell to see y g g q if it can absorb the logic attribute with HDL Try to save speed and area by using a more complex sequential cells
Advanced Reliable Systems (ARES) Lab.
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MappingCombinational Mappinga b a c b a x1 x1Critical Path
Sequential Mappingc A B A B
c
a b
D
Q
QAND_FF
a b
c
c
a x2 x4
c A B D Q A B QLoop_FF
Critical Path
a
(assume g loading high)
f g
a
f g11
Advanced Reliable Systems (ARES) Lab.
Boundary Optimization Design Compiler can do some optimizations across boundaries 1. Removes logic driving unconnected output ports
2. Removes redundant inverters across boundaries
3. Propagates constants to reduce logic
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Static Timing Analysis Main steps of STA Break the design into sets of timing paths Calculate the delay of each path Check all path delays to see if the given timing constraints are met
Four types of paths Register - Register ( (Reg - Reg) ) Primary Input - Register (PI - Reg) Register - Primary Output (Reg - PO) Primary Input - Primary Output (PI - PO)
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Static Timing Analysis (Cont)- Setup Time
To meet the setup time requirement: Trequire >= Tarrival Tarrival = Tclk1 + TDFF1(clk->Q) + TPATH Trequire = Tclk2 - TDFF2(setup) Tslack = Trequire - TarrivalClk_source clk1 PATH Tarrival clk2 DFF2
Reg to Reg
(Tslack > 0 denotes l k no timing violation)
DFF1
Dclk1
Q Q
D
Q Qclk2
TDFF1 + Tpath Tarrival data Tsetup Trequire Tslack14
Advanced Reliable Systems (ARES) Lab.
Static Timing Analysis (Cont) PI to Reg Tarrival = TPI(delay) + TPATH Trequire = Tclk1 - TDFF1(setup) Tslack = Trequire - Tarrival - Setup Time
Clk_source Tarrival TPI(delay) PI PATH Tarrival clk1 DFF1 Tpath data clk1 Tsetup Tslack15
D
Q Q
Trequire
Advanced Reliable Systems (ARES) Lab.
Static Timing Analysis (Cont) Reg to PO Tarrival = Tclk1 + TDFF1(clk->Q) + TPATH Trequire = Tcycle - TPO(output delay) Tslack = Trequire - Tarrival - Setup Time
Clk_source clk1 DFF1 TDFF1 + Tpath PATH PO Tarrival Tarrival data TPO(output delay)
Dclk1
Q Q
Trequire
Tslack16
Advanced Reliable Systems (ARES) Lab.
Static Timing Analysis (Cont) PI to PO Tarrival = TPI(delay) + TPATH Trequire = Tcycle - TPO(output delay) Tslack = Trequire - Tarrival - Setup Time
Clk_source
TPI + Tpath PI PATH PO Tarrival TrequireAdvanced Reliable Systems (ARES) Lab.
Tarrival
data TPO(output delay)
Tslack17
Static Timing Analysis (Cont)- Hold Time
To meet the hold time requirement: Trequire Q) + TPATH Trequire = Tclk2 + TDFF2(hold) Tslack = Tarrival - TrequireClk_source Clk source clk1 DFF1 DFF2 Tarrival clk2
Reg to Reg
TDFF1 + Tpath data 1
Dclk1
Q Q
PATH
data 0 clk2
D
Q QThold Trequire Tslack
Tarrivall iAdvanced Reliable Systems (ARES) Lab. 18
Static Timing Analysis (Cont) PI to Reg Tarrival = TPI(delay) + TPATH Trequire = Tclk1 + TDFF(hold) Tslack = Tarrival - Trequire Tarrival = Tclk1 + TDFF(clk->Q) + TPATH Trequire = - TPO(output delay) Tslack = Tarrivall - Trequire l k i i Tarrival = TPI(delay) + TPATH Trequire = - TPO(output delay) Tslack = Tarrival - Trequire - Hold Time
Reg to PO g
PI to PO
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Synthesizable Verilog Verilog Basis p parameter declarations wire, wand, wor declarations reg declarations input, output, input output inout continuous assignment module instructions gate instructions always blocks task statement function definitions for, while loop and, or, not, nand, nor, xor, xnor , , , bufif0, bufif1, notif0, notif120
Synthesizable Verilog primitives cells
Advanced Reliable Systems (ARES) Lab.
Synthesizable Verilog (Cont) Operators Binary bit-wise ( ~, &, |, ^, ~^ ) y | Unary reduction ( &, ~&, |, ~|, ^, ~^ ) Logical ( !, &&, || ) 2s 2s complement arithmetic ( + -, *, / % ) +, /, Relational ( >, =, >, dc shell dc_shell dc_shell-t> read_lib t13spsram512x32_slow_syn.lib dc_shell-t> write_lib t13spsram512x32 -output \ user library name, which should t13spsram512x32_slow_syn.dbany memory LIB file
Modify File:
be the same as the library name in the Artisan
set link_library * slow.db t13spsram512x32_slow.db dw_foundation.sldb memory DB file add to the file set target library slow db t13spsram512x32 slow db target_library slow.db t13spsram512x32_slow.db
Before the synthesis, the memory HDL model should be blocked in your netlist y
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Test Pins Reservation You can add the floating test pins to your design before synthesis se: scan enable si: scan input so: scan output scantest: control signal for memory shadow wrapper (i e memory is used) (i.e.
Ex:Normal IO Declaration Test IO Declaration
The pins will be connected to scans after the scan chain insertion pAdvanced Reliable Systems (ARES) Lab. 28
CHIP-Level Netlist The CHIP-level netlist consists of your Core-level netlist and the PADsEx: ECORNER1 CORNER2
CORE.v CORE
CHIP.v CHIP v (CHIP-Level Declaration)
I_CLK
CORECLK CSO
O_CSOCORNER3 CORNER4
(CORE-Level Design)
(Input PAD) (Output PAD)
I_CLK CSO
PAD I
C
CLK (IO PAD Declaration) D l ti )29
PAD O_CSO
Advanced Reliable Systems (ARES) Lab.
How To Choose the IO PAD You can reference the Databook of the IO
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