design compiler eng

Download Design Compiler Eng

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Design Compiler

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ASIC Design Flow

Design Compiler

Asic Desgin Flow

Design Compiler

Asic Desgin Flow

Design Compiler

Directory structure Design compiler step by step

Asic Desgin Flow

Design Compiler

Directory structure / - leda/ - vcs - dc

---Project directory --- Check rule -- Check timing and verification --- Design compiler : generate Netlist

rpt work syn

--- report ----- synthesis : contain files *.ddc, *.v after synthesis --- Formality --- Primetime --- Layout

- fm - pt - iccAsic Desgin Flow

Design Compiler

Design compiler step by stepStep 1: Invoke Desgin Compiler GUI flow steps : 1

Open termial go to folder dc in project directory design_vision OR dc_shell start_gui File Setup

Setp 2: Setup Library 2

Asic Desgin Flow

Design Compiler

Design compiler step by step

Asic Desgin Flow

Design Compiler

Design compiler step by step

Search path: path for searching file path link to directory contain library technology Target library : link to file *.db in library technology Symbol library: link to file generic.sdb library /usr/synopsys/dc/libraries/syn/generic.sdb Link library : link to both file *.db and *. sldb Synthetic library : dw_foundation.sldb /usr/synopsys/dc/libraries/syn/dw_foundation.sldb //NOTE: support library technology

Asic Desgin Flow

Design Compiler

Design compiler step by stepStep 3: creat file *.svf 3 // file *.svf use for FormalityGenerate a Formality setup imformation file for efficient comparepoint mathching in Formality

Asic Desgin Flow

Design Compiler

Design compiler step by stepStep 4: Read file 4 File Read top_module.v

Asic Desgin Flow

Design Compiler

Design compiler step by stepStep 5: Analyze 5 file analyze Add < top_module.v >OK

Asic Desgin Flow

Design Compiler

Design compiler step by stepStep 6: ElaborateFile Elaborate OK 6

Asic Desgin Flow

Asic Desgin Flow

Design Compiler

Design compiler step by stepStep 7: Check design: DesignCheck designOK

Asic Desgin Flow

Design Compiler

Design compiler step by stepStep 8: Set clock constraints 8 1- Creat design schematic- click icon on Design Vision GUI

Asic Desgin Flow

Design Compiler

Design compiler step by step

Asic Desgin Flow

Design Compiler

Design compiler step by step2- Creat clock:- Name : clk ; cycle = 4ns - Use key I & O to zoom in and zoom out - Click clk in Schematic

Asic Desgin Flow

Design Compiler

Design compiler step by step 3- Specify clk:Then click on Attributes in Design Vision GUI specify clock - At Port name must be have clk - At clock name: clk // clk is specfied - At period : 4 // a cycle = 4 time unit - Check in don't touch network and fix hold

After click OK look at terminal have a comman: create_clock -name "clk" -period 4 -waveform { 0.000 2.000 } { clk } OK

Asic Desgin Flow

Design Compiler

Design compiler step by step

Asic Desgin Flow

Design Compiler

Design compiler step by stepStep 9: Optimize the design : Design Compile design... 9

Asic Desgin Flow

Design Compiler

Design compiler step by stepStep 10: Optimized the design : Design Compile Ultra... 10

Asic Desgin Flow

Design Compiler

Design compiler step by stepStep 11: Report 11 1- Report- report_timing : Timing Report Timing Path - report_constraint : Design Report Constraint - report_power : Design Report Power - report_resource : Design Report Design Resources

Asic Desgin Flow

Design Compiler

Design compiler step by step2- Save report :

Asic Desgin Flow

Design Compiler

Design compiler step by stepStep 12: Creat NETLIST - top.v :File Save As

Asic Desgin Flow

Design Compiler

Design compiler step by stepStep 13: creat file top.ddc 13Save the unmapped design

Asic Desgin Flow

Design Compiler

Design compiler step by stepStep 14 : creat file top.sdf write a Standard Delay Format back annotation file

Asic Desgin Flow

Design Compiler

Design compiler step by stepStep 15: Creat file : top.sdc 15 write out a script in synopsys Design Constraint (sdc)format

Asic Desgin Flow

Design Compiler

Design compiler step by stepStep 16 : Set_svf_off

Asic Desgin Flow

Design Compiler

Question?

Asic Desgin Flow

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