department of electronic engineering, fju self checking carry-select adder design based on two-rail...
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Two-Rail Encoding
Adviser： Jenn-Wei Lin (林振緯 )Student： Jen-Chiun Guan(官振群 )
Mar. 16 , 2009
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 12, DECEMBER 2007
Dilip P. Vasudevan, Parag K. Lala, and James Patrick Parkerson
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IntroductionDesign of a self-checking 2-bit carry-select adderConfiguration logic for the input of the checker Design of self-checking multiplexerFaults caseOverhead Implementation of a 64 bit and 128 bit self-checking
adderConclusion
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INTRODUCTION
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To guarantee reliable operation of such an adder the detection of faults in the adder, especially transient faults, is extremely important. The probability of transient faults occurring in modern VLSI systems has grown significantly because of the shrinkage in transistor dimensions
This technique detects errors only at the output of an adder.
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This paper proposes a scheme that encodes the sum bits using two-rail codes , the encoded sum bits are then checked by self-checking checkers.
The scheme is illustrated with the implementation of a 2-bit carry select adder that can detect all single stuck-at faults on-line; the detection of double faults is not guaranteed.
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This paper proposes a design scheme for implementing self-checking carry-select adders by cascading totally self-checking 2-bit adders. The resulting carry-select adders satisfy the following criteria.
（ 1 ） They are totally self-checking for all single faults.
（ 2 ） Have a built-in compact checker.
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051015202530
Ripple-carry
Manchester
Carry-skip
Carry-select
Conditional-sum
Area(105μ m²)
Delay(ns)
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DESIGN OF A SELF-CHECKING 2-BIT CARRY-SELECT ADDER
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The 2-pair-2-rail checker can detect the presence of any single stuck-at fault in the circuit on-line.
In addition to the checker, three self-checking multiplexers and an EX-NOR gate are used for detecting these faults. Any single stuck-at fault in the modified adder can be detected online.
A totally self-checking checker at the output stage and determines the presence of the fault.
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The checker has two outputs; two of the output combinations 01 and 10 are considered valid code words. The sum bits with carry-in 0 and 1 generated internally by the adder are used as inputs to the checker. A nonvalid checker output , i.e., 00 or 11 indicates the presence of a fault in the circuit or in the checker.
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CONFIGURATION LOGIC FOR THE INPUT OF THE CHECKER
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A close observation of the sum bits generated with a carry-inof “0” and “1” shows the following property of addition：
In an addition of two -bit numbers with the least significantbit being “0” for both the numbers, if the carry-in bit is changedfrom one value to another the LSB of the sum is complemented,the other bits remain unchanged.
complementary
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complementary
110110
110001
01110111011100
SSS
SSS
SSSSSSS
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ing fault coverage
In the proposed self-checking adder the checker circuit cannot detect on-line the presence of faults in the multiplexer. Thus, it is necessary to make the multiplexer self-checking in order to increase the fault coverage of the adder. In the presence of faults the outputs of the multiplexer generate nonvalid code words and can either be transferred to a checker or can be used to raise an error flag.
Fault coverage = Number of detected faults
Total number of faults
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FAULTS CASE
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Case 1: A Fault at the Carry-In /Carry-Out of the Adders:
Case 2: A Fault at the Sum Bits With Carry-In “0” and Carry-In “1”:
Case 3: A Fault at the Inputs/Output of the EX-NOR:
Case 4: Faults at the Inputs/Outputs of the Multiplexer and Actual Carry-In:
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CASE1
CASE2
CASE3
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CASE4
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OVERHEAD
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The overhead in the proposed design for a self-checking 2-bit adder is the 2-pair-2-rail checker, and the EX-NOR gates. The number of transistors needed to implement these units for a 2-bit addition is given below:
• full adder – 28 transistors;
• 2-pair-2 Rail checker- 8 transistors
• EX-NOR – 10 transistors;
• self-checking multiplexer- 12 transistors.
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Self-Checking
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Self-Checking
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IMPLEMENTATION OF A 64 BIT AND 128 BIT SELF-
CHECKING ADDER
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absence of a fault.
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CONCLUSION
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A technique for implementing self-checking carry-select adders of arbitrary size using a 2-bit self-checking carry-select adder as the component is proposed. These adders are totally self-checking for both permanent and transient single stuck-at faults, however the detection of all double faults is not guaranteed.
In the presence of any fault a nonvalid code word is provided as input to the checker yielding a nonvalid output code word. Detailed implementations of a 64-bit and a 128-bit adder are provided to show the feasibility of the proposed design scheme.