fpga implementation of borrow save adder under threshold ......2019/03/22 · 2. borrow save adder...
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ICNSCET19- International Conference on New Scientific Creations in
Engineering and Technology
FPGA Implementation of Borrow Save Adder Under
Threshold Voltage Variability
P.Monika1, M.Gowsalya
2, N.Naga sowmiya
3
Electronics and Communication Engineering
Dr.Mahalingam College of Engineering and Technology
Abstract—Adder is a building block of all arithmetic units used in processors. The performances of
adders are evaluated on the basis of power consumption, energy consumption and delay. In this
approach the Borrow Save Adder (BSA) is designed with minimum delay under low threshold
voltage and it is compared with Ripple Carry Adder (RCA). It presents a solution for low power
addition under threshold voltage variability, which successfully handles the changes of increasing
threshold voltage. In addition the proposed approach demonstrates the tolerance of adder unit to
variations.
Keywords— Ripple Carry Adder(RCA); Borrow Save Adder(BSA); timing analysis; power
consumption; threshold voltage; delay.
I. INTRODUCTION
An adder is a digital circuit that performs addition operation and it act as a building block for
all processing units. Adders are utilized in processor, where they are used to
calculate addresses, increment and decrement operators, and similar operations are performed.
Adders are fundamental in DSP systems and several other applications, and contribute significantly
to the critical path delay of related hardware. The ripple carry adder and borrows save adder are
compared in presence of voltage supply variation. The comparison is performed in terms of delay
variation; voltage reduction is explored as a technique that leads to power efficiency. The main focus
is to estimate variability of maximum combinational delay caused by the threshold voltage
variations, neglecting the variability generated by other parameters that affect delay. The Borrow
Save Adder has proven suitable for low power operation under variations. In this paper, ripple carry
adder and borrow save adder is designed using Verilog code. Then the performance of these two
adders are analyzed and compared. The rest of the paper is organized as follows: Section I deals with
the introduction about adder. Section II deals with the working operation of RCA and BSA. Section
III deals with simulation output, layout design, FPGA implementation and performance analysis.
Section IV concludes the paper.
II. METHODOLOGY
An adder is capable of adding n-bit binary numbers, where n depends on the circuit implementation.
Adders are represented in different ways. Here, the methods considered for comparison are
1. Ripple Carry Adder
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2. Borrow Save Adder
3. Modified Borrow Save Adder
2.1. RIPPLE CARRY ADDER
A ripple carry adder is a logic circuit in which the carry-out of each full adder is the carry in of
the succeeding next most significant full adder. It is called a ripple carry adder because each carry bit
gets rippled into the next stage.
In RCA, all full adders are connected in series and the operation of nearby full adder does not
perform until previous FA exit the operation. So the delay becomes maximized. The architecture of
RCA is shown in fig.1.
Fig 1: Ripple Carry Adder
2.1.1. ILLUSTRATION OF RCA
In 4-bit Ripple Carry Adder, the addition of seven and one with zero carry-in is expressed in
conventional binary representation as x=0111 and y=0001 respectively , and a carry to be propagated
sequentially from the first to the fourth bit position through the carry chain in the RCA. The working
operation Ripple Carry Adder is given below. At last the sum output is eight and it is represented in
binary form as S=1000 and carry out is zero.
Let X=0 1 1 1; Y=0 0 0 1
Adding X and Y
1 1 1 => CARRY
X=0 1 1 1
Y=0 0 0 1
1 0 0 0 =>SUM (8)
2.2. BORROW SAVE ADDER
In Borrow Save Adder, 4 to 2 compressor is used to minimize the output. The carry-out from one
FA is connected as carry-in to another FA in cascade form so that delay is minimized.
In RCA, carry propagation from previous full adder to nearby full adder, the delay is maximized. To
overcome this problem, BSA technique is used to achieve minimum delay compared to RCA.
In BSA, all full adders can perform their operation at a same time since they are not connected in
series so the delay becomes minimized. The architecture of BSA is shown in fig.2.
1st International Conference on New Scientific Creations in Engineering and Technology (ICNSCET-19)
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Fig 2: Borrow save adder
The Borrow Save Adder employs the radix 2 encoding over the digit set S= [-1, 0, 1] also known as
borrow save encoding. In borrow save encoding, each digits Xi at ith bit position is represented by a
pair of bits (Xin, Xip), with positive and negative bits and Xi=Xip-Xin belongs to S.
2.2.1. ILLUSTRATION OF BSA
In borrow save adder, let us consider 4 input Xp,Xn,Yp,Yn where Xp and Yp is taken as
positive , Xn and Yn is taken as negative which is nothing but the input is inverted before giving to
full adder.
The inputs are given as
Xp=0 1 1 1; Xn=0 0 0 0
Yp=0 0 0 1; Yn=0 0 0 0
STEP-1: Taking complement of Xn, Yn
Xn’=1 1 1 1
Yn’=1 1 1 1
STEP-2: STEP-3: Add Yn’, Yp, Xn’
STEP-4: Sp XOR Sn
Spout = 1 1 1 0
Snout’= 0 1 1 0
1 0 0 0 =>SOUT (8)
From the step-2, the sum out and carry out is given as input in step-3 and input S, Xp, C is added, it
produces Snout’ and Spout. The counter operation in borrow save adder domain using
Inputs
Output
Sum Xp Carry Snout’ Spout
1 1 1 0 1
0 1 1 1 1
0 1 1 1 1
0 0 1 0 0
Inputs
Output
Yn’ Yp Xn’ Sum Carry
1 1 1 1 1
1 0 1 0 1
1 0 1 0 1
1 0 1 0 1
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X={(0,0),(0,1),(0,1),(0,1)} and Y={(0,0),(0,0),(0,0),(0,1)} is the representation for seven and one
respectively, results to the sum={(0,1),(1,1),(1,1),(0,0)} where Spout=1110 and Snout=0110 is
computed with a ripple effect of ti only in a neighbour bit position.
2.3. MODIFIED BORROW SAVE ADDER (BSA’)
In Borrow Save Adder, carry is propagated to full adder which are in parallel form but in
modified form of BSA, carry in FA1 is propagated to nearby full adder FA2 but in FA2 the carry is
propagated to FA7.In first row, the operation of FA1 and FA3 perform simultaneously whereas in
FA2 and FA4 operation does not exists until operation in FA1 and FA4 is completed. Due to this
process area becomes maximized. The architecture of modified BSA is shown in fig.3.
Fig 3: Modified Form of BSA
2.3.1. ILLUSTRATION OF MODIFIED BSA
In modified borrow save adder, let us consider 4 input Xp,Xn,Yp,Yn where Xp and Yp is
taken as positive , Xn and Yn is taken as negative which is nothing but the input is inverted before
giving to full adder. The input is taken as
Xp=0 1 1 1 Xn=0 0 0 0
Yp=0 0 0 1 Yn=0 0 0 0
STEP-1: Taking complement of Xn, Yn
Xn’=1 1 1 1
Yn’=1 1 1 1
STEP-2: STEP-3: Add Yn’, Yp, Xn’
Cells
Inputs
Output
Yn’ Yp Xn’ Sum Carry
FA 1 1 1 1 1 1
FA 3 1 0 1 0 1
Cells
Inputs
Output
Yn’ Xn’ C1 Sum(2) Carry(2)
FA 2 1 1 1 1 1
FA 4 1 1 1 1 1
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STEP-4: STEP-5:
Cells
Inputs
Output
Yn’ Xn’ C1 Sum’(3) Carry(3)
FA 5 1 1 1 0 1
FA 7 0 1 1 1 1
The obtained output for modified BSA is S= {(0, 1), (1, 1), (1, 1), (0, 0)}
STEP-6: Let
Sum be denoted as Sn
Carry be denoted as Sp
Sn xor Sp
Sn=0110
Sp=1110
Sout=1000 = 8
III SIMULATION RESULTS
The Ripple Carry Adder and Borrow Save Adder are designed using Xilinx ISE 8.1. The Verilog
coding is done for RCA and BSA. Thus the simulation results are obtained for both adders. These
adders are implemented in FPGA by using Vivado software tool. By using Cadence tool, analog
design is done and symbol is created for both RCA and BSA. The power, area and delay are
calculated by varying the supply voltage. In digital cadence tool, after simulation the floor planning,
placement, routing and timing analysis are done. After completing this process, the digital layout for
both ripple carry adder and borrow save adder are designed.
3.1. SIMULATION OUTPUT FOR RIPPLE CARRY ADDER
In ripple carry adder, the input is given as A[3:0]={0111} and B[3:0]={0001} and input clock pulse
is given as zero , the carry is propagated to nearby full adder , the sum output is given as S={1000}
and Cout=0. The simulation output for RCA is shown in fig4.
Fig 4: RCA Simulation
Cells
Inputs
Output
S2 Yp Xp Sum’(4) Carry(4)
FA 6 1 0 1 1 1
FA 8 1 0 0 0 1
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3.1.2. RCA SYMBOLIC REPRESENTATION
By using nmos and pmos transistor ripple carry adder is done in analog vitruso in cadence. The
complete form ripple carry adder is combined into single symbolic form. The clock pulse is given as
input and voltage supply and ground is connected. The RCA symbolic representation is shown in
fig5.
Fig 5: RCA Symbolic Representation
3.1.3. RCA LAYOUT
After completing simulation output the area, gate, power and timing analysis is done. Need to specify
the setup time and hold time .Floor planning and routing should be specified. At last RCA layout is
obtained. The RCA layout design is shown in fig 6.
Fig 6: RCA Layout
3.1.4. FPGA IMPLEMENTATION OF RCA
Field Programming Gate Array (FPGA) is implemented using Vivado software. The input is
given as A=0111 and B=0001. The sum output is eight S=1000. The FPGA implementation is shown
in fig 7.
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Fig 7: FPGA Implementation of RCA
3.2. SIMULATION OUTPUT FOR BORROW SAVE ADDER
In borrow save adder, the input is given as Xp=0111,Xn=0000 and Yp=0001,Yn=0000 input clock
pulse is given as zero , the carry is propagated to full adder which is in parallel form, the sum output
is given as S=1000 and Cout=0. The simulation output BSA is shown in fig 8.
Fig 8: BSA Simulation Output
3.2.1. BSA SYMBOLIC REPRESENTATION
By using nmos and pmos transistor ripple carry adder is done in analog vitruso in cadence.
The complete form borrow save adder is combined into single symbolic form. The clock pulse is
given as input and voltage supply and ground is connected. The BSA symbolic representation is
shown in fig 9.
Fig 9: BSA Symbolic Representation
3.2.2. LAYOUT FOR BSA AND MODIFIED BSA
After completing simulation output the area, gate, power and timing analysis is done. Need to specify
the setup time and hold time. Floor planning and routing should be specified. At last BSA and
modified BSA layout is obtained. The layout design for BSA and modified BSA is shown in fig10
and fig 11.
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Fig 10: BSA Layout
Fig 11: Modified BSA layout
On comparing BSA and modified form of BSA, the area and power is minimized in modified BSA.
The delay is lesser in BSA. Table 1: Performance Analysis
By varying supply voltage, the performance of power and delay is calculated and compared between
borrow save adder and ripple carry adder
Table 2: Power and Delay analysis by varying supply voltage
3.2.3. FPGA IMPLEMENTATION:
Field Programming Gate Array (FPGA) is implemented using Vivado software. The input is given as
Xp=0111, Xn=0000 and Yp=0001, Yn=0000.The sum output, Spout=0111 and Snout=0110. The
Xor operation is done between Spout and Snout. Finally Sout=Spout-Snout=1000. The FPGA
implementation is shown in fig 12.
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Fig 12: FPGA implementation of BSA
IV. CONCLUSION
The Ripple Carry Adder and Borrow Save Adder are designed and it is implemented in FPGA kit.
The digital layout has been designed using cadence software tool. By varying the supply voltage the
parameter such as power, delay and area are calculated. This shows that Borrow Save Adder
achieves three times smaller delay than Ripple Carry Adder at nominal supply voltage. Furthermore
it is possible to reduce the supply voltage of BSA, attaining the delay constraints imposed by the
delay characteristics of RCA as well as reducing significantly power dissipation. Finally simple
interconnections lead to a reduced normalized delay variation for Borrow Save Adder.
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