deog-kyoon jeong seoul national university [email protected] high-speed serial link

Deog-Kyoon JeongSeoul National University

[email protected]

High-Speed Serial Link

Integrated System Design Lab.

2

Introduction High-speed I/O overview Hot design issues Design examples Summary

Outline


3

Introduction

Moore’s law– Performance & density improvement in digital system

100

101

102

103

104

105

106

107

108

1980

1984

1988

1992

1996

2000

2004

Gates densit

y

100

101

102

103

104

1980

1984

1988

1992

1996

2000

2004

CPU per

form

ance


4

Introduction

Moore’s law

100

101

102

103

104

1980

1984

1988

1992

1996

2000

2004

CPU per

form

ance

Memory access

100

101

102

103

104

105

106

107

108

1980

1984

1988

1992

1996

2000

2004

Gates densit

y

Signal pins

Growing gap limits system performance!!


5

Digital System Performance

Communication - bound

Communication - bound

Computation - bound

Computation - bound

Performance bottleneck– The cost of arithmetic operation is cheap now

“Pentium Pro”10 ~ 20 cycles / Arithmetic operation

70 cycles / DRAM access

“Pentium 4”20 ~ 30 cycles / Arithmetic operation

500 ~ 600 cycles / DRAM access


6

Computing System

High-speed I/O is needed everywhere

NorthBridge

NorthBridge

CPU

SouthBridge

SouthBridge

MemoryGraphic

Disk

LAN

Display

Switch

Local I/OLong distance

SAN


7

Parallel Bus & Serial Link

Group data (Bus) Source synchronous Matched trace

Parallel Bus

Core I/O

Clock

Data

CoreI/O

Serial Link

Core I/O

SerialData

CoreI/O

Single trace Plesiochronous Clock embedded in data Clock & data recovery


8

Parallel vs. Serial

Parallel Bus Serial Link

Hardware Complexity

Low High

Latency Short Long

Speed ~ 200Mbps / pin~ 10Gbps / pin

or more

Manufacturing

CostHigh Low

World is moving toward “serial link” or “serial-link-like parallel bus” !!


9

Serial Link Architecture

Receiver

Transmitter

PLL

Framer

PCS Serializer

Deframer

Clock recovery

Channel

PCSDeserializer

Transmitter + Receiver= Transceiver


10

Link Component

PhaseDetector

Loop-Filter

Voltage-ControlledOscillator

M

CKi

( fin )Vctrerror CKo

( fout )

Phase-locked Loop (PLL)

Frequency multiplication: fout = M·fin

Jitter filter Zero-delay buffer


11

Link Component

High-speed, low voltage swing interface

Usually, differential Small swing - ~ several hundreds mV

Z 0Z 0

Channel

DC block

Termination( R = Z0 )VTT VRR

ToCDR

Driver Limiting amp


12

Link Component

Clock & data recovery (CDR) circuits

NRZ PhaseDetector

Loop-Filter


DiVctrerror

Do

CKr

Decision circuit

Di

Do

CKr

0 1 1 0 1 0 0 1 0 0 0


13

Link Performance Metric

Eye diagram & jitter

Random bit sequence

Tbit

Eye diagram

TbitTiming uncertainty : Jitter

Jitter histogram

Ideal Realistic


14


Eye diagram example – Near end & far end

PLL

Framer

Deframer

Clock recovery

Channel


15


Bit-error rate (BER)– In most serial link standards, BER < 10-12 is specified

Eye diagram

Jitter histogram

Recovered clock

Bit error!!

Jitter PDF = f(x)

UI

UI

dxxfdxxfBER5.0

5.0

)()(

UI

UI

dxxfdxxfBER5.0

5.0

)()(


16

High-Speed Link Standards

NorthBridge

NorthBridge

CPU

SouthBridge

SouthBridge

MemoryGraphic

Disk

LAN

Display

Switch

Local I/O

SAN

DVI

LVDS

Ethernet

SATA

SONET/SDH

FibreChannel

InfiniBand

PCI Express

HyperTransport

RDRAM

XDR


17

Industry Roadmaps

0.1G 1G 10G 100G

Data-rateEthernet

SONET/SDHFast Ethernet Gigabit Ethernet 10G Ethernet

OC-48 OC-192 OC-768SATA

OC-12

XAUI

Gen1 Gen2 Gen3PCI Express

PCIe1.0 PCIe2.0(?)Fibre Channel

FC-PI-1 FC-PI-2 10GFCDVI

VGA UXGASXGA

Year 2005, world is here!!


18

Digital Visual Interface (DVI)

PC display – CRT (analog) LCD (digital) DVI – Digital Visual Interface

Analog Digital


19

Digital Visual Interface (DVI)

TMDS– Transition minimized differential signaling– EMI reduction

TMD

Sen

code

r

PLL

Gra

phic

cont

rolle

r

TMD

Sde

code

r

PLL

Dis

play

cont

rolle

r


20

High Definition Multimedia Interface (HDMI) HDMI

– High-definition multi-media interface– Digital video + multi-channel audio interface for

consumer electronics– Compatible with DVI


21

Serial ATA (SATA)

Next generation ATA bus within PC box Eliminates fat ATA cables Point-to-point connection – 1.5G/3G/6G

Parallel ATA cabling Serial ATA cabling


22

Transceiver Chip Design

Technology– CMOS, InP, GaAs, SiGe, BiCMOS …– CMOS will be the eventual winner – Low cost, high-

integrity

Speed Power consumption Area Level of integration

– Mixed-signal SoC – Serial link interface + digital circuitry

Trade-off!!


23

Hot Design Issues

PLL

Framer

Deframer

Clock recovery

CMOS serial link transceiver


24

Hot Design Issues

PLL

Framer

Deframer

Clock recovery

CMOS serial link transceiver

Precise-timing generation- High-frequency, low jitter PLL

High-performance CDR- High-speed NRZ PD- Various CDR architectures

High-speed CMOS circuits- Logic gates, analog buffer

Channel loss compensation- Equalizer


25

Precise Timing generation

VCO noise PLL jitter Data eye jitter Low noise, high-frequency VCO is required

PhaseDetector

Loop-Filter


M

CKi

( fin )Vctrerror CKo

( fout )


26

Voltage-Controlled Oscillator

Poor Noise Good

Low Frequency High

Wide Tuning range Narrow

Low Cost High

Ring oscillator

M stages

dMTf

2

1

Td = C·V / I

LC tank oscillator

Parasitic resistance

Negative gm

On-chip spiral LOn-chip varactor

varLCf

21


27

High-Speed CMOS Circuits

Current-mode logic (CML)

ZL

NMOSLogic

• R• R + L• R + T-coil

CMOS logic

NMOSPull-down

PMOSPull-up

Complementary

Intermediate Speed Fast

Small Area Large

Small Power consumption Large

High-speed logic gates


28

High-Speed CMOS Circuits

High-speed buffer with on-chip inductor– Shunt peaking – Inserts a zero at high frequency– Series peaking – Isolates the buffer output node from

load capacitance

Normal Shunt peaking

Shunt peaking

Shunt seriespeaking

Series peaking

Shunt double-series peaking

Series peaking


29

High-Speed CDR – NRZ PD

Hogge phase-detector – Linear PD

Full-rate operation Matched up/down when locked – Less noisy

D Q D Q

DN

UP

CK

D

A

B

DCKABUPDN

Area difference Phase errorVery short pulse!!

Phase error – Clock early


30

High-Speed CDR – NRZ PD

Alexander phase-detector – Binary PD

With multi-phase clock – Time interleaving Bang-bang control – Noisy

D0 D1

A BT

Clock early

D0 D1

A BT

Clock late

UPDN

D Q D Q

D Q D Q

B

A

DN

UP

T

CK

D


31

High-Speed CDR – Architectures

PLL-based CDR

1 PLL / channel – Precise phase control Suitable for high-speed, high-performance

system

NRZ PhaseDetector

Loop-Filter


DiVctrerror

Do

CKr

Decision circuit

Either linear or binary


32

Channel Loss

Band-limited channel– Bonding wire, PCB trace, connector, cable …

Skin effect Dielectric loss

0 2 4 6 8 10

-60

-50

-40

-30

-20

-10

0

frequency [GHz]

Att

enu

atio

n [

dB

]

9" FR4, via stub

26" FR4,via stub

26" FR4

9" FR4


33

Channel Loss Effect

Inter-symbol interference (ISI)

0 0 0 1 0 1 1 1Time-4TB -3TB -2TB -TB TB 2TB 3TB 4TB0

Amplitude


34

Channel Loss Compensation TX – Pre-emphasis

Withpre-emphasis

Withoutpre-emphasis


35

Channel Loss Compensation

RX – Equalization

Continuous time equalizer

g

Din DoutHigh-pass filter

Capacitivedegeneration


36

Design Examples

40Gbps transmitter– Process – 0.13 CMOS– Power – 2.8W– Area – 2.5 3.6 mm2

Features– 20G standing-wave VCO– Shunt-double series

peaking at 10/20/40G buffers

– Active feedback at 20G divider

– 410 on-chip spiral inductors


37

Design Examples 40G transmitter – Standing wave VCO

differentialshort

L

VBIAS

VCTRL

MOS varactors

coupled microstrips

complementary cross-coupled VCO

Varactors


38

Design Examples

40G transmitter – test results

Test chip

25ps


39

Design Examples

Features– 10G LC-tank VCO– PLL-based 10G CDR– DLL-based quad 3.125G

CDR (XAUI)– Integrated with digital

control core

10G Ethernet PHY with XAUI interface– Process – 0.13 CMOS– Power – 900mW– Area – 5 5 mm2


40

Design Examples

3.5G continuous time adaptive equalizer– Process – 0.18 CMOS– Area – 0.48 0.73 mm2– Power – 80mW @ 3.5G

Cable input Cable output Equalizer output

Features– ~ 3.5G – Adaptive mode– ~ 5G – Manual mode


41

Summary

Now, digital system performance is bounded by system I/O bandwidth

In industry, serial link I/O is going mainstream

Toward low-cost, high-bandwidth system I/O, we should overcome several physical limitations such as– Jitter & noise – Channel loss– Device speed

deog-kyoon jeong seoul national university [email protected] high-speed serial link

Documents

serial link standards

cycles arithmetic operation500

eventual winner low

jitter pdf

differentialsmall swing

bicmos cmos

fibre channelfcpi

consumer electronicscompatible