delta sigma broadband communication

7/23/2019 Delta Sigma Broadband Communication

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Feed-forward Modulators Topologies Design for

Broadband Communications Applications

Houda Daoud, IEEE Student Member, Samir Ben salem, IEEE Member, Sonia Zouari, IEEE Student Member andMourad Loulou, IEEE Senior Member

Information Technologies and Electronics Laboratory

National Engineering School of Sfax, B.P.W, Sfax, Tunisia

Emails: [email protected], [email protected], [email protected], [email protected]

AbstractThis paper presents a design methodology for low-

distortions (feed-forward) Delta-Sigma () modulators

topologies used in next generations wireless applications.

Thus, optimized folded cascode OTA and telescopic OTA

gain-boosting are selected to implement the switched capacitor

(SC) integrator. First, a second order modulator is

implemented for 2MHz bandwidth. Second, a 2-2 cascaded modulator is designed for 2MHz and 10MHz bandwidths in

order to improve the modulator performances. These

modulators are implemented using system-level simulations as

well as device-level simulations implemented with SC circuits

in AMS 0.35m CMOS process. Device-level simulations

results indicate that the 2nd and the 2-2 cascaded

modulators achieve respectively SNRs of 43dB and 38dB over

bandwidths of 2MHz and 10MHz with over-sampling ratios

16 and 8.

Key words: modulator design, feed-forward signal path,

folded cascode OTA, telescopic OTA gain-boosted,

optimization, large bandwidth.

I.

INTRODUCTIONThe rapid growth in wireless communication systems

requiring higher capacities and data rates has motivated thedevelopment of new generation wireless transceivers. Toface the requirements of new forthcoming protocols,flexible receiver architecture is implemented using thesoftware defined radio (SDR) [1, 2]. The SDR aims to

performing the signal digitalization as near as possible tothe antenna, hence the digital programmable hardware,such as digital signal processors (DSPs) can be used, butcircuits requirements are increased. To alleviate the analogcircuits demands, the downconversion is performed intothe baseband. The analog/digital converter (ADC) which is

the final analog block of an analog baseband front-endreceiver, directly influences its performances. Among thediversity of ADCs architectures, modulator is the most

promising candidate to meet the needs of emerging multi-mode receivers [3]. The objective of this work is toevaluate the performances of wide band modulatorstopologies when designed using optimized OTA circuits viaHeuristic program. In fact, with the intensive ongoingresearch on modulators, data acquisition systemsrequire high-speed, high-resolution and low-power converters that are more challenging for SDRimplementation to operate in large signal bandwidths.

The SC technique makes the CMOS analog circuitsdesign more accurate and robust. In this context,

performances objectives of 2MHz/ 10MHz signalsbandwidths and 10bits/ 8-11bits resolutions are assumed inthis work in order to fulfill the requirements of WCDMA

and WLAN standards [4]. To achieve the targetedperformances objectives, folded cascode and telescopicgain-boosted OTAs architectures optimizing throughHeuristic Algorithm are investigated to design a 2nd orderand a 2-2 cascaded feed-forward modulators topologieswhich are highly suitable for wide band radio applications.This paper describes a methodology to design low-distortion modulators for wide bandwidths. The SCintegrator is implemented using the optimized OTAcircuits. The paper is organized as follows. Section II

presents the design methodology for modulator. Insection III, the performances of folded cascode andtelescopic gain-boosting OTAs circuits optimized viaHeuristic Algorithm are introduced. The implementation of

2nd

order and 2-2 cascaded feed-forward modulatorstopologies for wide bandwidths is presented in section IV.Finally, conclusions are reported in section V.

II. DESIGNMETHODOLOGYFORMODULATORS

In this section, a design methodology is proposed todetermine the design parameters of each modulatoranalog block. As it can be seen from fig. 1, firstly, we optfor the modulator topology for the reason that it is

modulator

architecture

Specifications

SC integrator

design

Comparator

design

Experimental results

Performances

comparisons

Clocks

Switches

Optimized coefficients

Optimized OTA

Device- level

design

System - level

design

OSR

Bandwidth

Sampling frequency

Resolution

Hysteresis Power consumption

Order L Number of bits B

Figure 1. Flow chart design of modulator

978-1-4577-1846-5/11/$26.00 2011 IEEE 69


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robust to non-idealities of circuit components [5]. Byvarying the order L and the number of bits B in thequantizer, a wide band topology could be performed.Secondly, we fix the specifications including the

bandwidth, the over-sampling ratio, the resolution and thesampling frequency. Using optimized OTAs circuits, the

SC integrator is then implemented taking the clocks andswitches design and the optimized coefficients intoconsideration. After designing the quantizer, the chosentopology is simulated using MATLAB software andORCAD PSPICE (CMOS 0.35m process). Finally, acomparison of modulator performances is made

between the two used tools.

III. OPTIMIZED OTAS CIRCUITS SELECTION

The OTA which constitute the core of the SC integratoris the most critical block to implement performant modulator [6]. Our objective is to select topologies that canmeet the integrator requirements at minimum powerconsumption. First, both high output swing and low noiseallowed us to optimize the folded cascode OTA withPMOS devices input shown in fig. 2 (a). Second, to obtainthe desired static gain, the gain-boosting technique isadopted for telescopic OTA (Fig. 2 (b)) [7]. The two OTAscircuits are optimized using the optimization processdescribed in [8]. The performances of folded cascode OTAand telescopic OTA gain-boosted are respectivelysummarized in table I and table II. The OTA circuit

performances collected in table II show that the use of gain-boosting technique enables us to optimize high DC gainand large GBW OTA circuit without scarifying its margin

5M

3M 4M

6M

1M

8M

10M

2M

7M

9M

ssV

biasI

inV +

inV -

outV -

outV +

1V

2V

3V

4V

ddV ddV

ssV

7

M

2M

biasI

8

M

5M 6M

3M 4M

1M

+_

+_

_+

_+

inV +

inV _

outV - outV

+

1V

1A

2A

(a) (b)

Figure 2. (a) Folded cascode OTA, (b) Telescopic OTA gain-boosted

TABLE I.

THE PERFORMANCES SUMMARY OF FOLDED CASCODE OTA

DC Gain (dB) 78

GBW (CL=2pF) (MHz) 306

Phase margin (degrees) 67

Slew Rate (V/s) 187

Power consumption (mW) 9.3

Supply voltage(V) 1.3

TABLE II.

THE PERFORMANCES SUMMARY OF TELESCOPIC GAIN-BOOSTED OTA

DC Gain (dB) 96

GBW (CL=2pF) (MHz) 487Phase margin (degrees) 58

Slew Rate (V/s) 300

Power consumption (mW) 12

Supply voltage(V) 1.4

phase. We conclude that the folded cascode OTA andtelescopic OTA gain-boosted circuits are optimizedrespectively for medium and large bandwidths modulators.

IV. FEED-FORWARDMODULATORS

IMPLEMENTATIONThis work is focused on the design of modulators

for wide band applications. Table III summarizes thechannel bandwidth and resolution requirements providedfrom performed researches on base-band ADCspecifications [4, 9, 10]. Traditional modulator architectureis increasingly sensitive to circuits imperfections. Recently,it has become very popular to make use of low-distortionswing suppression modulator topology [11]. Fig. 3depicts a 2

ndorder modulator with feed-forward signal

path that we choose because of its relaxed requirements onthe analog building blocks.

A. Second order feed-forwardmodulatordesign

Targeting on the requirements of broadbandtelecommunication ADC, we want to design a 2

ndorder

modulator for 2MHz bandwidth (table III). The output ofthe modulator is given by:

( ) ( )2

-1Y z = X + 1- z E (1)

Where X, Y and E represent respectively the input signal,the output signal and the quantization noise. Both of

bandwidth and resolution are expressed by (2) and (3):

Sf

B =2OSR

(2)

( )SNR dB -1.76ENOB=

6.02

(3)

Where fS, OSR and SNR are respectively the samplingfrequency, the over-sampling ratio and the signal-to-noiseratio. The figure of merit is given by:

ENOB

PFOM =

2 .2.BS (4)

Where P is the modulator power consumption. To achievethe best performance and maintain loop stability, loopcoefficients must be optimized. We use the optimized loop

coefficients presented in table IV [12]. To perform asystem-level simulation of the modulator, the chosenarchitecture was simulated using MATLAB blocks. Fig. 4shows the output spectrum of the modulator for an inputfrequency of 1MHz, a sampling frequency of 64MHz andan OSR of 16. Simulation results indicate that the chosenarchitecture achieves a SNR of 44.6dB and an ENOB of7bits for 2MHz bandwidth. The linear model described infig. 3 is implemented into SC circuits, as represented in fig.5 using AMS CMOS 0.35m process. The most important

building block of a modulator is the SC integrator. Theoptimized folded cascode OTA is used to implement theintegrators.

TABLE III.

WIRELESS COMMUNICATION ADC REQUIREMENTS

Channel bandwidth (MHz) Resolution (Bits)

2 10

10 8-11

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+

-1z

-11-z

X

+1a

-1z

-11-z

2a 2c

1c

E

Y

Figure 3. Low-distortion topology block diagram

TABLE IV.

LOOP COEFFICIENTS FOR SINGLE-BIT FEED-FORWARDMODULATOR

Loopcoefficients

a = [0.3, 0.7] a = [0.3, 0.7] a = [0.3, 0.7]

c = [2, 1] c = [1, 1, 1] c = [1, 1, 1, 2]

Loop order 2 3 4

OSR SNRp OL SNRp OL SNRp OL

16 45 0.95 41 0.85 22 0.9

32 62 0.9 63 0.85 63 0.85

The switches used in the integrator are implemented withCMOS transmission gate where two non-overlap clocks

phases are needed. In order to reduce the influence ofcharge injection, a delayed signal is needed for each clock

phase. The quantizer presents a hysteresis of 976.7V/Vwhich is less than 0.5*LSB, a propagation time of 3.8nsand a power consumption of 36.5pW (Fig. 6). The single-

bit DAC is a simple switch network connected to referencevoltages. The values of sampling and integration capacitorsare (1pF, 1pF) and (3.3pF, 1.42pF). From fig. 7, the SNRand the ENOB which values are respectively about of43dB/ 3.3dBFS and 6.85bits are close to system-level

performances with an error deviation less than 4%. In 2nd

order single-loop modulators, stability can be easilyachieved and modulator performances are less sensitive to

OTA non-idealities [12]. In order to satisfy the largebandwidth (10MHz) and the resolution requirements givenby table III, the modulator needs to be of order of three ofmore. Unfortunately, high order single-stages modulators suffer from stability issues, so they are replaced

by cascaded modulators to improve the SNR [14]. In thenext section, we will focus on the implementation of the 2-2 cascaded feed-forward modulator.

0 0.5 1 1.5 2

-120

-100

-80

-60

-40

-20

0

Frequency (MHz)

PSD(

dB)

Figure 4. PSD of the 2nd order modulator using MATLAB blocks

S1C

1dF

2dF

+

inV +

-

-

+OTA1

1F

2F

2dF

-

inV

+

refV

-

ref

V

f1C

S2C1dF2d

F

OTA2

+

-

-

+OTA2

2dF

f2C

fd1C1

F

2F

2F

2F

2F

1dF

1dF

2dF

2dF fd2C

fd1C

fd2C

f3C

+

refV

-

refV

-

refV

+

refV

+

outV

-

outV

1S

S1C

f1C

S2C

f2C

f3C

1S

1dF

2F

1F

1F

2F

1dF 2F

1F

1F

Figure 5. The 2ndorder feed-forward single-bit SC modulator

1F

1F

1F

1F

+

inV -

inV

+

outV

-

outV

ssV

ddV

1M

2M

3M 4

M

5M

6M

7M

8M 9M 10M

11M

12M

13M

14M

Figure 6. Regenerative quantizer

0 0.5 1 1.5 2

x 106

-100

-80

-60

-40

-20

0

Frequency (Hz)

PSD(

dB)

Figure 7. PSD of the 2nd order single-bit modulator device-level

B. 2-2 cascaded feed-forwardmodulatordesign

Cascaded modulators realize high-order noiseshaping by cascading stages of 2

nd or 1

st order to avoid

instability. Using loop coefficients collected in table V, thesimulation of the 2-2 cascaded feed-forward modulatoris carried out using a set of Simulink blocks (Fig. 8). Theoutput of the modulator is given by:

( ) ( ) ( ) ( )4

-2 -1

2 2Y z = X z z + e 1- z E z (5)

e2 is the digital coefficient. The high order modulatorincreases circuits complexity and the requirements ofanalog building blocks become more demanding for highersampling frequency. For wide bandwidth of 10MHz, theOSR cannot be very high because the achievable clockfrequency is constrained by the process. The outputspectrum of the modulator is presented for a samplingfrequency of 160MHz, an OSR of 8 and 16384 samples(Fig. 9). It reveals a SNR and an ENOB respectively ofabout 50dB and 8bits. From fig. 9, the 8.5MHz input

frequency is chosen close to the 10MHz bandwidth tofurther improve the modulator performances. The 2-2cascaded feed-forward modulator has been designedafter, in AMS 0.35m CMOS process. In SC cascaded modulators, the main non-idealities considered are finiteand non-linear DC gain, slew rate and gain-bandwidthlimitations, OTA saturation voltage, OTA input referred

+

-1z

-11-z

X

+

1a -1z

-11-z

2a

2c

1c

1E

+

-1z

-11-z+

3a -1z-1

1-z

4a 4c

3c

2E

1e

1y

2y

digital cancellation

Y

+

1H

2H

-1z

-1z

-1z

-1z + +2e

2

1 2 1

1e =

aa e

Figure 8. The 2-2 cascaded feed-forward modulator block diagram

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TABLE V.

LOOP COEFFICIENTS FOR THE CASCADED 2-2 FEED-FORWARD SINGLE-BIT MODULATOR

Loop coefficients(a1, a2, a3, a4, c1, c2, c3, c4, e1, e2)

(0.4, 0.8, 0.4, 0.8, 2, 1, 2, 1, 1, 3.125)

OSR SNRp OL

16 65 0.95

32 92 0.89

0 2 4 6 8 10-120

-100

-80

-60

-40

-20

0

Frequency (MHz)

PSD(

dB)

8 8.5 9-100

-50

0

Frequency (MHz)

PSD(

dB)

Figure 9. PSD of the 2-2 cascadedmodulator system-level

noise, kT/CS noise and capacitor mismatch which candegrade the modulator performances. The used feed-forward signal path has reduced sensitivity to OTA non-idealities. In addition, we use the optimized telescopic OTAgain-boosted with low noise, high gain and slew rate andlarge GBW that are sufficient to achieve best performances.The values of sampling and integration capacitors of thefirst stage are (1pF, 1pF) and (2.5pF, 1.25pF). Fig. 10shows the modulator output spectrum for 10MHz/-3.6dBFSat a sampling frequency of 160MHz. Simulations results

present a SNR and an ENOB respectively of about 38.3dBand 6bits. Table VI resumes the performances of both of 2nd

order and 2-2 cascaded modulators. We point out thatthe use of folded cascode OTA has allowed to achieve thedesired performance when designing the 2

nd order

modulator. Despite the increase of modulator stages toimprove its performances, the capacitor mismatch betweenstages and the non-linear capacity degrade them. The powerconsumption is increased from 18.7mW to 48mW becauseof the increased number of used OTAs and the highsampling frequency that requires the design of large

bandwidth OTA circuit.

V. CONCLUSION

2nd

order and 2-2 cascaded SC modulators have

been implemented inMATLAB software and AMS 0.35mCMOS process for use in wireless receivers. The

modulators topologies involve two key design issues. Oneis the modulator with feed-forward signal path, which

has reduced sensitivity to OTA non-idealities.

0 2 4 6 8 10

x 106

-100

-80

-60

-40

-20

0

Frequency (Hz)

PSD(

dB)

8 8.5 9

x 106

-80

-60

-40

-20

0

Frequency (Hz)

PSD(

dB)

Figure 10. PSD of the 2-2 cascaded modulator device-level

TABLE VI.

SUMMARY OF SINGLE-BIT FEED-FORWARDMODULATORPERFORMANCES

Feed-forward modulator topology

2ndorder 2-2 cascaded

Design modeSystemlevel

Devicelevel

Systemlevel

Devicelevel

Signal Bandwidth (MHz) 2 10Sampling frequency (MHz) 64 160

OSR 16 8

SNR 44.6 43 50 38.3

ENOB 7 6.85 8 6

Power consumption (mW) - 19 - 48.3

FOM (pJ/conversion) - 41 - 37.7

Process/ Supply voltage 0.35m/ 2.6V 0.35m/ 2.8V

The other key issue is the selected OTAs architecturesoptimizing through Heuristic Algorithm to meet theintegrator requirements. For 2MHz bandwidth, system-level simulation results have confirmed that both SNR andENOB are approximately saved compared to device-levelsimulation results of the 2

nd order modulator. The 2-2

cascaded modulator implemented recurring to SCcircuits and simulated at device level consumes 48mW andachieves SNR of about 38dB that is degraded comparedwith system-level design. Future works would involve theuse of multi-bits quantizers to design wide band modulator with high performances for flexible receivers.

REFERENCES

[1] M. Ismail, D. Rodrguez, "Radio design in nanometer technologies",Springer, 326 pages, 2006.

[2] P. Chatzimisios, "Mobile Lightweight Wireless Systems", Springer,783 pages, 2010.

[3] B. Li, "Design of Multi-bit Sigma-Delta Modulators for DigitalWireless Communications", thesis, 81 pages, Stockholm, 2003.

[4]

A. Rusu, A. Borodenkov, M. Ismail and H. Tenhunen, "A Triple-mode sigma-delta modulator for multi-standardwireless radioreceivers", Analog Integrated Circuits and Signal Processing, 47,113124, 2006.

[5] W. Ying, "Development of structural circuit macromodels andsystematic design of reconfigurable Delta Sigma modulator", thesis,state university of New York, 131 pages, 2007.

[6] H. Roh, Y. Choi and J. Roh, "a 89-dB DR 457-lW 20-kHzbandwidth delta-sigma modulator with gain-boosting OTAs",Analog Integrated Circuits and Signal Processing, page 173182,2010.

[7] D. Nageshwarrao, S. Venkata and V. Malleswara, "Gain boostedtelescopic OTA with 110dB gain and 1.8GHz UGF", InternationalJournal of Electronic Engineering Research, Vol 2 N 2, 2010.

[8] H. Daoud, S. Bennour., S. BenSalem and M. Loulou, "Low power

SC CMFB folded cascode OTA optimization", IEEE InternationalConference on Electronics, Circuits and Systems, ICECS, Malta,2008.

[9] A. Silva, J. Guilherme and N. Horta, "Reconfigurable multi-modesigmadelta modulator for 4G mobile terminalsv, VLSI journal,Elseiver, 2009.

[10] A. Rusu, M. Ismail and H. Tenhunen, "A Modified cascaded sigma-delta modulator with improved linearity", Proceedings of the IEEEComputer Society Annual Symposium on VLSI New Frontiers inVLSI Design, 2005.

[11] H. Casier, M. Steyaert, A. van Roermund, "Robust design, sigmadelta converters, RFID", Springer, 367 pages, 2011.

[12] L. Yao, M. Steyaert, W. M. C., "Low-power low-voltage sigma-deltamodulators in nanometer CMOS", springer, 2006.

[13] S. K. Nathany, "Design of fully differential discrete time delta-sigma

modulator", thesis, New York, 2006.

[14] R. H. M. van Veldhoven, A. H. M. van Roermund, "Robust sigmadelta converters: and their application in low-power highly-digitizedflexible receivers", Springer, 294 pages, 2011.

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delta sigma broadband communication

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